Manifest variables description

Manifests are python scripts with some variables of special meaning. They are used to describe your project. Below there is a list of each variable that can be used and that is interpreted by Hdlmake. If a variable is not
described here, then you can use it, but its value will not influence the program's behavior.

Top manifest variables

action

python string
Specifies the action that should be taken by hdlmake. Possible values are "synthesis" and "simulation".
When it is set to "synthesis", Hdlmake knows that the manifest is used for synthesis only and a synthesis makefile should be prepared
When it is set to "simulation", Hdlmake knows that the manifest is used for simulation only and a simulation makefile should be prepared

Universal variables

modules

python dictionary with allowed keys: svn, local, git
This is probably the most important of all variables. It should be Python's dictionary containing at most three keywords: local, svn* and git. Values connected with these keywords can be either strings or lists containing strings. Each string indicates a particular location that is correct in terms of its keyword. For example, a project consisting of 4 modules: one stored locally, one in git and two in SVN can have a manifest like the following:

@
module = {
local,
git,
svn,
"http://svn.cern.ch/trunk/oasis/client@25"\]
}
@

files

python list of strings or python string
For each module you can specify what files (or directories) should be taken into account for synthesis or simulation. The files is used to do this.

fetchto

python string
This specifies the location of repositories for fetching modules from repositories.

library

python string
Specifies a library, that all files of a module should go to.
By default set to "work".

Simulation variables

vsim_opt, vcom_opt, vlog_opt, vmap_opt

python string
These 4 variables contain run parameters for vsim, vcom, vlog and vmap respectively. They are used in makefile generation.

Synthesis variables

syn_name

python string
This is the name of the project that will be used for storage on the synthesis server. If you want to makes synthesis faster (and avoid transferring the same files all the time) you should specify some meaningful name here.

syn_device

python string
Name or number of the synthesis device.

syn_grade

python string
Speed grade of the target FPGA

syn_package

python string
Package variant of the target FPGA

syn_top

python string
Name of the top entity of HDL sources.

syn_project

python string
Specifies the main project's filename. Its extension depends on the software and vendor, that you chose. For Xilinx it should be an .xise or .ise (for older versions) file. For Quartus, a .qsf file is expected.