Hdlmake
Hdlmake generates multi-purpose makefiles for FPGA projects. It supports local and remote synthesis, simulation, fetching module dependencies from repositories, creating Quartus/ISE project files. All of this can be done with a makefile command or with Hdlmake directly. It supports modularity, scalability, use of revision control systems and code reuse. Hdlmake is free, open and distributed with GPL.
Features
Supported Tools
Tool | Synthesis | Simulation |
Xilinx ISE | Yes | n.a. |
Xilinx PlanAhead | Yes | No |
Altera Quartus | Yes | n.a. |
Microsemi (Actel) Libero | Yes | n.a. |
Lattice Semi. Diamond | Yes | n.a. |
Xilinx ISim | Yes | n.a. |
Mentor Graphics Modelsim | n.a. | Yes |
Aldec Active-HDL | n.a. | Yes |
Icarus Verilog | n.a. | Verilog |
GHDL | n.a. | VHDL |
Supported Operating Systems
Operating System | Comments |
Linux | tested on Ubuntu Precise/Trusty, CentOS 6/7 |
Windows | tested on Windows 7/8/8.1 by using Cygwin |
Supported Python Version
Version | Comments |
Python 2 | Runs on 2.6 / 2.7 |
Python 3 | To be done, not supported yet |
Documentation
Hdlmake docs are written by using Sphinx and hosted in Read the docs in order to allow dynamic updates of the different code branches and releases.
- Browse hdlmake docs
- Download hdlmake docs:
Previous Releases
ISYP
ISYP is the name of the original hdlmake release written by Pawel Szostek. Most of the projects in the Open Hardware Repository relies in this stable version, so you can find more info about it from the next link: