CERN OHR moved to GitLab and the repository structure has changed.
Fetch the test code from the new location:
git clone https://ohwr.org/project/wr-cores.git
The stable version for WRPC is 4.2, so we checkout the associated tag:
cd wr-cores
git checkout wrpc-v4.2
This version relies on Git submodule to grab the required IP Cores. This are the submodule repositories and their associated commits:
Core Module | Repository URL | Commit ID |
---|---|---|
etherbone-core | git://ohwr.org/hdl-core-lib/etherbone-core.git | 8489445985ff2afe6c72712014a92a271869f20a |
general-cores | git://ohwr.org/hdl-core-lib/general-cores.git | 5205d9754b1e0887df5914a47f8aa745e4f3c2fe |
gn4124-core | git://ohwr.org/hdl-core-lib/gn4124-core.git | 9b9625bb4270114266cd357f199d649f3d799f04 |
vme64x-core | git://ohwr.org/hdl-core-lib/vme64x-core.git | fa34d06e35ca0bfad8eac24aa51713e81639da64 |
If a user try to retrieve the required submodules by using Git, the tool will fail to grab the sources because of the repository migration. This is an example capture:
jgarcia@titan:~/Workspace/wr-cores$ git submodule init
Submodule 'ip_cores/etherbone-core' (git://ohwr.org/hdl-core-lib/etherbone-core.git) registered for path 'ip_cores/etherbone-core'
Submodule 'ip_cores/general-cores' (git://ohwr.org/hdl-core-lib/general-cores.git) registered for path 'ip_cores/general-cores'
Submodule 'ip_cores/gn4124-core' (git://ohwr.org/hdl-core-lib/gn4124-core.git) registered for path 'ip_cores/gn4124-core'
Submodule 'ip_cores/vme64x-core' (git://ohwr.org/hdl-core-lib/vme64x-core.git) registered for path 'ip_cores/vme64x-core'
jgarcia@titan:~/Workspace/wr-cores$ git submodule update
Cloning into 'ip_cores/etherbone-core'...
fatal: unable to connect to ohwr.org:
ohwr.org[0: 188.185.83.37]: errno=Connection timed out
fatal: clone of 'git://ohwr.org/hdl-core-lib/etherbone-core.git' into submodule path 'ip_cores/etherbone-core' failed
If we try to use HDLMake to fetch the required modules in a per platform basis, we will face the same problems.
In order to build our own designs, we can modify the associated Manifest.py files to point to the appropriated repositories and commits for SPEC, SVEC and VFCHD:
Core Module | Repository URL | Commit ID |
---|---|---|
etherbone-core | https://ohwr.org/project/etherbone-core.git | 8489445985ff2afe6c72712014a92a271869f20a |
general-cores | https://ohwr.org/project/general-cores.git | 5205d9754b1e0887df5914a47f8aa745e4f3c2fe |
gn4124-core | https://ohwr.org/project/gn4124-core.git | 9b9625bb4270114266cd357f199d649f3d799f04 |
vme64x-core | https://ohwr.org/project/vme64x-core.git | fa34d06e35ca0bfad8eac24aa51713e81639da64 |
In order to do this, we can apply this patch: fix_hdlmake_remote_modules.patch
diff --git a/top/clbv2_ref_design/Manifest.py b/top/clbv2_ref_design/Manifest.py
index 7c87ee1..ff3f88b 100644
--- a/top/clbv2_ref_design/Manifest.py
+++ b/top/clbv2_ref_design/Manifest.py
@@ -12,7 +12,7 @@ modules = {
"../../board/clbv2",
],
"git" : [
- "git://ohwr.org/hdl-core-lib/general-cores.git",
- "git://ohwr.org/hdl-core-lib/etherbone-core.git",
+ "https://ohwr.org/project/general-cores.git@@5205d9754b1e0887df5914a47f8aa745e4f3c2fe",
+ "https://ohwr.org/project/etherbone-core.git@@8489445985ff2afe6c72712014a92a271869f20a",
],
}
diff --git a/top/clbv3_ref_design/Manifest.py b/top/clbv3_ref_design/Manifest.py
index 227900c..4820aa3 100644
--- a/top/clbv3_ref_design/Manifest.py
+++ b/top/clbv3_ref_design/Manifest.py
@@ -12,7 +12,7 @@ modules = {
"../../board/clbv3",
],
"git" : [
- "git://ohwr.org/hdl-core-lib/general-cores.git",
- "git://ohwr.org/hdl-core-lib/etherbone-core.git",
+ "https://ohwr.org/project/general-cores.git@@5205d9754b1e0887df5914a47f8aa745e4f3c2fe",
+ "https://ohwr.org/project/etherbone-core.git@@8489445985ff2afe6c72712014a92a271869f20a",
],
}
diff --git a/top/spec_ref_design/Manifest.py b/top/spec_ref_design/Manifest.py
index 2ec34a6..05fe493 100644
--- a/top/spec_ref_design/Manifest.py
+++ b/top/spec_ref_design/Manifest.py
@@ -11,8 +11,8 @@ modules = {
"../../board/spec",
],
"git" : [
- "git://ohwr.org/hdl-core-lib/general-cores.git",
- "git://ohwr.org/hdl-core-lib/gn4124-core.git",
- "git://ohwr.org/hdl-core-lib/etherbone-core.git",
+ "https://ohwr.org/project/general-cores.git@@5205d9754b1e0887df5914a47f8aa745e4f3c2fe",
+ "https://ohwr.org/project/gn4124-core.git@@9b9625bb4270114266cd357f199d649f3d799f04",
+ "https://ohwr.org/project/etherbone-core.git@@8489445985ff2afe6c72712014a92a271869f20a",
],
}
diff --git a/top/svec_ref_design/Manifest.py b/top/svec_ref_design/Manifest.py
index 7370d85..9648287 100644
--- a/top/svec_ref_design/Manifest.py
+++ b/top/svec_ref_design/Manifest.py
@@ -11,8 +11,8 @@ modules = {
"../../board/svec",
],
"git" : [
- "git://ohwr.org/hdl-core-lib/general-cores.git",
- "git://ohwr.org/hdl-core-lib/vme64x-core.git",
- "git://ohwr.org/hdl-core-lib/etherbone-core.git",
+ "https://ohwr.org/project/general-cores.git@@5205d9754b1e0887df5914a47f8aa745e4f3c2fe",
+ "https://ohwr.org/project/vme64x-core.git@@fa34d06e35ca0bfad8eac24aa51713e81639da64",
+ "https://ohwr.org/project/etherbone-core.git@@8489445985ff2afe6c72712014a92a271869f20a",
],
}
diff --git a/top/vfchd_ref_design/Manifest.py b/top/vfchd_ref_design/Manifest.py
index 587c58c..d7fff5d 100644
--- a/top/vfchd_ref_design/Manifest.py
+++ b/top/vfchd_ref_design/Manifest.py
@@ -14,8 +14,8 @@ modules = {
"../../board/vfchd",
],
"git" : [
- "git://ohwr.org/hdl-core-lib/general-cores.git",
- "git://ohwr.org/hdl-core-lib/vme64x-core.git",
- "git://ohwr.org/hdl-core-lib/etherbone-core.git",
+ "https://ohwr.org/project/general-cores.git@@5205d9754b1e0887df5914a47f8aa745e4f3c2fe",
+ "https://ohwr.org/project/vme64x-core.git@@fa34d06e35ca0bfad8eac24aa51713e81639da64",
+ "https://ohwr.org/project/etherbone-core.git@@8489445985ff2afe6c72712014a92a271869f20a",
],
}
Test for ISE
SPEC
source ~/Xilinx/14.7/ISE_DS/settings64.sh
cd wr-cores/syn/spec_ref_design/
hdlmake fetch
hdlmake
make
In order to regenerate a complete ISE project with the user defined properties used by CERN staff, we should include the following syn_properties in the Manifest.py:
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_wr_ref_top"
syn_project = "spec_wr_ref.xise"
syn_tool = "ise"
syn_properties = [
["Auto Implementation Compile Order", "false"],
["Manual Implementation Compile Order", "true"],
["Manual Implementation Compile Order", "true"],
["Pack I/O Registers/Latches into IOBs", "For Outputs Only"],
["Generate Detailed MAP Report", "true"]]
modules = { "local" : "../../top/spec_ref_design/"}
SVEC
source ~/Xilinx/14.7/ISE_DS/settings64.sh
cd wr-cores/syn/svec_ref_design/
hdlmake fetch
hdlmake
make
CLBv2
WRPC reference design for KM3NeT Central Logic Board (CLBv2) based on Xilinx Kintex-7
source ~/Xilinx/14.7/ISE_DS/settings64.sh
cd wr-cores/syn/clbv2_ref_design/
hdlmake fetch
hdlmake
make
CLBv3
WRPC reference design for KM3NeT Central Logic Board (CLBv3) based on Xilinx Artix-7
source ~/Xilinx/14.7/ISE_DS/settings64.sh
cd wr-cores/syn/clbv3_ref_design/
hdlmake fetch
hdlmake
make