SystemVerilog files included twice in Quartus project
hdlmake seems to include the SystemVerilog files twice in my Quartus project, once as a SYSTEMVERILOG_FILE
and then later as a VERILOG_FILE
.
Quartus seems to take the latter definition and complains that they use invalid syntax.
Here is a snip of the files.tcl script:
...
set_global_assignment -name SYSTEMVERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/AddrDecoderWbSys.sv -library work
set_global_assignment -name SYSTEMVERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/I2cMuxAndExpMaster.sv -library work
set_global_assignment -name SYSTEMVERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/I2cMuxAndExpReqArbiter.sv -library work
set_global_assignment -name SYSTEMVERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/InterruptManagerWb.sv -library work
set_global_assignment -name SYSTEMVERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/OneWireBus.sv -library work
set_global_assignment -name SYSTEMVERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/SfpIdReader.sv -library work
set_global_assignment -name SYSTEMVERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/SfpStatusRegs.sv -library work
set_global_assignment -name SYSTEMVERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/SpiMaster.sv -library work
set_global_assignment -name SYSTEMVERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/SysAppIdRegs.sv -library work
set_global_assignment -name SYSTEMVERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/UniqueIdTemp.sv -library work
set_global_assignment -name SYSTEMVERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/VadjControl.sv -library work
set_global_assignment -name SYSTEMVERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/VfcConfiguration.sv -library work
set_global_assignment -name SYSTEMVERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/VfcHdSystem.sv -library work
set_global_assignment -name SYSTEMVERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/VfcHdTop.sv -library work
set_global_assignment -name SYSTEMVERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/VoltageMonitoring.sv -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/AddrDecoderWbSys.sv -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/I2cMuxAndExpMaster.sv -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/I2cMuxAndExpReqArbiter.sv -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/InterruptManagerWb.sv -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/OneWireBus.sv -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/SfpIdReader.sv -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/SfpStatusRegs.sv -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/SpiMaster.sv -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/SysAppIdRegs.sv -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/UniqueIdTemp.sv -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/VadjConfig.vh -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/VadjControl.sv -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/VfcConfiguration.sv -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/VfcHdSystem.sv -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/VfcHdTop.sv -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/VfcHdUserIo_unused.vh -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/VfcHdUserIo.vh -library work
set_global_assignment -name VERILOG_FILE ../../libs/VFC-HD_System/hdl/modules/VoltageMonitoring.sv -library work
...