so hdlmake can satisfy dependencies declared by qips

this brings additional support to describe content of QIP files

Following commmit implements to standard makefile argument
"syn_properties" as well additional 3:

- syn_instances -> set_global_instance
- syn_location_assignments-> set_location_assignment
- syn_instance_assignments -> set_instance_assignment

The original foreseen only

- syn_properties -> set_global_assignment

Following brings possibility to specify in manifest in more detail for
example logilock regions.

In order to make the parameters compatible with quartus manifest
properties 'to' and 'region_id' can be now preprended by tilde (~) to
announce that the given value of the command shall be enclosed in
quotes. This is needed as it differs from parameter to
parameter. Example:

following does not need any quotes:

set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 3A

but following does:

set_instance_assignment -name LL_MEMBER_OF "bst_sync:i_bst_sync" -to
"VfcHdApplication:i_VfcHdApplication|bran:i_bran|bst_sync:i_bst_sync"
-section_id "bst_sync:i_bst_sync"

Needed to setup certain global properties, as e.g.

set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise

lib components are ignored during dependency search

in addition to original CLEAN_TARGETS this commits as well:

- a5_pin_model_dump.txt
- *.sld

to be erased when 'make clean' is issued

This patch brings functionality of automatic detection of whether to
add or not compilation scripts for the system libraries into the
generate VUnit simulation makefile. The decision is based on presence
of "system" libs in the Manifest module.

If manifest contains "system" key in modules description, this one is
passed to the VUnit make file, which generates compilation code to the
makefile. Currently Altera libs are implemented, but framework permits
easily to extend to other libraries

reverse order for manifests picks externals first, then locals

Following commmit implements to standard makefile argument
"syn_properties" as well additional 3:

- syn_instances -> set_global_instance
- syn_location_assignments-> set_location_assignment
- syn_instance_assignments -> set_instance_assignment

The original foreseen only

- syn_properties -> set_global_assignment

Following brings possibility to specify in manifest in more detail for
example logilock regions.

In order to make the parameters compatible with quartus manifest
properties 'to' and 'region_id' can be now preprended by tilde (~) to
announce that the given value of the command shall be enclosed in
quotes. This is needed as it differs from parameter to
parameter. Example:

following does not need any quotes:

set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 3A

but following does:

set_instance_assignment -name LL_MEMBER_OF "bst_sync:i_bst_sync" -to
"VfcHdApplication:i_VfcHdApplication|bran:i_bran|bst_sync:i_bst_sync"
-section_id "bst_sync:i_bst_sync"

Needed to setup certain global properties, as e.g.

set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise

Picking wildcard support

sim_target -> target (used as well in synth)
sim_family -> syn_device (as well in synth)

into one sim_lib directory, with subdirs vhdl and verilog one can use
compiled libs in the design

lib components are ignored during dependency search

this is very specific case for the moment, but skeleton is there and
hence we can easily extend this to other compilers and use cases

In some cases the top-level is not needed for the operation, following
patch brings to all tools flag which indicates whether given tool
requires or not top-level and acts accordingly when parsin the filetree

- added hook which allows tool to modify the fileset before it is used
for further actions. This is required by VUnit, which needs additional
absolute path of incdir coming from installation place of VUnit.

- added skeleton of vunit and makefilevunit which will serve as
provider of makefile for vunit

- improved on detection of off-loaded libraries for systemverilog
files. Package detection mechanism looks different for VHDL and SV

- added new simulation target 'vunit'

in addition to original CLEAN_TARGETS this commits as well:

- a5_pin_model_dump.txt
- *.sld

to be erased when 'make clean' is issued