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Hdlmake
Commit f7ca1122 authored by Paweł Szostek's avatar Paweł Szostek
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Merge branch 'master' of ohwr.org:misc/hdl-make 

Conflicts:
	hdlmake
parents aff4c49c aceb7036
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Showing with 23 additions and 16 deletions
src/__main__.py
View file @ f7ca1122
......@@ -67,6 +67,10 @@ def main():
default=None, help="create/update an ise project including list of project"
"files")
parser.add_option("--quartus-proj", action="store_true", dest="quartus_proj",
default=None, help="create/update a quartus project including list of project"
"files")
parser.add_option("-l", "--synthesize-locally", dest="local",
default=None, action="store_true", help="perform a local synthesis")
......@@ -127,6 +131,7 @@ def main():
"fetch" : "fetch",
"make_sim" : "generate_modelsim_makefile",
"ise_proj" : "generate_ise_project",
"quartus_proj" : "generate_quartus_project",
"local" : "run_local_synthesis",
"remote": "run_remote_synthesis",
"make_fetch": "generate_fetch_makefile",
......@@ -144,7 +149,6 @@ def main():
if is_set:
sth_chosen = True
getattr(kernel, function)()
sth_chosen = True
except Exception, unknown_error :
p.echo("Oooops! We've got an error. Here is the appropriate info:\n")
p.print_version()
......
src/flow.py
View file @ f7ca1122
......@@ -297,7 +297,7 @@ class ModelsiminiReader(object):
reading_libraries = False
for line in ini:
line = line.split("")[0]
line = line.split(" ")[0]
line = line.strip()
if line == "": continue
if line.lower() == "[library]":
......
src/flow_altera.py
View file @ f7ca1122
......@@ -87,7 +87,7 @@ class QuartusProject:
return pre+'\n'+post+'\n'
def __emit_files(self):
from srcfile import VHDLFile, VerilogFile, SignalTapFile, SDCFile, DPFFile
from srcfile import VHDLFile, VerilogFile, SignalTapFile, SDCFile, QIPFile, DPFFile
tmp = "set_global_assignment -name {0} {1}"
ret = []
for f in self.files:
......@@ -99,6 +99,8 @@ class QuartusProject:
line = tmp.format("SIGNALTAP_FILE", f.rel_path())
elif isinstance(f, SDCFile):
line = tmp.format("SDC_FILE", f.rel_path())
elif isinstance(f, QIPFile):
line = tmp.format("QIP_FILE", f.rel_path())
elif isinstance(f, DPFFile):
line = tmp.format("MISC_FILE", f.rel_path())
else:
......
src/global_mod.py
View file @ f7ca1122
......@@ -22,10 +22,7 @@
options = None
top_module = None
global_target = "''"
<<<<<<< HEAD
#######
#this var is modified by the build makefile - DON'T TOUCH IT!
BUILD_ID = "2013Feb22:341efe"
=======
>>>>>>> Makefile: add release generation
######
src/makefile_writer.py
View file @ f7ca1122
......@@ -341,16 +341,14 @@ clean:
lib = vhdl.library
purename = vhdl.purename
#each .dat depends on corresponding .vhd file
self.write(os.path.join(lib, purename, "."+purename+"_"+ vhdl.extension()) + ": "+vhdl.rel_path()+'\n')
self.write(os.path.join(lib, purename, "."+purename+"_"+ vhdl.extension()) + ": " + vhdl.rel_path())
for dep_file in vhdl.dep_depends_on:
name = dep_file.purename
self.write(" \\\n"+ os.path.join(dep_file.library, name, "."+name+"_vhd"))
self.writeln()
self.writeln(' '.join(["\t\tvcom $(VCOM_FLAGS)", vhdl.vcom_opt, "-work", lib, "$< "]))
self.writeln("\t\t@mkdir -p $(dir $@) && touch $@\n")
self.writeln()
if len(vhdl.dep_depends_on) != 0:
self.write(os.path.join(lib, purename, "."+purename) +":")
for dep_file in vhdl.dep_depends_on:
name = dep_file.purename
self.write(" \\\n"+ os.path.join(dep_file.library, name, "."+name))
self.write('\n\n')
def __get_rid_of_incdirs(self, vlog_opt):
vlog_opt = self.__emit_string(vlog_opt)
......
src/srcfile.py
View file @ f7ca1122
......@@ -102,7 +102,7 @@ class SourceFile(IDependable, File):
class VHDLFile(SourceFile):
def __init__(self, path, library = None, vcom_opt = None):
SourceFile.__init__(self, path, library)
##self.__create_deps()
self.__create_deps()
if not vcom_opt:
self.vcom_opt = ""
else:
......@@ -142,7 +142,7 @@ class VHDLFile(SourceFile):
if global_mod.top_module.target == "xilinx":
std_libs = flow.ISE_STANDARD_LIBS
elif global_mod.top_module.target == "altera":
std_libs = flow.MODELSIM_STANDARD_LIBS
std_libs = flow.QUARTUS_STANDARD_LIBS
import re
try:
......@@ -277,6 +277,10 @@ class SDCFile(File):
def __init__(self, path):
File.__init__(self, path)
class QIPFile(File):
def __init__(self, path):
File.__init__(self, path)
class DPFFile(File):
def __init__(self, path):
File.__init__(self, path)
......@@ -351,7 +355,7 @@ class SourceFileFactory:
nf = None
if extension == 'vhd' or extension == 'vhdl' or extension == 'vho':
nf = VHDLFile(path, library, vcom_opt)
elif extension == 'v' or extension == 'vh' or extension == 'vo':
elif extension == 'v' or extension == 'vh' or extension == 'vo' or extension == 'vm':
nf = VerilogFile(path, library, vlog_opt, include_dirs)
elif extension == 'sv' or extension == 'svh':
nf = SVFile(path, library, vlog_opt, include_dirs)
......@@ -371,6 +375,8 @@ class SourceFileFactory:
nf = SignalTapFile(path)
elif extension == 'sdc':
nf = SDCFile(path)
elif extension == 'qip':
nf = QIPFile(path)
elif extension == 'dpf':
nf = DPFFile(path)
return nf
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