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Hdlmake
Commit f5a6d101 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Top_module and fileset are now properties of the Tool class

parent e8e42a2b
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Showing with 126 additions and 100 deletions
hdlmake/action/simulation.py
View file @ f5a6d101
...@@ -85,11 +85,12 @@ class ActionSimulation(Action): ...@@ -85,11 +85,12 @@ class ActionSimulation(Action):
dep_files = fset.filter(DepFile) dep_files = fset.filter(DepFile)
# dep_solver.solve(dep_files) # dep_solver.solve(dep_files)
# tool_object.generate_simulation_makefile(dep_files, top_module) # tool_object.generate_simulation_makefile(dep_files, top_module)
tool_object.makefile_sim_top(top_module) tool_object.makefile_setup(top_module, dep_files)
tool_object.makefile_sim_options(top_module) tool_object.makefile_sim_top()
tool_object.makefile_sim_local(top_module) tool_object.makefile_sim_options()
tool_object.makefile_sim_sources(dep_files) tool_object.makefile_sim_local()
tool_object.makefile_sim_compilation(dep_files, top_module) tool_object.makefile_sim_sources()
tool_object.makefile_sim_command(top_module) tool_object.makefile_sim_compilation()
tool_object.makefile_sim_command()
tool_object.makefile_sim_clean() tool_object.makefile_sim_clean()
tool_object.makefile_sim_phony(top_module) tool_object.makefile_sim_phony()
hdlmake/action/synthesis.py
View file @ f5a6d101
...@@ -106,12 +106,13 @@ class ActionSynthesis(Action): ...@@ -106,12 +106,13 @@ class ActionSynthesis(Action):
logging.info("Detected %d supported files that are not parseable", logging.info("Detected %d supported files that are not parseable",
len(privative_files)) len(privative_files))
fileset.add(privative_files) fileset.add(privative_files)
tool_object.makefile_includes(top_module) tool_object.makefile_setup(top_module, fileset)
tool_object.makefile_syn_top(top_module, tool_path) tool_object.makefile_includes()
tool_object.makefile_syn_tcl(top_module) tool_object.makefile_syn_top(tool_path)
tool_object.makefile_syn_files(fileset) tool_object.makefile_syn_tcl()
tool_object.makefile_syn_files()
tool_object.makefile_syn_local() tool_object.makefile_syn_local()
tool_object.makefile_syn_command(top_module) tool_object.makefile_syn_command()
tool_object.makefile_syn_build() tool_object.makefile_syn_build()
tool_object.makefile_syn_clean() tool_object.makefile_syn_clean()
tool_object.makefile_syn_phony() tool_object.makefile_syn_phony()
......
hdlmake/tools/active_hdl.py
View file @ f5a6d101
...@@ -48,8 +48,9 @@ class ToolActiveHDL(ToolSim): ...@@ -48,8 +48,9 @@ class ToolActiveHDL(ToolSim):
self._hdl_files.extend(ToolActiveHDL.HDL_FILES) self._hdl_files.extend(ToolActiveHDL.HDL_FILES)
self._clean_targets.update(ToolActiveHDL.CLEAN_TARGETS) self._clean_targets.update(ToolActiveHDL.CLEAN_TARGETS)
def makefile_sim_compilation(self, fileset, top_module): def makefile_sim_compilation(self):
"""Print Makefile compilation target for Aldec Active-HDL simulator""" """Print Makefile compilation target for Aldec Active-HDL simulator"""
fileset = self.fileset
self.writeln("simulation:") self.writeln("simulation:")
self.writeln("\t\techo \"# Active-HDL command file," self.writeln("\t\techo \"# Active-HDL command file,"
" generated by HDLMake\" > run.command") " generated by HDLMake\" > run.command")
......
hdlmake/tools/diamond.py
View file @ f5a6d101
...@@ -70,21 +70,21 @@ class ToolDiamond(ToolSyn): ...@@ -70,21 +70,21 @@ class ToolDiamond(ToolSyn):
self._clean_targets.update(ToolDiamond.CLEAN_TARGETS) self._clean_targets.update(ToolDiamond.CLEAN_TARGETS)
self._tcl_controls.update(ToolDiamond.TCL_CONTROLS) self._tcl_controls.update(ToolDiamond.TCL_CONTROLS)
def makefile_syn_tcl(self, top_module): def makefile_syn_tcl(self):
"""Create a Diamond synthesis project by TCL""" """Create a Diamond synthesis project by TCL"""
syn_device = top_module.manifest_dict["syn_device"] syn_device = self.top_module.manifest_dict["syn_device"]
syn_grade = top_module.manifest_dict["syn_grade"] syn_grade = self.top_module.manifest_dict["syn_grade"]
syn_package = top_module.manifest_dict["syn_package"] syn_package = self.top_module.manifest_dict["syn_package"]
create_tmp = self._tcl_controls["create"] create_tmp = self._tcl_controls["create"]
target = syn_device + syn_grade + syn_package target = syn_device + syn_grade + syn_package
self._tcl_controls["create"] = create_tmp.format(target.upper()) self._tcl_controls["create"] = create_tmp.format(target.upper())
super(ToolDiamond, self).makefile_syn_tcl(top_module) super(ToolDiamond, self).makefile_syn_tcl()
def makefile_syn_files(self, fileset): def makefile_syn_files(self):
"""Write the files TCL section of the Makefile""" """Write the files TCL section of the Makefile"""
hdl = 'prj_src {0} \"{1}\"' hdl = 'prj_src {0} \"{1}\"'
self.writeln("define TCL_FILES") self.writeln("define TCL_FILES")
for file_aux in fileset: for file_aux in self.fileset:
if isinstance(file_aux, LPFFile): if isinstance(file_aux, LPFFile):
self.writeln(hdl.format('add -exclude', file_aux.rel_path())) self.writeln(hdl.format('add -exclude', file_aux.rel_path()))
self.writeln(hdl.format('enable', file_aux.rel_path())) self.writeln(hdl.format('enable', file_aux.rel_path()))
......
hdlmake/tools/ghdl.py
View file @ f5a6d101
...@@ -52,10 +52,10 @@ class ToolGHDL(ToolSim): ...@@ -52,10 +52,10 @@ class ToolGHDL(ToolSim):
self._hdl_files.extend(ToolGHDL.HDL_FILES) self._hdl_files.extend(ToolGHDL.HDL_FILES)
self._clean_targets.update(ToolGHDL.CLEAN_TARGETS) self._clean_targets.update(ToolGHDL.CLEAN_TARGETS)
def makefile_sim_options(self, top_module): def makefile_sim_options(self):
"""Print the GHDL options to the Makefile""" """Print the GHDL options to the Makefile"""
if top_module.manifest_dict["ghdl_opt"]: if self.top_module.manifest_dict["ghdl_opt"]:
ghdl_opt = top_module.manifest_dict["ghdl_opt"] ghdl_opt = self.top_module.manifest_dict["ghdl_opt"]
else: else:
ghdl_opt = '' ghdl_opt = ''
ghdl_string = string.Template( ghdl_string = string.Template(
...@@ -63,8 +63,9 @@ class ToolGHDL(ToolSim): ...@@ -63,8 +63,9 @@ class ToolGHDL(ToolSim):
self.writeln(ghdl_string.substitute( self.writeln(ghdl_string.substitute(
ghdl_opt=ghdl_opt)) ghdl_opt=ghdl_opt))
def makefile_sim_compilation(self, fileset, top_module): def makefile_sim_compilation(self):
"""Print the GDHL simulation compilation target""" """Print the GDHL simulation compilation target"""
fileset = self.fileset
self.writeln("simulation:") self.writeln("simulation:")
self.writeln("\t\t# Analyze sources") self.writeln("\t\t# Analyze sources")
for vhdl in fileset.filter(VHDLFile): for vhdl in fileset.filter(VHDLFile):
......
hdlmake/tools/ise.py
View file @ f5a6d101
...@@ -99,8 +99,9 @@ class ToolISE(ToolSyn): ...@@ -99,8 +99,9 @@ class ToolISE(ToolSyn):
self._clean_targets.update(ToolISE.CLEAN_TARGETS) self._clean_targets.update(ToolISE.CLEAN_TARGETS)
self._tcl_controls.update(ToolISE.TCL_CONTROLS) self._tcl_controls.update(ToolISE.TCL_CONTROLS)
def makefile_syn_tcl(self, top_module): def makefile_syn_tcl(self):
"""Create a Xilinx synthesis project by TCL""" """Create a Xilinx synthesis project by TCL"""
top_module = self.top_module
tmp = "{0}set {1} {2}" tmp = "{0}set {1} {2}"
syn_device = top_module.manifest_dict["syn_device"] syn_device = top_module.manifest_dict["syn_device"]
syn_grade = top_module.manifest_dict["syn_grade"] syn_grade = top_module.manifest_dict["syn_grade"]
...@@ -128,13 +129,13 @@ class ToolISE(ToolSyn): ...@@ -128,13 +129,13 @@ class ToolISE(ToolSyn):
for prop in properties: for prop in properties:
create_new.append(tmp.format(prop[0], prop[1], prop[2])) create_new.append(tmp.format(prop[0], prop[1], prop[2]))
self._tcl_controls["create"] = "\n".join(create_new) self._tcl_controls["create"] = "\n".join(create_new)
super(ToolISE, self).makefile_syn_tcl(top_module) super(ToolISE, self).makefile_syn_tcl()
def makefile_syn_files(self, fileset): def makefile_syn_files(self):
"""Write the files TCL section of the Makefile""" """Write the files TCL section of the Makefile"""
hdl = "xfile add {0}" hdl = "xfile add {0}"
self.writeln("define TCL_FILES") self.writeln("define TCL_FILES")
for file_aux in fileset: for file_aux in self.fileset:
self.writeln(hdl.format(file_aux.rel_path())) self.writeln(hdl.format(file_aux.rel_path()))
self.writeln("project set top $(TOP_MODULE)") self.writeln("project set top $(TOP_MODULE)")
self.writeln("endef") self.writeln("endef")
......
hdlmake/tools/isim.py
View file @ f5a6d101
...@@ -65,8 +65,9 @@ class ToolISim(ToolSim): ...@@ -65,8 +65,9 @@ class ToolISim(ToolSim):
self._hdl_files.extend(ToolISim.HDL_FILES) self._hdl_files.extend(ToolISim.HDL_FILES)
self._clean_targets.update(ToolISim.CLEAN_TARGETS) self._clean_targets.update(ToolISim.CLEAN_TARGETS)
def makefile_sim_top(self, top_module): def makefile_sim_top(self):
"""Print the top section of the Makefile for Xilinx ISim""" """Print the top section of the Makefile for Xilinx ISim"""
top_module = self.top_module
def __get_xilinxsim_ini_dir(env): def __get_xilinxsim_ini_dir(env):
"""Get Xilinx ISim ini simulation file""" """Get Xilinx ISim ini simulation file"""
if env["isim_path"]: if env["isim_path"]:
...@@ -98,7 +99,7 @@ XILINX_INI_PATH := """ + __get_xilinxsim_ini_dir(top_module.pool.env) + ...@@ -98,7 +99,7 @@ XILINX_INI_PATH := """ + __get_xilinxsim_ini_dir(top_module.pool.env) +
""" """
""") """)
def makefile_sim_options(self, top_module): def makefile_sim_options(self):
"""Print the Xilinx ISim simulation options in the Makefile""" """Print the Xilinx ISim simulation options in the Makefile"""
def __get_rid_of_isim_incdirs(vlog_opt): def __get_rid_of_isim_incdirs(vlog_opt):
"""Clean the vlog options from include dirs""" """Clean the vlog options from include dirs"""
...@@ -121,11 +122,12 @@ XILINX_INI_PATH := """ + __get_xilinxsim_ini_dir(top_module.pool.env) + ...@@ -121,11 +122,12 @@ XILINX_INI_PATH := """ + __get_xilinxsim_ini_dir(top_module.pool.env) +
ISIM_FLAGS := ISIM_FLAGS :=
VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini """ + VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini """ +
__get_rid_of_isim_incdirs( __get_rid_of_isim_incdirs(
top_module.manifest_dict["vlog_opt"]) + """ self.top_module.manifest_dict["vlog_opt"]) + """
""") """)
def makefile_sim_compilation(self, fileset, top_module): def makefile_sim_compilation(self):
"""Print the compile simulation target for Xilinx ISim""" """Print the compile simulation target for Xilinx ISim"""
fileset = self.fileset
make_preambule_p2 = """## rules ################################# make_preambule_p2 = """## rules #################################
simulation: xilinxsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) fuse simulation: xilinxsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) fuse
$(VERILOG_OBJ): $(LIB_IND) xilinxsim.ini $(VERILOG_OBJ): $(LIB_IND) xilinxsim.ini
......
hdlmake/tools/iverilog.py
View file @ f5a6d101
...@@ -57,8 +57,10 @@ class ToolIVerilog(ToolSim): ...@@ -57,8 +57,10 @@ class ToolIVerilog(ToolSim):
self._hdl_files.extend(ToolIVerilog.HDL_FILES) self._hdl_files.extend(ToolIVerilog.HDL_FILES)
self._clean_targets.update(ToolIVerilog.CLEAN_TARGETS) self._clean_targets.update(ToolIVerilog.CLEAN_TARGETS)
def makefile_sim_compilation(self, fileset, top_module): def makefile_sim_compilation(self):
"""Generate compile simulation Makefile target for IVerilog""" """Generate compile simulation Makefile target for IVerilog"""
fileset = self.fileset
top_module = self.top_module
self.writeln("simulation:") self.writeln("simulation:")
...@@ -84,8 +86,9 @@ class ToolIVerilog(ToolSim): ...@@ -84,8 +86,9 @@ class ToolIVerilog(ToolSim):
self.writeln("\t\tiverilog $(IVERILOG_OPT) -s $(TOP_MODULE)" self.writeln("\t\tiverilog $(IVERILOG_OPT) -s $(TOP_MODULE)"
" -o $(TOP_MODULE).vvp -c run.command") " -o $(TOP_MODULE).vvp -c run.command")
def makefile_sim_options(self, top_module): def makefile_sim_options(self):
"""Print the IVerilog options to the Makefile""" """Print the IVerilog options to the Makefile"""
top_module = self.top_module
if top_module.manifest_dict["iverilog_opt"]: if top_module.manifest_dict["iverilog_opt"]:
iverilog_opt = top_module.manifest_dict["iverilog_opt"] iverilog_opt = top_module.manifest_dict["iverilog_opt"]
else: else:
......
hdlmake/tools/libero.py
View file @ f5a6d101
...@@ -72,20 +72,20 @@ class ToolLibero(ToolSyn): ...@@ -72,20 +72,20 @@ class ToolLibero(ToolSyn):
self._clean_targets.update(ToolLibero.CLEAN_TARGETS) self._clean_targets.update(ToolLibero.CLEAN_TARGETS)
self._tcl_controls.update(ToolLibero.TCL_CONTROLS) self._tcl_controls.update(ToolLibero.TCL_CONTROLS)
def makefile_syn_tcl(self, top_module): def makefile_syn_tcl(self):
"""Create a Libero synthesis project by TCL""" """Create a Libero synthesis project by TCL"""
syn_project = top_module.manifest_dict["syn_project"] syn_project = self.top_module.manifest_dict["syn_project"]
syn_device = top_module.manifest_dict["syn_device"] syn_device = self.top_module.manifest_dict["syn_device"]
syn_grade = top_module.manifest_dict["syn_grade"] syn_grade = self.top_module.manifest_dict["syn_grade"]
syn_package = top_module.manifest_dict["syn_package"] syn_package = self.top_module.manifest_dict["syn_package"]
create_tmp = self._tcl_controls["create"] create_tmp = self._tcl_controls["create"]
self._tcl_controls["create"] = create_tmp.format(syn_project, self._tcl_controls["create"] = create_tmp.format(syn_project,
syn_device.upper(), syn_device.upper(),
syn_package.upper(), syn_package.upper(),
syn_grade) syn_grade)
super(ToolLibero, self).makefile_syn_tcl(top_module) super(ToolLibero, self).makefile_syn_tcl()
def makefile_syn_files(self, fileset): def makefile_syn_files(self):
"""Write the files TCL section of the Makefile""" """Write the files TCL section of the Makefile"""
link_string = 'create_links {0} {{{1}}}' link_string = 'create_links {0} {{{1}}}'
synthesis_constraints = [] synthesis_constraints = []
...@@ -93,7 +93,7 @@ class ToolLibero(ToolSyn): ...@@ -93,7 +93,7 @@ class ToolLibero(ToolSyn):
ret = [] ret = []
ret.append("define TCL_FILES") ret.append("define TCL_FILES")
# First stage: linking files # First stage: linking files
for file_aux in fileset: for file_aux in self.fileset:
if (isinstance(file_aux, VHDLFile) or if (isinstance(file_aux, VHDLFile) or
isinstance(file_aux, VerilogFile)): isinstance(file_aux, VerilogFile)):
line = link_string.format('-hdl_source', file_aux.rel_path()) line = link_string.format('-hdl_source', file_aux.rel_path())
......
hdlmake/tools/make_sim.py
View file @ f5a6d101
...@@ -13,27 +13,28 @@ class ToolSim(ToolMakefile): ...@@ -13,27 +13,28 @@ class ToolSim(ToolMakefile):
def __init__(self): def __init__(self):
super(ToolSim, self).__init__() super(ToolSim, self).__init__()
def makefile_sim_top(self, top_module): def makefile_sim_top(self):
"""Generic method to write the simulation Makefile top section""" """Generic method to write the simulation Makefile top section"""
top_parameter = string.Template("""\ top_parameter = string.Template("""\
TOP_MODULE := ${top_module} TOP_MODULE := ${top_module}
PWD := $$(shell pwd) PWD := $$(shell pwd)
""") """)
self.writeln(top_parameter.substitute( self.writeln(top_parameter.substitute(
top_module=top_module.manifest_dict["sim_top"])) top_module=self.top_module.manifest_dict["sim_top"]))
def makefile_sim_options(self, top_module): def makefile_sim_options(self):
"""End stub method to write the synthesis Makefile options section""" """End stub method to write the synthesis Makefile options section"""
pass pass
def makefile_sim_local(self, top_module): def makefile_sim_local(self):
"""Generic method to write the simulation Makefile local target""" """Generic method to write the simulation Makefile local target"""
self.writeln("#target for performing local simulation\n" self.writeln("#target for performing local simulation\n"
"local: sim_pre_cmd simulation sim_post_cmd\n") "local: sim_pre_cmd simulation sim_post_cmd\n")
def makefile_sim_sources(self, fileset): def makefile_sim_sources(self):
"""Generic method to write the simulation Makefile HDL sources""" """Generic method to write the simulation Makefile HDL sources"""
from hdlmake.srcfile import VerilogFile, VHDLFile from hdlmake.srcfile import VerilogFile, VHDLFile
fileset = self.fileset
self.write("VERILOG_SRC := ") self.write("VERILOG_SRC := ")
for vlog in fileset.filter(VerilogFile): for vlog in fileset.filter(VerilogFile):
self.writeln(vlog.rel_path() + " \\") self.writeln(vlog.rel_path() + " \\")
...@@ -75,14 +76,14 @@ PWD := $$(shell pwd) ...@@ -75,14 +76,14 @@ PWD := $$(shell pwd)
" \\") " \\")
self.writeln() self.writeln()
def makefile_sim_command(self, top_module): def makefile_sim_command(self):
"""Generic method to write the simulation Makefile user commands""" """Generic method to write the simulation Makefile user commands"""
if top_module.manifest_dict["sim_pre_cmd"]: if self.top_module.manifest_dict["sim_pre_cmd"]:
sim_pre_cmd = top_module.manifest_dict["sim_pre_cmd"] sim_pre_cmd = self.top_module.manifest_dict["sim_pre_cmd"]
else: else:
sim_pre_cmd = '' sim_pre_cmd = ''
if top_module.manifest_dict["sim_post_cmd"]: if self.top_module.manifest_dict["sim_post_cmd"]:
sim_post_cmd = top_module.manifest_dict["sim_post_cmd"] sim_post_cmd = self.top_module.manifest_dict["sim_post_cmd"]
else: else:
sim_post_cmd = '' sim_post_cmd = ''
sim_command = string.Template("""# USER SIM COMMANDS sim_command = string.Template("""# USER SIM COMMANDS
...@@ -99,7 +100,7 @@ sim_post_cmd: ...@@ -99,7 +100,7 @@ sim_post_cmd:
self.makefile_clean() self.makefile_clean()
self.makefile_mrproper() self.makefile_mrproper()
def makefile_sim_phony(self, top_module): def makefile_sim_phony(self):
"""Print simulation PHONY target list to the Makefile""" """Print simulation PHONY target list to the Makefile"""
self.writeln( self.writeln(
".PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation") ".PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation")
hdlmake/tools/make_syn.py
View file @ f5a6d101
...@@ -13,7 +13,7 @@ class ToolSyn(ToolMakefile): ...@@ -13,7 +13,7 @@ class ToolSyn(ToolMakefile):
def __init__(self): def __init__(self):
super(ToolSyn, self).__init__() super(ToolSyn, self).__init__()
def makefile_syn_top(self, top_module, tool_path): def makefile_syn_top(self, tool_path):
"""Create the top part of the synthesis Makefile""" """Create the top part of the synthesis Makefile"""
if path_mod.check_windows(): if path_mod.check_windows():
tcl_interpreter = self._tool_info["windows_bin"] tcl_interpreter = self._tool_info["windows_bin"]
...@@ -30,12 +30,12 @@ TCL_INTERPRETER := $$(TOOL_PATH)/${tcl_interpreter} ...@@ -30,12 +30,12 @@ TCL_INTERPRETER := $$(TOOL_PATH)/${tcl_interpreter}
""") """)
self.writeln(top_parameter.substitute( self.writeln(top_parameter.substitute(
tcl_interpreter=tcl_interpreter, tcl_interpreter=tcl_interpreter,
project_name=top_module.manifest_dict["syn_project"], project_name=self.top_module.manifest_dict["syn_project"],
project_ext=self._tool_info["project_ext"], project_ext=self._tool_info["project_ext"],
tool_path=tool_path, tool_path=tool_path,
top_module=top_module.manifest_dict["syn_top"])) top_module=self.top_module.manifest_dict["syn_top"]))
def makefile_syn_tcl(self, top_module): def makefile_syn_tcl(self):
"""Create the Makefile TCL dictionary for the selected tool""" """Create the Makefile TCL dictionary for the selected tool"""
tcl_string = string.Template("""\ tcl_string = string.Template("""\
...@@ -151,7 +151,7 @@ bitstream: tcl_clean tcl_open tcl_bitstream tcl_close syn_pre_bitstream_cmd run_ ...@@ -151,7 +151,7 @@ bitstream: tcl_clean tcl_open tcl_bitstream tcl_close syn_pre_bitstream_cmd run_
""") """)
def makefile_syn_command(self, top_module): def makefile_syn_command(self):
"""Create the Makefile targets for user defined commands""" """Create the Makefile targets for user defined commands"""
syn_command = string.Template("""\ syn_command = string.Template("""\
# User defined commands # User defined commands
...@@ -187,29 +187,29 @@ syn_post_bitstream_cmd: ...@@ -187,29 +187,29 @@ syn_post_bitstream_cmd:
""") """)
self.writeln(syn_command.substitute( self.writeln(syn_command.substitute(
syn_pre_cmd=top_module.manifest_dict[ syn_pre_cmd=self.top_module.manifest_dict[
"syn_pre_cmd"], "syn_pre_cmd"],
syn_post_cmd=top_module.manifest_dict[ syn_post_cmd=self.top_module.manifest_dict[
"syn_post_cmd"], "syn_post_cmd"],
syn_pre_synthesize_cmd=top_module.manifest_dict[ syn_pre_synthesize_cmd=self.top_module.manifest_dict[
"syn_pre_synthesize_cmd"], "syn_pre_synthesize_cmd"],
syn_post_synthesize_cmd=top_module.manifest_dict[ syn_post_synthesize_cmd=self.top_module.manifest_dict[
"syn_post_synthesize_cmd"], "syn_post_synthesize_cmd"],
syn_pre_translate_cmd=top_module.manifest_dict[ syn_pre_translate_cmd=self.top_module.manifest_dict[
"syn_pre_translate_cmd"], "syn_pre_translate_cmd"],
syn_post_translate_cmd=top_module.manifest_dict[ syn_post_translate_cmd=self.top_module.manifest_dict[
"syn_post_translate_cmd"], "syn_post_translate_cmd"],
syn_pre_map_cmd=top_module.manifest_dict[ syn_pre_map_cmd=self.top_module.manifest_dict[
"syn_pre_map_cmd"], "syn_pre_map_cmd"],
syn_post_map_cmd=top_module.manifest_dict[ syn_post_map_cmd=self.top_module.manifest_dict[
"syn_post_map_cmd"], "syn_post_map_cmd"],
syn_pre_par_cmd=top_module.manifest_dict[ syn_pre_par_cmd=self.top_module.manifest_dict[
"syn_pre_par_cmd"], "syn_pre_par_cmd"],
syn_post_par_cmd=top_module.manifest_dict[ syn_post_par_cmd=self.top_module.manifest_dict[
"syn_post_par_cmd"], "syn_post_par_cmd"],
syn_pre_bitstream_cmd=top_module.manifest_dict[ syn_pre_bitstream_cmd=self.top_module.manifest_dict[
"syn_pre_bitstream_cmd"], "syn_pre_bitstream_cmd"],
syn_post_bitstream_cmd=top_module.manifest_dict[ syn_post_bitstream_cmd=self.top_module.manifest_dict[
"syn_post_bitstream_cmd"])) "syn_post_bitstream_cmd"]))
def makefile_syn_clean(self): def makefile_syn_clean(self):
...@@ -217,8 +217,8 @@ syn_post_bitstream_cmd: ...@@ -217,8 +217,8 @@ syn_post_bitstream_cmd:
self.makefile_clean() self.makefile_clean()
self.writeln("\t\t" + path_mod.del_command() + self.writeln("\t\t" + path_mod.del_command() +
" synthesize translate map par bitstream") " synthesize translate map par bitstream")
self.writeln("\t\t" + path_mod.del_command() + self.writeln("\t\t" + path_mod.del_command() + " tcl_synthesize " +
" tcl_synthesize tcl_translate tcl_map tcl_par tcl_bitstream") "tcl_translate tcl_map tcl_par tcl_bitstream")
self.makefile_mrproper() self.makefile_mrproper()
def makefile_syn_phony(self): def makefile_syn_phony(self):
......
hdlmake/tools/makefile.py
View file @ f5a6d101
...@@ -41,6 +41,8 @@ class ToolMakefile(object): ...@@ -41,6 +41,8 @@ class ToolMakefile(object):
self._tcl_controls = {} self._tcl_controls = {}
self._hdl_files = [] self._hdl_files = []
self._supported_files = [] self._supported_files = []
self.top_module = None
self.fileset = None
if filename: if filename:
self._filename = filename self._filename = filename
else: else:
...@@ -50,9 +52,14 @@ class ToolMakefile(object): ...@@ -50,9 +52,14 @@ class ToolMakefile(object):
if self._file: if self._file:
self._file.close() self._file.close()
def makefile_includes(self, top_module): def makefile_setup(self, top_module, fileset):
"""Set the Makefile configuration"""
self.top_module = top_module
self.fileset = fileset
def makefile_includes(self):
"""Add the included makefiles that need to be previously loaded""" """Add the included makefiles that need to be previously loaded"""
for file_aux in top_module.incl_makefiles: for file_aux in self.top_module.incl_makefiles:
if os.path.exists(file_aux): if os.path.exists(file_aux):
self.write("include %s\n" % file_aux) self.write("include %s\n" % file_aux)
......
hdlmake/tools/modelsim.py
View file @ f5a6d101
...@@ -55,8 +55,9 @@ class ToolModelsim(VsimMakefileWriter): ...@@ -55,8 +55,9 @@ class ToolModelsim(VsimMakefileWriter):
self._tool_info.update(ToolModelsim.TOOL_INFO) self._tool_info.update(ToolModelsim.TOOL_INFO)
self._clean_targets.update(ToolModelsim.CLEAN_TARGETS) self._clean_targets.update(ToolModelsim.CLEAN_TARGETS)
def makefile_sim_options(self, top_module): def makefile_sim_options(self):
"""Print the Modelsim options to the Makefile""" """Print the Modelsim options to the Makefile"""
top_module = self.top_module
if top_module.pool.env["modelsim_path"]: if top_module.pool.env["modelsim_path"]:
modelsim_ini_path = os.path.join( modelsim_ini_path = os.path.join(
top_module.pool.env["modelsim_path"], top_module.pool.env["modelsim_path"],
...@@ -64,4 +65,4 @@ class ToolModelsim(VsimMakefileWriter): ...@@ -64,4 +65,4 @@ class ToolModelsim(VsimMakefileWriter):
else: else:
modelsim_ini_path = os.path.join("$(HDLMAKE_MODELSIM_PATH)", "..") modelsim_ini_path = os.path.join("$(HDLMAKE_MODELSIM_PATH)", "..")
self.custom_variables["MODELSIM_INI_PATH"] = modelsim_ini_path self.custom_variables["MODELSIM_INI_PATH"] = modelsim_ini_path
super(ToolModelsim, self).makefile_sim_options(top_module) super(ToolModelsim, self).makefile_sim_options()
hdlmake/tools/quartus.py
View file @ f5a6d101
...@@ -90,7 +90,7 @@ class ToolQuartus(ToolSyn): ...@@ -90,7 +90,7 @@ class ToolQuartus(ToolSyn):
self._clean_targets.update(ToolQuartus.CLEAN_TARGETS) self._clean_targets.update(ToolQuartus.CLEAN_TARGETS)
self._tcl_controls.update(ToolQuartus.TCL_CONTROLS) self._tcl_controls.update(ToolQuartus.TCL_CONTROLS)
def makefile_syn_tcl(self, top_module): def makefile_syn_tcl(self):
"""Add initial properties to the Altera Quartus project""" """Add initial properties to the Altera Quartus project"""
import re import re
...@@ -139,6 +139,7 @@ class ToolQuartus(ToolSyn): ...@@ -139,6 +139,7 @@ class ToolQuartus(ToolSyn):
sys.exit("\nExiting") sys.exit("\nExiting")
return family return family
top_module = self.top_module
# Set the core Quartus project properties # Set the core Quartus project properties
family_string = __get_family_string( family_string = __get_family_string(
family=top_module.manifest_dict["syn_family"], family=top_module.manifest_dict["syn_family"],
...@@ -149,13 +150,16 @@ class ToolQuartus(ToolSyn): ...@@ -149,13 +150,16 @@ class ToolQuartus(ToolSyn):
top_module.manifest_dict["syn_grade"]).upper() top_module.manifest_dict["syn_grade"]).upper()
command_list = [] command_list = []
command_list.append(self._tcl_controls["create"]) command_list.append(self._tcl_controls["create"])
command_list.append(_emit_property(self.SET_GLOBAL_ASSIGNMENT, command_list.append(_emit_property(
self.SET_GLOBAL_ASSIGNMENT,
name_type='FAMILY', name_type='FAMILY',
name='"' + family_string + '"')) name='"' + family_string + '"'))
command_list.append(_emit_property(self.SET_GLOBAL_ASSIGNMENT, command_list.append(_emit_property(
self.SET_GLOBAL_ASSIGNMENT,
name_type='DEVICE', name_type='DEVICE',
name=device_string)) name=device_string))
command_list.append(_emit_property(self.SET_GLOBAL_ASSIGNMENT, command_list.append(_emit_property(
self.SET_GLOBAL_ASSIGNMENT,
name_type='TOP_LEVEL_ENTITY', name_type='TOP_LEVEL_ENTITY',
name=top_module.manifest_dict["syn_top"])) name=top_module.manifest_dict["syn_top"]))
# Insert the Quartus standard control TCL files # Insert the Quartus standard control TCL files
...@@ -196,15 +200,15 @@ class ToolQuartus(ToolSyn): ...@@ -196,15 +200,15 @@ class ToolQuartus(ToolSyn):
name_type='POST_FLOW_SCRIPT_FILE', name_type='POST_FLOW_SCRIPT_FILE',
name=postflow)) name=postflow))
self._tcl_controls["create"] = '\n'.join(command_list) self._tcl_controls["create"] = '\n'.join(command_list)
super(ToolQuartus, self).makefile_syn_tcl(top_module) super(ToolQuartus, self).makefile_syn_tcl()
def makefile_syn_files(self, fileset): def makefile_syn_files(self):
"""Write the files TCL section of the Makefile""" """Write the files TCL section of the Makefile"""
self.writeln("define TCL_FILES") self.writeln("define TCL_FILES")
tmp = "set_global_assignment -name {0} {1}" tmp = "set_global_assignment -name {0} {1}"
tmplib = tmp + " -library {2}" tmplib = tmp + " -library {2}"
ret = [] ret = []
for file_aux in fileset: for file_aux in self.fileset:
if isinstance(file_aux, VHDLFile): if isinstance(file_aux, VHDLFile):
line = tmplib.format("VHDL_FILE", line = tmplib.format("VHDL_FILE",
file_aux.rel_path(), file_aux.library) file_aux.rel_path(), file_aux.library)
......
hdlmake/tools/sim_makefile_support.py
View file @ f5a6d101
...@@ -59,7 +59,7 @@ class VsimMakefileWriter(ToolSim): ...@@ -59,7 +59,7 @@ class VsimMakefileWriter(ToolSim):
self.copy_rules = {} self.copy_rules = {}
self._hdl_files.extend(VsimMakefileWriter.HDL_FILES) self._hdl_files.extend(VsimMakefileWriter.HDL_FILES)
def makefile_sim_options(self, top_module): def makefile_sim_options(self):
"""Print the vsim options to the Makefile""" """Print the vsim options to the Makefile"""
def __get_rid_of_vsim_incdirs(vlog_opt=""): def __get_rid_of_vsim_incdirs(vlog_opt=""):
"""Parse the VLOG options and purge the included dirs""" """Parse the VLOG options and purge the included dirs"""
...@@ -71,6 +71,7 @@ class VsimMakefileWriter(ToolSim): ...@@ -71,6 +71,7 @@ class VsimMakefileWriter(ToolSim):
if not vlog_aux.startswith("+incdir+"): if not vlog_aux.startswith("+incdir+"):
ret.append(vlog_aux) ret.append(vlog_aux)
return ' '.join(ret) return ' '.join(ret)
top_module = self.top_module
self.vlog_flags.append(__get_rid_of_vsim_incdirs( self.vlog_flags.append(__get_rid_of_vsim_incdirs(
top_module.manifest_dict["vlog_opt"])) top_module.manifest_dict["vlog_opt"]))
self.vcom_flags.append(top_module.manifest_dict["vcom_opt"]) self.vcom_flags.append(top_module.manifest_dict["vcom_opt"])
...@@ -84,7 +85,7 @@ class VsimMakefileWriter(ToolSim): ...@@ -84,7 +85,7 @@ class VsimMakefileWriter(ToolSim):
self.writeln("VLOG_FLAGS := %s" % (' '.join(self.vlog_flags))) self.writeln("VLOG_FLAGS := %s" % (' '.join(self.vlog_flags)))
self.writeln("VMAP_FLAGS := %s" % (' '.join(self.vmap_flags))) self.writeln("VMAP_FLAGS := %s" % (' '.join(self.vmap_flags)))
def makefile_sim_compilation(self, fileset, top_module): def makefile_sim_compilation(self):
"""Write a properly formatted Makefile for the simulator. """Write a properly formatted Makefile for the simulator.
The Makefile format is shared, but flags, dependencies, clean rules, The Makefile format is shared, but flags, dependencies, clean rules,
etc are defined by the specific tool. etc are defined by the specific tool.
...@@ -96,6 +97,7 @@ class VsimMakefileWriter(ToolSim): ...@@ -96,6 +97,7 @@ class VsimMakefileWriter(ToolSim):
\t\t%s $< . 2>&1 \t\t%s $< . 2>&1
""" % (name, src, path_mod.copy_command()) """ % (name, src, path_mod.copy_command())
return rule return rule
fileset = self.fileset
# self.writeln("INCLUDE_DIRS := +incdir+%s" % # self.writeln("INCLUDE_DIRS := +incdir+%s" %
# ('+'.join(top_module.include_dirs))) # ('+'.join(top_module.include_dirs)))
libs = set(f.library for f in fileset) libs = set(f.library for f in fileset)
...@@ -123,7 +125,8 @@ class VsimMakefileWriter(ToolSim): ...@@ -123,7 +125,8 @@ class VsimMakefileWriter(ToolSim):
self.write(lib + path_mod.slash_char() + "." + lib + ":\n") self.write(lib + path_mod.slash_char() + "." + lib + ":\n")
vmap_command = "vmap $(VMAP_FLAGS)" vmap_command = "vmap $(VMAP_FLAGS)"
self.write(' '.join(["\t(vlib", lib, "&&", vmap_command, lib, "&&", self.write(' '.join(["\t(vlib", lib, "&&", vmap_command, lib, "&&",
"touch", lib + path_mod.slash_char() + "." + lib, ")"])) "touch", lib + path_mod.slash_char() +
"." + lib, ")"]))
self.write(' '.join(["||", path_mod.del_command(), lib, "\n"])) self.write(' '.join(["||", path_mod.del_command(), lib, "\n"]))
self.write('\n\n') self.write('\n\n')
# rules for all _primary.dat files for sv # rules for all _primary.dat files for sv
......
hdlmake/tools/xilinx.py
View file @ f5a6d101
...@@ -59,13 +59,13 @@ class ToolXilinx(ToolSyn): ...@@ -59,13 +59,13 @@ class ToolXilinx(ToolSyn):
self._clean_targets.update(ToolXilinx.CLEAN_TARGETS) self._clean_targets.update(ToolXilinx.CLEAN_TARGETS)
self._tcl_controls.update(ToolXilinx.TCL_CONTROLS) self._tcl_controls.update(ToolXilinx.TCL_CONTROLS)
def makefile_syn_tcl(self, top_module): def makefile_syn_tcl(self):
"""Create a Xilinx synthesis project by TCL""" """Create a Xilinx synthesis project by TCL"""
tmp = "set_property {0} {1} [{2}]" tmp = "set_property {0} {1} [{2}]"
syn_device = top_module.manifest_dict["syn_device"] syn_device = self.top_module.manifest_dict["syn_device"]
syn_grade = top_module.manifest_dict["syn_grade"] syn_grade = self.top_module.manifest_dict["syn_grade"]
syn_package = top_module.manifest_dict["syn_package"] syn_package = self.top_module.manifest_dict["syn_package"]
syn_top = top_module.manifest_dict["syn_top"] syn_top = self.top_module.manifest_dict["syn_top"]
create_new = [] create_new = []
create_new.append(self._tcl_controls["create"]) create_new.append(self._tcl_controls["create"])
properties = [ properties = [
...@@ -75,14 +75,14 @@ class ToolXilinx(ToolSyn): ...@@ -75,14 +75,14 @@ class ToolXilinx(ToolSyn):
for prop in properties: for prop in properties:
create_new.append(tmp.format(prop[0], prop[1], prop[2])) create_new.append(tmp.format(prop[0], prop[1], prop[2]))
self._tcl_controls["create"] = "\n".join(create_new) self._tcl_controls["create"] = "\n".join(create_new)
super(ToolXilinx, self).makefile_syn_tcl(top_module) super(ToolXilinx, self).makefile_syn_tcl()
def makefile_syn_files(self, fileset): def makefile_syn_files(self):
"""Write the files TCL section of the Makefile""" """Write the files TCL section of the Makefile"""
self.writeln("define TCL_FILES") self.writeln("define TCL_FILES")
tmp = "add_files -norecurse {0}" tmp = "add_files -norecurse {0}"
tcl = "source {0}" tcl = "source {0}"
for file_aux in fileset: for file_aux in self.fileset:
if isinstance(file_aux, TCLFile): if isinstance(file_aux, TCLFile):
line = tcl.format(file_aux.rel_path()) line = tcl.format(file_aux.rel_path())
else: else:
......
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