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Hdlmake
Commit f3cb9d26 authored by Paweł Szostek's avatar Paweł Szostek
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actions: add more verbosity

parent f9a1af27
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Showing with 28 additions and 8 deletions
hdlmake/action/clean.py
View file @ f3cb9d26
......@@ -33,4 +33,5 @@ class CleanModules(Action):
print("\t" + m.url + " [from: " + m.path + "]")
m.remove_dir_from_disk()
else:
logging.info("There are no modules to be removed")
\ No newline at end of file
logging.info("There are no modules to be removed")
logging.info("Modules cleaned.")
\ No newline at end of file
hdlmake/action/fetch.py
View file @ f3cb9d26
......@@ -35,3 +35,4 @@ class FetchModules(Action):
logging.info("Fetching needed modules.")
self.modules_pool.fetch_all(unfetched_only=not self.options.update, flatten=self.options.flatten)
logging.debug(str(self.modules_pool))
logging.info("All modules fetched.")
\ No newline at end of file
hdlmake/action/fetch_makefile.py
View file @ f3cb9d26
......@@ -20,17 +20,19 @@
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
from action import Action
import global_mod
import logging
class GenerateFetchMakefile(Action):
def run(self):
pool = self.modules_pool
logging.info("Generating makefile for fetching modules.")
if pool.get_fetchable_modules() == []:
logging.error("There are no fetchable modules. "
"No fetch makefile is produced")
quit()
self._check_all_fetched_or_quit()
self.make_writer.generate_fetch_makefile(pool)
global_mod.makefile_writer.generate_fetch_makefile(pool)
logging.info("Makefile for fetching modules generated.")
\ No newline at end of file
hdlmake/action/ise_makefile.py
View file @ f3cb9d26
......@@ -36,3 +36,4 @@ class GenerateISEMakefile(Action):
global_mod.makefile_writer.generate_ise_makefile(top_mod=self.modules_pool.get_top_module(),
ise_path=ise_path)
logging.info("Local synthesis makefile generated.")
\ No newline at end of file
hdlmake/action/ise_project.py
View file @ f3cb9d26
......@@ -24,9 +24,7 @@ import logging
from action import Action
import sys
import os
from dep_file import DepFile
import new_dep_solver as dep_solver
from srcfile import SourceFileSet
from tools.ise import ISEProject
from srcfile import SourceFileFactory
import global_mod
......@@ -61,11 +59,13 @@ class GenerateISEProject(Action):
self._handle_ise_project(update=True)
else:
self._handle_ise_project(update=False)
logging.info("ISE project file generated.")
def _handle_ise_project(self, update=False):
top_mod = self.modules_pool.get_top_module()
fileset = self.modules_pool.build_file_set()
flist = dep_solver.make_dependency_sorted_list(fileset)
assert isinstance(flist, list)
prj = ISEProject(ise=self.env["ise_version"],
top_mod=self.modules_pool.get_top_module())
......
hdlmake/action/merge_cores.py
View file @ f3cb9d26
......@@ -43,6 +43,7 @@ class MergeCores(Action):
pool = self.modules_pool
self._check_all_fetched_or_quit()
logging.info("Merging all cores into one source file per language.")
flist = pool.build_global_file_set()
# if not os.path.exists(self.options.merge_cores):
# os.makedirs(self.options.merge_cores)
......@@ -100,3 +101,5 @@ class MergeCores(Action):
import shutil
logging.info("copying NGC file: %s" % ngc.rel_path())
shutil.copy(ngc.rel_path(), os.getcwd())
logging.info("Cores merged.")
\ No newline at end of file
hdlmake/action/quartus_project.py
View file @ f3cb9d26
......@@ -24,7 +24,6 @@ import logging
import os
from dependable_file import DependableFile
from action import Action
import dep_solver
from tools.quartus import QuartusProject
......@@ -42,6 +41,7 @@ class GenerateQuartusProject(Action):
self._update_existing_quartus_project()
else:
self._create_new_quartus_project()
logging.info("Quartus project file generated.")
def _create_new_quartus_project(self):
top_mod = self.modules_pool.get_top_module()
......
hdlmake/action/remote_synthesis.py
View file @ f3cb9d26
......@@ -48,6 +48,7 @@ class GenerateRemoteSynthesisMakefile(Action):
global_mod.makefile_writer.generate_remote_synthesis_makefile(files=files, name=top_mod.syn_name,
cwd=os.getcwd(), user=self.env["rsynth_user"],
server=self.env["rsynth_server"])
logging.info("Remote synthesis makefile generated.")
def _check_manifest(self):
if not self.top_module.action == "synthesis":
......
hdlmake/action/simulation.py
View file @ f3cb9d26
......@@ -21,6 +21,8 @@
from __future__ import print_function
from action import Action
from dep_file import DepFile
import new_dep_solver as dep_solver
import logging
import sys
import global_mod
......@@ -38,27 +40,32 @@ class GenerateSimulationMakefile(Action):
tm = self.modules_pool.top_module
if tm.sim_tool == "iverilog":
logging.info("Generating simulation makefile for iverilog")
self._generate_iverilog_makefile()
elif tm.sim_tool == "isim":
self._generate_isim_makefile()
logging.info("Generating simulation makefile for isim")
elif tm.sim_tool == "vsim" or tm.sim_tool == "modelsim":
self._generate_vsim_makefile()
logging.info("Generating simulation makefile for vsim")
else:
logging.error("Unrecognized or not specified simulation tool: %s" % str(tm.sim_tool))
sys.exit("Exiting")
logging.info("Simulation makefile generated.")
def _generate_vsim_makefile(self):
if self.env["modelsim_path"] is None:
logging.error("Can't generate a Modelsim makefile. Modelsim not found.")
sys.exit("Exiting")
from dep_file import DepFile
logging.info("Generating ModelSim makefile for simulation.")
pool = self.modules_pool
top_module = pool.get_top_module()
fset = pool.build_file_set()
dep_files = fset.filter(DepFile)
dep_solver.solve(dep_files)
global_mod.makefile_writer.generate_vsim_makefile(dep_files, top_module)
def _generate_isim_makefile(self):
......@@ -72,7 +79,9 @@ class GenerateSimulationMakefile(Action):
top_module = pool.get_top_module()
fset = pool.build_file_set()
global_mod.makefile_writer.generate_isim_makefile(fset, top_module)
dep_files = fset.filter(DepFile)
dep_solver.solve(dep_files)
global_mod.makefile_writer.generate_isim_makefile(dep_files, top_module)
def _generate_iverilog_makefile(self):
logging.info("Generating IVerilog makefile for simulation.")
......@@ -84,4 +93,6 @@ class GenerateSimulationMakefile(Action):
tm = pool.get_top_module()
fset = pool.build_file_set()
dep_solver.solve(fset)
global_mod.makefile_writer.generate_iverilog_makefile(fset, tm, pool)
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