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Hdlmake
Commits
ebe3f5f6
Commit
ebe3f5f6
authored
Mar 17, 2016
by
Projects
Committed by
Javier D. Garcia-Lasheras
Mar 17, 2016
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Output include_dirs variable for Icarus simulation (NOTE: patch rebased by project manager)
parent
2ece8425
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1 changed file
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3 additions
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2 deletions
+3
-2
iverilog.py
hdlmake/tools/iverilog/iverilog.py
+3
-2
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hdlmake/tools/iverilog/iverilog.py
View file @
ebe3f5f6
...
@@ -64,8 +64,6 @@ class ToolControls(MakefileWriter):
...
@@ -64,8 +64,6 @@ class ToolControls(MakefileWriter):
def
generate_simulation_makefile
(
self
,
fileset
,
top_module
):
def
generate_simulation_makefile
(
self
,
fileset
,
top_module
):
# TODO FLAGS: 2009 enables SystemVerilog (ongoing support) and partial VHDL support
# TODO FLAGS: 2009 enables SystemVerilog (ongoing support) and partial VHDL support
# TODO: include dir
from
hdlmake.srcfile
import
VerilogFile
,
VHDLFile
,
SVFile
from
hdlmake.srcfile
import
VerilogFile
,
VHDLFile
,
SVFile
makefile_tmplt_1
=
string
.
Template
(
"""TOP_MODULE := ${top_module}
makefile_tmplt_1
=
string
.
Template
(
"""TOP_MODULE := ${top_module}
...
@@ -86,6 +84,9 @@ simulation:
...
@@ -86,6 +84,9 @@ simulation:
self
.
writeln
(
"
\t\t
echo
\"
# IVerilog command file, generated by HDLMake
\"
> run.command"
)
self
.
writeln
(
"
\t\t
echo
\"
# IVerilog command file, generated by HDLMake
\"
> run.command"
)
for
inc
in
top_module
.
include_dirs
:
self
.
writeln
(
"
\t\t
echo
\"
+incdir+"
+
inc
+
"
\"
>> run.command"
)
for
vl
in
fileset
.
filter
(
VerilogFile
):
for
vl
in
fileset
.
filter
(
VerilogFile
):
self
.
writeln
(
"
\t\t
echo
\"
"
+
vl
.
rel_path
()
+
"
\"
>> run.command"
)
self
.
writeln
(
"
\t\t
echo
\"
"
+
vl
.
rel_path
()
+
"
\"
>> run.command"
)
...
...
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