Add a test for previous commit

e34c7c02 · Tristan Gingold · 8685b0e2 · e34c7c02 · e34c7c02 · e34c7c02
Commit e34c7c02 authored Nov 18, 2021 by Tristan Gingold
Showing with 95 additions and 0 deletions

Makefile.ref testsuite/116vhdl_parser/Makefile.ref +61 -0

Manifest.py testsuite/116vhdl_parser/Manifest.py +8 -0

gate3.vhd testsuite/116vhdl_parser/gate3.vhd +23 -0

test_all.py testsuite/test_all.py +3 -0

No files found.
--- a/testsuite/116vhdl_parser/Makefile.ref
+++ b/testsuite/116vhdl_parser/Makefile.ref
+########################################
+#  This file was generated by hdlmake  #
+#  http://ohwr.org/projects/hdl-make/  #
+########################################
+
+TOP_MODULE := gate3
+
+MODELSIM_INI_PATH := my_ini
+
+VCOM_FLAGS := -quiet -modelsimini modelsim.ini 
+VSIM_FLAGS := 
+VLOG_FLAGS := -quiet -modelsimini modelsim.ini 
+VMAP_FLAGS := -modelsimini modelsim.ini 
+#target for performing local simulation
+local: sim_pre_cmd simulation sim_post_cmd
+
+VERILOG_SRC := 
+VERILOG_OBJ := 
+VHDL_SRC := gate3.vhd \
+../files/gate.vhdl \
+
+VHDL_OBJ := work/hdlmake/gate3_vhd \
+work/hdlmake/gate_vhdl \
+
+INCLUDE_DIRS :=
+LIBS := work
+LIB_IND := work/hdlmake/work-stamp
+
+simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
+$(VERILOG_OBJ): modelsim.ini
+$(VHDL_OBJ): $(LIB_IND) modelsim.ini
+
+modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
+		cp $< . 2>&1
+
+work/hdlmake/work-stamp:
+	(vlib work && vmap $(VMAP_FLAGS) work && mkdir -p work/hdlmake && touch work/hdlmake/work-stamp) || rm -rf work
+
+work/hdlmake/gate3_vhd: gate3.vhd \
+work/hdlmake/gate_vhdl
+		vcom $(VCOM_FLAGS) -work work $< 
+		@touch $@
+
+work/hdlmake/gate_vhdl: ../files/gate.vhdl
+		vcom $(VCOM_FLAGS) -work work $< 
+		@touch $@
+
+# USER SIM COMMANDS
+sim_pre_cmd:
+		
+sim_post_cmd:
+		
+
+CLEAN_TARGETS := $(LIBS) modelsim.ini transcript
+
+clean:
+		rm -rf $(CLEAN_TARGETS)
+mrproper: clean
+		rm -rf *.vcd *.wlf
+
+.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
--- a/testsuite/116vhdl_parser/Manifest.py
+++ b/testsuite/116vhdl_parser/Manifest.py
+action = "simulation"
+
+sim_tool="modelsim"
+modelsim_ini_path="my_ini"
+
+top_module = "gate3"
+
+files = [ "gate3.vhd", "../files/gate.vhdl" ]
--- a/testsuite/116vhdl_parser/gate3.vhd
+++ b/testsuite/116vhdl_parser/gate3.vhd
+entity gate3 is
+  port (i : in bit;
+        o : out bit);
+end gate3;
+
+architecture behav of gate3 is
+  function f return natural is
+  begin
+    return 4;
+  end;
+begin
+  inst: entity work.gate 
+    port map (i, o);
+
+  process
+    function g return natural is
+    begin
+      return 5;
+    end function;
+  begin
+    wait;
+  end process;
+end behav;
--- a/testsuite/test_all.py
+++ b/testsuite/test_all.py
@@ -553,6 +553,9 @@ def test_vhdl_libraries_liberosoc_114():
 def test_vhdl_libraries_GHDLSyn_115():
    run_compare_filter(filter="TOOL_PATH", path="115_ghdlsyn_libraries")

+def test_vhdl_parser_116():
+    run_compare(path="116vhdl_parser")
+
 @pytest.mark.xfail
 def test_xfail():
    """This is a self-consistency test: the test is known to fail"""