Commit c894f8f1 authored by Tristan Gingold's avatar Tristan Gingold remove useless import.

parent b5924e1c
......@@ -103,14 +103,11 @@ class VerilogPreprocessor(object):
def _handle_macros(text):
'''Process text to implement ifdef/ifndef/elsif/else/endif & define logic'''
from pprint import pprint
vpp_match = namedtuple('vpp_match', ['mtext','pptype','ppident', 'macroident','ppargs','ppdefn','incfile','substid'])
vpp_macrodefn = namedtuple('vpp_macrodefn', ['params', 'expansion'])
def _munge_list(flist):
'''Take the split list & normalize into a list of string literals & seperator matches'''
from pprint import pprint
if not flist:
return []
is_match = False # if nothing was present, split inserts an empty element
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