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Commit bea57492 authored by Tristan Gingold's avatar Tristan Gingold
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isim, makefilevsim: factorize code.

parent 657b69e8
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Showing with 21 additions and 15 deletions
hdlmake/tools/isim.py
View file @ bea57492
......@@ -135,13 +135,8 @@ class ToolISim(MakefileSim):
def _makefile_sim_compilation(self):
"""Print the compile simulation target for Xilinx ISim"""
libs = set(f.library for f in self.fileset)
self.writeln('LIBS := ' + ' '.join(libs))
# tell how to make libraries
self.write('LIB_IND := ')
self.write(' '.join([lib + shell.makefile_slash_char() +
"." + lib for lib in libs]))
self.write('\n')
libs = self.get_all_libs()
self._makefile_sim_libs_variables(libs)
self.writeln("""\
simulation: xilinxsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) fuse
$(VERILOG_OBJ): $(LIB_IND) xilinxsim.ini
......
hdlmake/tools/makefilesim.py
View file @ bea57492
......@@ -127,6 +127,19 @@ class MakefileSim(ToolMakefile):
self._makefile_touch_stamp_file()
self.writeln()
def get_all_libs(self):
"""Return a sorted list of all the libraries name"""
return sorted(set(f.library for f in self.fileset))
def _makefile_sim_libs_variables(self, libs):
"""Create variables for libraries name"""
self.writeln('LIBS := ' + ' '.join(libs))
self.write('LIB_IND := ')
self.write(' '.join([lib + shell.makefile_slash_char() +
"." + lib for lib in libs]))
self.write('\n')
self.writeln()
def _makefile_sim_command(self):
"""Generic method to write the simulation Makefile user commands"""
self.writeln("# USER SIM COMMANDS")
......
hdlmake/tools/makefilevsim.py
View file @ bea57492
......@@ -100,14 +100,8 @@ class MakefileVsim(MakefileSim):
else:
self.writeln("INCLUDE_DIRS := +incdir+%s" %
('+'.join(self.manifest_dict.get("include_dirs"))))
libs = sorted(set(f.library for f in self.fileset))
self.writeln('LIBS := ' + ' '.join(libs))
# tell how to make libraries
self.write('LIB_IND := ')
self.write(' '.join([lib + shell.makefile_slash_char() +
"." + lib for lib in libs]))
self.write('\n')
self.writeln()
libs = self.get_all_libs()
self._makefile_sim_libs_variables(libs)
self.writeln(
"simulation: %s $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)" %
(' '.join(self.additional_deps)),)
......
testsuite/010isim/Makefile.ref
View file @ bea57492
......@@ -25,6 +25,7 @@ work/gate3/.gate3_vhd \
LIBS := work
LIB_IND := work/.work
simulation: xilinxsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) fuse
$(VERILOG_OBJ): $(LIB_IND) xilinxsim.ini
$(VHDL_OBJ): $(LIB_IND) xilinxsim.ini
......
testsuite/060isim_windows/Makefile.ref
View file @ bea57492
......@@ -25,6 +25,7 @@ work/gate3/.gate3_vhd \
LIBS := work
LIB_IND := work\.work
simulation: xilinxsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) fuse
$(VERILOG_OBJ): $(LIB_IND) xilinxsim.ini
$(VHDL_OBJ): $(LIB_IND) xilinxsim.ini
......
testsuite/061err_nobin/Makefile.ref
View file @ bea57492
......@@ -25,6 +25,7 @@ work/gate3/.gate3_vhd \
LIBS := work
LIB_IND := work/.work
simulation: xilinxsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) fuse
$(VERILOG_OBJ): $(LIB_IND) xilinxsim.ini
$(VHDL_OBJ): $(LIB_IND) xilinxsim.ini
......
testsuite/097sys_package/Makefile.ref
View file @ bea57492
......@@ -21,6 +21,7 @@ VHDL_OBJ := work/gate/.gate_vhdl \
LIBS := work
LIB_IND := work/.work
simulation: xilinxsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) fuse
$(VERILOG_OBJ): $(LIB_IND) xilinxsim.ini
$(VHDL_OBJ): $(LIB_IND) xilinxsim.ini
......
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