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Commit bc478ac4 authored by Tristan Gingold's avatar Tristan Gingold
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tools: renaming to improve consistency.

parent f928f8a3
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Showing with 34 additions and 34 deletions
hdlmake/tools/active_hdl.py
View file @ bc478ac4
...@@ -24,11 +24,11 @@ ...@@ -24,11 +24,11 @@
"""Module providing support for Aldec Active-HDL simulator""" """Module providing support for Aldec Active-HDL simulator"""
from __future__ import absolute_import from __future__ import absolute_import
from .make_sim import MakeSim from .makefilesim import MakefileSim
from hdlmake.srcfile import VHDLFile, VerilogFile, SVFile from hdlmake.srcfile import VHDLFile, VerilogFile, SVFile
class ToolActiveHDL(MakeSim): class ToolActiveHDL(MakefileSim):
"""Class providing the interface to control an Active-HDL simulation""" """Class providing the interface to control an Active-HDL simulation"""
......
hdlmake/tools/diamond.py
View file @ bc478ac4
...@@ -25,11 +25,11 @@ ...@@ -25,11 +25,11 @@
from __future__ import absolute_import from __future__ import absolute_import
from .make_syn import MakeSyn from .makefilesyn import MakefileSyn
from hdlmake.srcfile import EDFFile, LPFFile, VHDLFile, VerilogFile from hdlmake.srcfile import EDFFile, LPFFile, VHDLFile, VerilogFile
class ToolDiamond(MakeSyn): class ToolDiamond(MakefileSyn):
"""Class providing the interface for Lattice Diamond synthesis""" """Class providing the interface for Lattice Diamond synthesis"""
......
hdlmake/tools/ghdl.py
View file @ bc478ac4
...@@ -26,11 +26,11 @@ ...@@ -26,11 +26,11 @@
from __future__ import absolute_import from __future__ import absolute_import
import string import string
from .make_sim import MakeSim from .makefilesim import MakefileSim
from hdlmake.srcfile import VHDLFile from hdlmake.srcfile import VHDLFile
class ToolGHDL(MakeSim): class ToolGHDL(MakefileSim):
"""Class providing the interface for GHDL simulator""" """Class providing the interface for GHDL simulator"""
......
hdlmake/tools/icestorm.py
View file @ bc478ac4
...@@ -25,11 +25,11 @@ ...@@ -25,11 +25,11 @@
from __future__ import absolute_import from __future__ import absolute_import
from .make_syn import MakeSyn from .makefilesyn import MakefileSyn
from hdlmake.srcfile import VerilogFile, PCFFile from hdlmake.srcfile import VerilogFile, PCFFile
class ToolIcestorm(MakeSyn): class ToolIcestorm(MakefileSyn):
"""Class providing the interface for IceStorm synthesis""" """Class providing the interface for IceStorm synthesis"""
......
hdlmake/tools/ise.py
View file @ bc478ac4
...@@ -27,7 +27,7 @@ from __future__ import print_function ...@@ -27,7 +27,7 @@ from __future__ import print_function
from __future__ import absolute_import from __future__ import absolute_import
import logging import logging
from .make_syn import MakeSyn from .makefilesyn import MakefileSyn
from hdlmake.util import shell from hdlmake.util import shell
from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile, from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile,
...@@ -48,7 +48,7 @@ ISE_STANDARD_LIBS = ['ieee', 'ieee_proposed', 'iSE', 'simprims', 'std', ...@@ -48,7 +48,7 @@ ISE_STANDARD_LIBS = ['ieee', 'ieee_proposed', 'iSE', 'simprims', 'std',
'synopsys', 'unimacro', 'unisim', 'XilinxCoreLib'] 'synopsys', 'unimacro', 'unisim', 'XilinxCoreLib']
class ToolISE(MakeSyn): class ToolISE(MakefileSyn):
"""Class providing the methods to create and build a Xilinx ISE project""" """Class providing the methods to create and build a Xilinx ISE project"""
......
hdlmake/tools/isim.py
View file @ bc478ac4
...@@ -30,12 +30,12 @@ import os ...@@ -30,12 +30,12 @@ import os
import os.path import os.path
import logging import logging
from .make_sim import MakeSim from .makefilesim import MakefileSim
from hdlmake.util import shell from hdlmake.util import shell
from hdlmake.srcfile import VerilogFile, VHDLFile from hdlmake.srcfile import VerilogFile, VHDLFile
class ToolISim(MakeSim): class ToolISim(MakefileSim):
"""Class providing the interface for Xilinx ISim simulator""" """Class providing the interface for Xilinx ISim simulator"""
......
hdlmake/tools/iverilog.py
View file @ bc478ac4
...@@ -26,11 +26,11 @@ ...@@ -26,11 +26,11 @@
from __future__ import absolute_import from __future__ import absolute_import
import string import string
from .make_sim import MakeSim from .makefilesim import MakefileSim
from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile
class ToolIVerilog(MakeSim): class ToolIVerilog(MakefileSim):
"""Class providing the interface for Icarus Verilog simulator""" """Class providing the interface for Icarus Verilog simulator"""
......
hdlmake/tools/libero.py
View file @ bc478ac4
...@@ -25,11 +25,11 @@ ...@@ -25,11 +25,11 @@
from __future__ import absolute_import from __future__ import absolute_import
from .make_syn import MakeSyn from .makefilesyn import MakefileSyn
from hdlmake.srcfile import VHDLFile, VerilogFile, SDCFile, PDCFile from hdlmake.srcfile import VHDLFile, VerilogFile, SDCFile, PDCFile
class ToolLibero(MakeSyn): class ToolLibero(MakefileSyn):
"""Class providing the interface for Microsemi Libero IDE synthesis""" """Class providing the interface for Microsemi Libero IDE synthesis"""
......
hdlmake/tools/make_sim.py → hdlmake/tools/makefilesim.py
View file @ bc478ac4
...@@ -16,12 +16,12 @@ def _check_simulation_manifest(manifest_dict): ...@@ -16,12 +16,12 @@ def _check_simulation_manifest(manifest_dict):
raise Exception("sim_top variable must be set in the top manifest.") raise Exception("sim_top variable must be set in the top manifest.")
class MakeSim(ToolMakefile): class MakefileSim(ToolMakefile):
"""Class that provides the Makefile writing methods and status""" """Class that provides the Makefile writing methods and status"""
def __init__(self): def __init__(self):
super(MakeSim, self).__init__() super(MakefileSim, self).__init__()
self._simulator_controls = {} self._simulator_controls = {}
def write_makefile(self, config, fileset, filename=None): def write_makefile(self, config, fileset, filename=None):
......
hdlmake/tools/make_syn.py → hdlmake/tools/makefilesyn.py
View file @ bc478ac4
...@@ -21,12 +21,12 @@ def _check_synthesis_manifest(manifest_dict): ...@@ -21,12 +21,12 @@ def _check_synthesis_manifest(manifest_dict):
"syn_top variable must be set in the top manifest.") "syn_top variable must be set in the top manifest.")
class MakeSyn(ToolMakefile): class MakefileSyn(ToolMakefile):
"""Class that provides the synthesis Makefile writing methods and status""" """Class that provides the synthesis Makefile writing methods and status"""
def __init__(self): def __init__(self):
super(MakeSyn, self).__init__() super(MakefileSyn, self).__init__()
def write_makefile(self, config, fileset, filename=None): def write_makefile(self, config, fileset, filename=None):
"""Generate a Makefile for the specific synthesis tool""" """Generate a Makefile for the specific synthesis tool"""
......
hdlmake/tools/sim_makefile_support.py → hdlmake/tools/makefilevsim.py
View file @ bc478ac4
...@@ -27,13 +27,13 @@ from __future__ import absolute_import ...@@ -27,13 +27,13 @@ from __future__ import absolute_import
import os import os
import string import string
from .make_sim import MakeSim from .makefilesim import MakefileSim
from hdlmake.util import shell from hdlmake.util import shell
from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile
import six import six
class VsimMakefileWriter(MakeSim): class MakefileVsim(MakefileSim):
"""A Makefile writer for simulation suitable for vsim based simulators. """A Makefile writer for simulation suitable for vsim based simulators.
...@@ -45,7 +45,7 @@ class VsimMakefileWriter(MakeSim): ...@@ -45,7 +45,7 @@ class VsimMakefileWriter(MakeSim):
HDL_FILES = {VerilogFile: '', VHDLFile: '', SVFile: ''} HDL_FILES = {VerilogFile: '', VHDLFile: '', SVFile: ''}
def __init__(self): def __init__(self):
super(VsimMakefileWriter, self).__init__() super(MakefileVsim, self).__init__()
# These are variables that will be set in the makefile # These are variables that will be set in the makefile
# The key is the variable name, and the value is the variable value # The key is the variable name, and the value is the variable value
self.custom_variables = {} self.custom_variables = {}
...@@ -54,7 +54,7 @@ class VsimMakefileWriter(MakeSim): ...@@ -54,7 +54,7 @@ class VsimMakefileWriter(MakeSim):
# These are files copied into your working directory by a make rule # These are files copied into your working directory by a make rule
# The key is the filename, the value is the file source path # The key is the filename, the value is the file source path
self.copy_rules = {} self.copy_rules = {}
self._hdl_files.update(VsimMakefileWriter.HDL_FILES) self._hdl_files.update(MakefileVsim.HDL_FILES)
def _makefile_sim_options(self): def _makefile_sim_options(self):
"""Print the vsim options to the Makefile""" """Print the vsim options to the Makefile"""
......
hdlmake/tools/modelsim.py
View file @ bc478ac4
...@@ -27,10 +27,10 @@ from __future__ import print_function ...@@ -27,10 +27,10 @@ from __future__ import print_function
from __future__ import absolute_import from __future__ import absolute_import
import os import os
from .sim_makefile_support import VsimMakefileWriter from .makefilevsim import MakefileVsim
class ToolModelsim(VsimMakefileWriter): class ToolModelsim(MakefileVsim):
"""Class providing the interface for Mentor Modelsim simulator""" """Class providing the interface for Mentor Modelsim simulator"""
......
hdlmake/tools/quartus.py
View file @ bc478ac4
...@@ -28,7 +28,7 @@ import os ...@@ -28,7 +28,7 @@ import os
import sys import sys
import logging import logging
from .make_syn import MakeSyn from .makefilesyn import MakefileSyn
from hdlmake.util import path as path_mod from hdlmake.util import path as path_mod
from hdlmake.util import shell from hdlmake.util import shell
from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile, DPFFile, from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile, DPFFile,
...@@ -36,7 +36,7 @@ from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile, DPFFile, ...@@ -36,7 +36,7 @@ from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile, DPFFile,
QSFFile, BSFFile, BDFFile, TDFFile, GDFFile) QSFFile, BSFFile, BDFFile, TDFFile, GDFFile)
class ToolQuartus(MakeSyn): class ToolQuartus(MakefileSyn):
"""Class providing the interface for Altera Quartus synthesis""" """Class providing the interface for Altera Quartus synthesis"""
......
hdlmake/tools/riviera.py
View file @ bc478ac4
...@@ -25,7 +25,7 @@ ...@@ -25,7 +25,7 @@
"""Module providing support for Aldec Riviera-PRO simulation""" """Module providing support for Aldec Riviera-PRO simulation"""
from __future__ import print_function from __future__ import print_function
from .sim_makefile_support import VsimMakefileWriter from .makefilevsim import MakefileVsim
# as of 2014.06, these are the standard libraries # as of 2014.06, these are the standard libraries
# included in an installation # included in an installation
...@@ -62,7 +62,7 @@ RIVIERA_STANDARD_LIBS.extend(RIVIERA_XILINX_VHDL_LIBRARIES) ...@@ -62,7 +62,7 @@ RIVIERA_STANDARD_LIBS.extend(RIVIERA_XILINX_VHDL_LIBRARIES)
RIVIERA_STANDARD_LIBS.extend(RIVIERA_XILINX_VLOG_LIBRARIES) RIVIERA_STANDARD_LIBS.extend(RIVIERA_XILINX_VLOG_LIBRARIES)
class ToolRiviera(VsimMakefileWriter): class ToolRiviera(MakefileVsim):
"""Class providing the interface for Aldec Riviera-PRO simulator""" """Class providing the interface for Aldec Riviera-PRO simulator"""
......
hdlmake/tools/vivado_sim.py
View file @ bc478ac4
...@@ -25,10 +25,10 @@ ...@@ -25,10 +25,10 @@
from __future__ import absolute_import from __future__ import absolute_import
from .make_sim import MakeSim from .makefilesim import MakefileSim
from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile
class ToolVivadoSim(MakeSim): class ToolVivadoSim(MakefileSim):
"""Class providing the interface for Xilinx Vivado synthesis""" """Class providing the interface for Xilinx Vivado synthesis"""
......
hdlmake/tools/xilinx.py
View file @ bc478ac4
...@@ -25,12 +25,12 @@ ...@@ -25,12 +25,12 @@
from __future__ import absolute_import from __future__ import absolute_import
from .make_syn import MakeSyn from .makefilesyn import MakefileSyn
from hdlmake.srcfile import VHDLFile, VerilogFile, SVFile, TCLFile from hdlmake.srcfile import VHDLFile, VerilogFile, SVFile, TCLFile
import logging import logging
class ToolXilinx(MakeSyn): class ToolXilinx(MakefileSyn):
"""Class providing the interface for Xilinx Vivado synthesis""" """Class providing the interface for Xilinx Vivado synthesis"""
......
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