Commit ba564b0f authored by Pawel Szostek's avatar Pawel Szostek

move path.py to util/path.py

parent 7e4c34bd
...@@ -9,7 +9,7 @@ from srcfile import SourceFileSet ...@@ -9,7 +9,7 @@ from srcfile import SourceFileSet
from tools.ise import ISEProject from tools.ise import ISEProject
from srcfile import SourceFileFactory from srcfile import SourceFileFactory
import global_mod import global_mod
import path from util import path
class GenerateISEProject(Action): class GenerateISEProject(Action):
def _check_manifest(self): def _check_manifest(self):
......
from action import Action from action import Action
import path from util import path
class ListModules(Action): class ListModules(Action):
......
...@@ -27,7 +27,7 @@ from subprocess import Popen, PIPE ...@@ -27,7 +27,7 @@ from subprocess import Popen, PIPE
import re import re
import logging import logging
import os.path import os.path
import path from util import path
_plain_print = print _plain_print = print
......
#!/usr/bin/env python #!/usr/bin/env python
import os import os
import path from util import path
import logging import logging
from subprocess import Popen, PIPE from subprocess import Popen, PIPE
......
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
import os import os
import logging import logging
import path from util import path
from subprocess import Popen, PIPE from subprocess import Popen, PIPE
......
...@@ -19,7 +19,7 @@ ...@@ -19,7 +19,7 @@
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>. # along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
# #
import path as path_mod from util import path as path_mod
import os import os
from configparser import ConfigParser from configparser import ConfigParser
......
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
from __future__ import print_function from __future__ import print_function
from manifest_parser import Manifest, ManifestParser from manifest_parser import Manifest, ManifestParser
from srcfile import VerilogFile, VHDLFile, SourceFileFactory, SourceFileSet from srcfile import VerilogFile, VHDLFile, SourceFileFactory, SourceFileSet
import path as path_mod from util import path as path_mod
import os import os
import global_mod import global_mod
import logging import logging
...@@ -31,7 +31,7 @@ class Module(object): ...@@ -31,7 +31,7 @@ class Module(object):
@property @property
def basename(self): def basename(self):
import path from util import path
if self.source == "svn": if self.source == "svn":
return path.svn_basename(self.url) return path.svn_basename(self.url)
else: else:
...@@ -39,7 +39,7 @@ class Module(object): ...@@ -39,7 +39,7 @@ class Module(object):
#PLEASE don't use this constructor. Create all modules with ModulePool.new_module() #PLEASE don't use this constructor. Create all modules with ModulePool.new_module()
def __init__(self, parent, url, source, fetchto, pool): def __init__(self, parent, url, source, fetchto, pool):
import path from util import path
assert url is not None assert url is not None
assert source is not None assert source is not None
......
...@@ -27,8 +27,8 @@ import logging ...@@ -27,8 +27,8 @@ import logging
from tools import ise from tools import ise
from tools import modelsim from tools import modelsim
from tools import quartus from tools import quartus
import path as path_mod from util import path as path_mod
from subprocess import Popen, PIPE
class File(object): class File(object):
def __init__(self, path, module=None): def __init__(self, path, module=None):
...@@ -52,10 +52,9 @@ class File(object): ...@@ -52,10 +52,9 @@ class File(object):
return os.path.dirname(self.path) return os.path.dirname(self.path)
def rel_path(self, dir=None): def rel_path(self, dir=None):
import path
if dir is None: if dir is None:
dir = os.getcwd() dir = os.getcwd()
return path.relpath(self.path, dir) return path_mod.relpath(self.path, dir)
def __str__(self): def __str__(self):
return self.path return self.path
......
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