Start refactoring simulators for a future common base

parent 1582a4e4
...@@ -23,11 +23,9 @@ ...@@ -23,11 +23,9 @@
"""Module providing support for GHDL simulator""" """Module providing support for GHDL simulator"""
import os
import string import string
from .make_sim import ToolSim from .make_sim import ToolSim
from hdlmake.util import path as path_mod
from hdlmake.srcfile import VHDLFile from hdlmake.srcfile import VHDLFile
...@@ -45,7 +43,7 @@ class ToolGHDL(ToolSim): ...@@ -45,7 +43,7 @@ class ToolGHDL(ToolSim):
HDL_FILES = [VHDLFile] HDL_FILES = [VHDLFile]
CLEAN_TARGETS = {'clean': ["*.cf", "*.o", "$(TOP_MODULE)"], CLEAN_TARGETS = {'clean': ["*.cf", "*.o", "$(TOP_MODULE)", "work"],
'mrproper': ["*.vcd"]} 'mrproper': ["*.vcd"]}
def __init__(self): def __init__(self):
...@@ -67,32 +65,8 @@ class ToolGHDL(ToolSim): ...@@ -67,32 +65,8 @@ class ToolGHDL(ToolSim):
def makefile_sim_compilation(self): def makefile_sim_compilation(self):
"""Print the GDHL simulation compilation target""" """Print the GDHL simulation compilation target"""
fileset = self.fileset
self.writeln("simulation: $(VERILOG_OBJ) $(VHDL_OBJ)") self.writeln("simulation: $(VERILOG_OBJ) $(VHDL_OBJ)")
self.writeln("\t\tghdl -e $(TOP_MODULE)") self.writeln("\t\tghdl -e $(TOP_MODULE)")
self.writeln('\n') self.writeln('\n')
for file_aux in fileset: self.makefile_sim_dep_files("ghdl -a $<")
if any(isinstance(file_aux, file_type)
for file_type in self._hdl_files):
self.write("%s: %s" % (os.path.join(
file_aux.library, file_aux.purename,
".%s_%s" % (file_aux.purename, file_aux.extension())),
file_aux.rel_path()))
# list dependencies, do not include the target file
for dep_file in [dfile for dfile in file_aux.depends_on
if dfile is not file_aux]:
if dep_file in fileset:
name = dep_file.purename
extension = dep_file.extension()
self.write(" \\\n" + os.path.join(
dep_file.library, name, ".%s_%s" %
(name, extension)))
else:
# the file is included -> we depend directly on it
self.write(" \\\n" + dep_file.rel_path())
self.writeln()
self.writeln("\t\tghdl -a $<")
self.write("\t\t@" + path_mod.mkdir_command() + " $(dir $@)")
self.writeln(" && touch $@ \n")
self.writeln()
...@@ -23,11 +23,9 @@ ...@@ -23,11 +23,9 @@
"""Module providing support for IVerilog (Icarus Verilog) simulator""" """Module providing support for IVerilog (Icarus Verilog) simulator"""
import os
import string import string
from .make_sim import ToolSim from .make_sim import ToolSim
from hdlmake.util import path as path_mod
from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile
...@@ -56,8 +54,6 @@ class ToolIVerilog(ToolSim): ...@@ -56,8 +54,6 @@ class ToolIVerilog(ToolSim):
def makefile_sim_compilation(self): def makefile_sim_compilation(self):
"""Generate compile simulation Makefile target for IVerilog""" """Generate compile simulation Makefile target for IVerilog"""
fileset = self.fileset
top_module = self.top_module
self.writeln("simulation: include_dirs $(VERILOG_OBJ) $(VHDL_OBJ)") self.writeln("simulation: include_dirs $(VERILOG_OBJ) $(VHDL_OBJ)")
self.writeln("\t\tiverilog $(IVERILOG_OPT) -s $(TOP_MODULE)" self.writeln("\t\tiverilog $(IVERILOG_OPT) -s $(TOP_MODULE)"
" -o $(TOP_MODULE).vvp -c run.command") " -o $(TOP_MODULE).vvp -c run.command")
...@@ -66,33 +62,12 @@ class ToolIVerilog(ToolSim): ...@@ -66,33 +62,12 @@ class ToolIVerilog(ToolSim):
self.writeln("\t\techo \"# IVerilog command file," self.writeln("\t\techo \"# IVerilog command file,"
" generated by HDLMake\" > run.command") " generated by HDLMake\" > run.command")
self.writeln() self.writeln()
top_module = self.top_module
for inc in top_module.get_include_dirs_list(): for inc in top_module.get_include_dirs_list():
self.writeln("\t\techo \"+incdir+" + inc + "\" >> run.command") self.writeln("\t\techo \"+incdir+" + inc + "\" >> run.command")
self.writeln('\n') self.writeln('\n')
for file_aux in fileset: compilation_command = "echo $< >> run.command"
if any(isinstance(file_aux, file_type) self.makefile_sim_dep_files(compilation_command)
for file_type in self._hdl_files):
self.write("%s: %s" % (os.path.join(
file_aux.library, file_aux.purename,
".%s_%s" % (file_aux.purename, file_aux.extension())),
file_aux.rel_path()))
# list dependencies, do not include the target file
for dep_file in [dfile for dfile in file_aux.depends_on
if dfile is not file_aux]:
if dep_file in fileset:
name = dep_file.purename
extension = dep_file.extension()
self.write(" \\\n" + os.path.join(
dep_file.library, name, ".%s_%s" %
(name, extension)))
else:
# the file is included -> we depend directly on it
self.write(" \\\n" + dep_file.rel_path())
self.writeln()
self.writeln("\t\techo $< >> run.command")
self.write("\t\t@" + path_mod.mkdir_command() + " $(dir $@)")
self.writeln(" && touch $@ \n")
self.writeln()
def makefile_sim_options(self): def makefile_sim_options(self):
"""Print the IVerilog options to the Makefile""" """Print the IVerilog options to the Makefile"""
......
...@@ -4,6 +4,7 @@ import os ...@@ -4,6 +4,7 @@ import os
import string import string
from .makefile import ToolMakefile from .makefile import ToolMakefile
from hdlmake.util import path as path_mod
class ToolSim(ToolMakefile): class ToolSim(ToolMakefile):
...@@ -76,6 +77,34 @@ PWD := $$(shell pwd) ...@@ -76,6 +77,34 @@ PWD := $$(shell pwd)
" \\") " \\")
self.writeln() self.writeln()
def makefile_sim_dep_files(self, compilation_command):
"""Print dummy targets to handle file dependencies"""
fileset = self.fileset
for file_aux in fileset:
if any(isinstance(file_aux, file_type)
for file_type in self._hdl_files):
self.write("%s: %s" % (os.path.join(
file_aux.library, file_aux.purename,
".%s_%s" % (file_aux.purename, file_aux.extension())),
file_aux.rel_path()))
# list dependencies, do not include the target file
for dep_file in [dfile for dfile in file_aux.depends_on
if dfile is not file_aux]:
if dep_file in fileset:
name = dep_file.purename
extension = dep_file.extension()
self.write(" \\\n" + os.path.join(
dep_file.library, name, ".%s_%s" %
(name, extension)))
else:
# the file is included -> we depend directly on it
self.write(" \\\n" + dep_file.rel_path())
self.writeln()
self.writeln("\t\t" + compilation_command)
self.write("\t\t@" + path_mod.mkdir_command() + " $(dir $@)")
self.writeln(" && touch $@ \n")
self.writeln()
def makefile_sim_command(self): def makefile_sim_command(self):
"""Generic method to write the simulation Makefile user commands""" """Generic method to write the simulation Makefile user commands"""
if self.top_module.manifest_dict["sim_pre_cmd"]: if self.top_module.manifest_dict["sim_pre_cmd"]:
......
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