Fixing hierarchical support for Icarus Verilog

parent ceac87ea
......@@ -71,19 +71,14 @@ class ToolIVerilog(ToolSim):
self.writeln("\t\techo \"# IVerilog command file,"
" generated by HDLMake\" > run.command")
self.writeln()
top_module = self.top_module
for inc in top_module.get_include_dirs_list():
for inc in self.manifest_dict.get("include_dirs", []):
self.writeln("\t\techo \"+incdir+" + inc + "\" >> run.command")
self.writeln('\n')
self.makefile_sim_dep_files()
def makefile_sim_options(self):
"""Print the IVerilog options to the Makefile"""
top_module = self.top_module
if top_module.manifest_dict["iverilog_opt"]:
iverilog_opt = top_module.manifest_dict["iverilog_opt"]
else:
iverilog_opt = ''
iverilog_opt = self.manifest_dict.get("iverilog_opt", '')
iverilog_string = string.Template(
"""IVERILOG_OPT := ${iverilog_opt}\n""")
self.writeln(iverilog_string.substitute(
......
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