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9ba2b9f3
Commit
9ba2b9f3
authored
Nov 18, 2021
by
Tristan Gingold
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testsuites: adjust test 093 to avoid non-determinisms
parent
c2129c4a
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3 changed files
with
69 additions
and
1 deletion
+69
-1
Makefile.ref1
testsuite/093multi_sat/Makefile.ref1
+0
-0
Makefile.ref2
testsuite/093multi_sat/Makefile.ref2
+61
-0
test_all.py
testsuite/test_all.py
+8
-1
No files found.
testsuite/093multi_sat/Makefile.ref
→
testsuite/093multi_sat/Makefile.ref
1
View file @
9ba2b9f3
File moved
testsuite/093multi_sat/Makefile.ref2
0 → 100644
View file @
9ba2b9f3
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE
:=
gate3
MODELSIM_INI_PATH
:=
$(HDLMAKE_MODELSIM_PATH)
/..
VCOM_FLAGS
:=
-quiet
-modelsimini
modelsim.ini
VSIM_FLAGS
:=
VLOG_FLAGS
:=
-quiet
-modelsimini
modelsim.ini
VMAP_FLAGS
:=
-modelsimini
modelsim.ini
#target for performing local simulation
local
:
sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC
:=
VERILOG_OBJ
:=
VHDL_SRC
:=
lgate.vhdl
\
../files/gate3.vhd
\
VHDL_OBJ
:=
work/hdlmake/lgate_vhdl
\
work/hdlmake/gate3_vhd
\
INCLUDE_DIRS
:=
LIBS
:=
work
LIB_IND
:=
work/hdlmake/work-stamp
simulation
:
modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ)
:
modelsim.ini
$(VHDL_OBJ)
:
$(LIB_IND) modelsim.ini
modelsim.ini
:
$(MODELSIM_INI_PATH)/modelsim.ini
cp
$<
.
2>&1
work/hdlmake/work-stamp
:
(
vlib work
&&
vmap
$(VMAP_FLAGS)
work
&&
mkdir
-p
work/hdlmake
&&
touch
work/hdlmake/work-stamp
)
||
rm
-rf
work
work/hdlmake/lgate_vhdl
:
lgate.vhdl
vcom
$(VCOM_FLAGS)
-work
work
$<
@
touch
$@
work/hdlmake/gate3_vhd
:
../files/gate3.vhd
\
work/hdlmake/lgate_vhdl
vcom
$(VCOM_FLAGS)
-work
work
$<
@
touch
$@
# USER SIM COMMANDS
sim_pre_cmd
:
sim_post_cmd
:
CLEAN_TARGETS
:=
$(LIBS)
modelsim.ini transcript
clean
:
rm
-rf
$(CLEAN_TARGETS)
mrproper
:
clean
rm
-rf
*
.vcd
*
.wlf
.PHONY
:
mrproper clean sim_pre_cmd sim_post_cmd simulation
testsuite/test_all.py
View file @
9ba2b9f3
...
...
@@ -532,7 +532,14 @@ def test_err_filetype():
assert
False
def
test_multi_sat093
():
run_compare
(
path
=
"093multi_sat"
)
with
Config
(
path
=
"093multi_sat"
):
hdlmake
.
main
.
hdlmake
([])
# Output is not deterministic
ref1
=
open
(
'Makefile.ref1'
,
'r'
)
.
read
()
ref2
=
open
(
'Makefile.ref2'
,
'r'
)
.
read
()
out
=
open
(
'Makefile'
,
'r'
)
.
read
()
assert
out
==
ref1
or
out
==
ref2
os
.
remove
(
'Makefile'
)
def
test_sys_package_097
():
run_compare_xilinx
(
path
=
"097sys_package"
)
...
...
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