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Hdlmake
Commits
954ff749
Commit
954ff749
authored
Jan 12, 2022
by
Tristan Gingold
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Add a test for
#117
and adjust baseline
parent
8864de21
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4 changed files
with
96 additions
and
1 deletion
+96
-1
Makefile.ref
testsuite/114_libero_libraries/Makefile.ref
+1
-1
Makefile.ref
testsuite/117libero_project/Makefile.ref
+78
-0
Manifest.py
testsuite/117libero_project/Manifest.py
+14
-0
test_all.py
testsuite/test_all.py
+3
-0
No files found.
testsuite/114_libero_libraries/Makefile.ref
View file @
954ff749
...
@@ -17,7 +17,7 @@ SYN_DEVICE := M2GL025
...
@@ -17,7 +17,7 @@ SYN_DEVICE := M2GL025
SYN_PACKAGE
:=
484 FBGA
SYN_PACKAGE
:=
484 FBGA
SYN_GRADE
:=
-1
SYN_GRADE
:=
-1
TCL_CREATE
:=
new_project
-location
{
./demo
}
-name
{
demo
}
-hdl
{
VHDL
}
-family
{
IGLOO2
}
-die
{
M2GL025
}
-package
{
484 FBGA
}
-speed
{
-1
}
TCL_CREATE
:=
new_project
-location
{
./demo
}
-name
{
demo
}
-hdl
{
VHDL
}
-family
{
IGLOO2
}
-die
{
M2GL025
}
-package
{
484 FBGA
}
-speed
{
-1
}
TCL_OPEN
:=
open_project
-file
{
$(PROJECT)
/
$(PROJECT_FILE)
}
TCL_OPEN
:=
open_project
-file
{
$(PROJECT)
/
$(PROJECT_FILE)
}
TCL_SAVE
:=
save_project
TCL_SAVE
:=
save_project
TCL_CLOSE
:=
close_project
TCL_CLOSE
:=
close_project
...
...
testsuite/117libero_project/Makefile.ref
0 → 100644
View file @
954ff749
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE
:=
gate
PROJECT
:=
demo
PROJECT_FILE
:=
$(PROJECT)
.prjx
TOOL_PATH
:=
TCL_INTERPRETER
:=
libero SCRIPT:
ifneq
($(strip
$(TOOL_PATH)),)
TCL_INTERPRETER
:=
$(TOOL_PATH)
/
$(TCL_INTERPRETER)
endif
SYN_FAMILY
:=
IGLOO2
SYN_DEVICE
:=
M2GL025
SYN_PACKAGE
:=
484 FBGA
SYN_GRADE
:=
-1
TCL_CREATE
:=
new_project
-location
{
./demo
}
-name
{
demo
}
-hdl
{
VHDL
}
-family
{
IGLOO2
}
-die
{
M2GL025
}
-package
{
484 FBGA
}
-speed
{
-1
}
-adv_options
{
RESTRICTPROBEPINS:0
}
TCL_OPEN
:=
open_project
-file
{
$(PROJECT)
/
$(PROJECT_FILE)
}
TCL_SAVE
:=
save_project
TCL_CLOSE
:=
close_project
ifneq
($(wildcard
$(PROJECT_FILE)),)
TCL_CREATE
:=
$(TCL_OPEN)
endif
#target for performing local synthesis
all
:
bitstream
files.tcl
:
echo
'create_links -hdl_source ../files/gate.vhdl'
>>
$@
SYN_PRE_PROJECT_CMD
:=
SYN_POST_PROJECT_CMD
:=
SYN_PRE_BITSTREAM_CMD
:=
SYN_POST_BITSTREAM_CMD
:=
project.tcl
:
echo
$(TCL_CREATE)
>>
$@
echo source
files.tcl
>>
$@
echo
refresh
>>
$@
echo
set_root
-module
{
$(TOP_MODULE)
}
>>
$@
echo
$(TCL_SAVE)
>>
$@
echo
$(TCL_CLOSE)
>>
$@
project
:
files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER)$@
.tcl LOGFILE:project_output.log
$(SYN_POST_PROJECT_CMD)
touch
$@
bitstream.tcl
:
echo
$(TCL_OPEN)
>>
$@
echo
run_tool
-name
{
GENERATEPROGRAMMINGDATA
}
>>
$@
echo
file
mkdir
./
$(PROJECT)
/bitstream
>>
$@
echo
export_bitstream_file
-file_name
{
$(PROJECT)
}
-export_dir
{
$(PROJECT)
/bitstream
}
-format
{
STP
}
-trusted_facility_file
1
-trusted_facility_file_components
{
FABRIC
}
-serialization_stapl_type
{
SINGLE
}
-serialization_target_solution
{
FLASHPRO_3_4_5
}
>>
$@
echo
$(TCL_SAVE)
>>
$@
echo
$(TCL_CLOSE)
>>
$@
bitstream
:
project bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER)$@
.tcl LOGFILE:bitstream_output.log
$(SYN_POST_BITSTREAM_CMD)
touch
$@
CLEAN_TARGETS
:=
$(LIBS)
$(PROJECT)
*
.log
clean
:
rm
-rf
$(CLEAN_TARGETS)
rm
-rf
project synthesize translate map par bitstream
rm
-rf
project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper
:
clean
rm
-rf
*
.pdb
*
.stp
.PHONY
:
mrproper clean all
testsuite/117libero_project/Manifest.py
0 → 100644
View file @
954ff749
target
=
"microsemi"
action
=
"synthesis"
syn_tool
=
"liberosoc"
syn_family
=
"IGLOO2"
syn_device
=
"M2GL025"
syn_grade
=
"-1"
syn_package
=
"484 FBGA"
syn_top
=
"gate"
syn_project
=
"demo"
project_opt
=
"-adv_options {RESTRICTPROBEPINS:0}"
files
=
[
"../files/gate.vhdl"
]
testsuite/test_all.py
View file @
954ff749
...
@@ -556,6 +556,9 @@ def test_vhdl_libraries_GHDLSyn_115():
...
@@ -556,6 +556,9 @@ def test_vhdl_libraries_GHDLSyn_115():
def
test_vhdl_parser_116
():
def
test_vhdl_parser_116
():
run_compare
(
path
=
"116vhdl_parser"
)
run_compare
(
path
=
"116vhdl_parser"
)
def
test_linerosoc_project_opt_117
():
run_compare
(
path
=
"117libero_project"
)
@
pytest
.
mark
.
xfail
@
pytest
.
mark
.
xfail
def
test_xfail
():
def
test_xfail
():
"""This is a self-consistency test: the test is known to fail"""
"""This is a self-consistency test: the test is known to fail"""
...
...
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