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Commit 7d443b7b authored by Tristan Gingold's avatar Tristan Gingold
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Improve support of Libero. Adjust test.

parent c54d5710
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Showing with 54 additions and 28 deletions
hdlmake/tools/libero.py
View file @ 7d443b7b
......@@ -56,9 +56,9 @@ class ToolLibero(MakefileSyn):
'mrproper': ["*.pdb", "*.stp"]}
TCL_CONTROLS = {
'create': 'new_project -location {{./{0}}} -name {{{0}}}'
' -hdl {{VHDL}} -family {{ProASIC3}} -die {{{1}}}'
' -package {{{2}}} -speed {{{3}}} -die_voltage {{1.5}}',
'create': 'new_project -location {{./{project}}} -name {{{project}}}'
' -hdl {{VHDL}} -family {{{family}}} -die {{{device}}}'
' -package {{{package}}} -speed {{{grade}}} -die_voltage {{1.5}}',
'open': 'open_project -file {$(PROJECT)/$(PROJECT_FILE)}',
'save': 'save_project',
'close': 'close_project',
......@@ -74,6 +74,18 @@ class ToolLibero(MakefileSyn):
'$(TCL_CLOSE)',
'install_source': '$(PROJECT)/designer/impl1/$(SYN_TOP).pdb'}
# Override the build command, because no space is expected between TCL_INTERPRETER and the tcl file
MAKEFILE_SYN_BUILD_CMD="""\
{0}.tcl:
{3}
{0}: {1} {0}.tcl
\t$(SYN_PRE_{2}_CMD)
\t$(TCL_INTERPRETER)$@.tcl
\t$(SYN_POST_{2}_CMD)
\t{4} $@
"""
def __init__(self):
super(ToolLibero, self).__init__()
self._tcl_controls.update(ToolLibero.TCL_CONTROLS)
......@@ -81,14 +93,17 @@ class ToolLibero(MakefileSyn):
def _makefile_syn_tcl(self):
"""Create a Libero synthesis project by TCL"""
syn_project = self.manifest_dict["syn_project"]
syn_family = self.manifest_dict["syn_family"]
syn_device = self.manifest_dict["syn_device"]
syn_grade = self.manifest_dict["syn_grade"]
syn_package = self.manifest_dict["syn_package"]
# Template substitute for 'create'.
create_tmp = self._tcl_controls["create"]
self._tcl_controls["create"] = create_tmp.format(syn_project,
syn_device.upper(),
syn_package.upper(),
syn_grade)
self._tcl_controls["create"] = create_tmp.format(project=syn_project,
family=syn_family,
device=syn_device,
package=syn_package,
grade=syn_grade)
project_tmp = self._tcl_controls["project"]
synthesis_constraints = []
compilation_constraints = []
......
hdlmake/tools/makefilesyn.py
View file @ 7d443b7b
......@@ -22,6 +22,24 @@ class MakefileSyn(ToolMakefile):
"""Class that provides the synthesis Makefile writing methods and status"""
"""Makefile template to build and execute a command.
Arguments:
{0}: name of the stage (project, bitstream, ...)
{1}: prevous stage (for dependency)
{2}: name of the stage, in upper case
{3}: commands to create the tcp script
{4}: touch command"""
MAKEFILE_SYN_BUILD_CMD="""\
{0}.tcl:
{3}
{0}: {1} {0}.tcl
\t\t$(SYN_PRE_{2}_CMD)
\t\t$(TCL_INTERPRETER) $@.tcl
\t\t$(SYN_POST_{2}_CMD)
\t\t{4} $@
"""
def __init__(self):
super(MakefileSyn, self).__init__()
self._tcl_controls = {}
......@@ -148,17 +166,9 @@ endif""")
if shell.check_windows_commands():
command_string = command_string.replace(
"'", "")
self.writeln("""\
{0}.tcl:
{3}
{0}: {1} {0}.tcl
\t\t$(SYN_PRE_{2}_CMD)
\t\t$(TCL_INTERPRETER) $@.tcl
\t\t$(SYN_POST_{2}_CMD)
\t\t{4} $@
""".format(stage, stage_previous, stage.upper(),
command_string, shell.touch_command()))
self.writeln(self.MAKEFILE_SYN_BUILD_CMD.format(
stage, stage_previous, stage.upper(),
command_string, shell.touch_command()))
stage_previous = stage
def _makefile_syn_command(self):
......
testsuite/013libero/Makefile.ref
View file @ 7d443b7b
......@@ -12,12 +12,12 @@ ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY :=
SYN_FAMILY := ProASIC3
SYN_DEVICE := anfpga
SYN_PACKAGE := ff
SYN_GRADE := 3
TCL_CREATE := new_project -location {./gate} -name {gate} -hdl {VHDL} -family {ProASIC3} -die {ANFPGA} -package {FF} -speed {3} -die_voltage {1.5}
TCL_CREATE := new_project -location {./gate} -name {gate} -hdl {VHDL} -family {ProASIC3} -die {anfpga} -package {ff} -speed {3} -die_voltage {1.5}
TCL_OPEN := open_project -file {$(PROJECT)/$(PROJECT_FILE)}
TCL_SAVE := save_project
TCL_CLOSE := close_project
......@@ -58,10 +58,10 @@ project.tcl:
echo $(TCL_CLOSE) >> $@
project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER)$@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
bitstream.tcl:
echo $(TCL_OPEN) >> $@
......@@ -70,10 +70,10 @@ bitstream.tcl:
echo $(TCL_CLOSE) >> $@
bitstream: project bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER)$@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) $(PROJECT)
......
testsuite/013libero/Manifest.py
View file @ 7d443b7b
action = "synthesis"
syn_tool="libero"
syn_family="ProASIC3"
syn_device="anfpga"
syn_grade="3"
syn_package="ff"
......
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