@@ -547,7 +547,6 @@ And for the Verilog synthesis top Manifest.py:
.. code-block:: python
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
...
...
@@ -563,7 +562,6 @@ And for the Verilog synthesis top Manifest.py:
We can see that the only difference is that each of the top synthesis Manifest.py points to its specific Verilog/VHDL top module describing the interface for the constrained FPGA design. The other Manifest.py variables are common for both languages and they means:
- ``target``: specific targeted FPGA architecture
- ``action``: indicates that this is a synthesis process
- ``syn_device``: indicates the specific FPGA device
- ``syn_family``: indicates the specific FPGA family
...
...
@@ -750,6 +748,8 @@ As a very simple example, we can introduce both extra commands in the top synthe
}
.. note:: the ``target`` parameter is used as a condition code variable in this specific example
**Simulation:**
Now, if we want to add external commands to a simulation top makefile, the following parameters must be introduced: