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Projects
Hdlmake
Commits
519edc38
Commit
519edc38
authored
Nov 14, 2014
by
Adrian Fiergolski
Browse files
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Plain Diff
Working on bug 1029.
parent
d82dc290
Hide whitespace changes
Inline
Side-by-side
Showing
3 changed files
with
49 additions
and
47 deletions
+49
-47
srcfile.py
hdlmake/srcfile.py
+5
-2
vhdl_parser.py
hdlmake/vhdl_parser.py
+16
-17
vlog_parser.py
hdlmake/vlog_parser.py
+28
-28
No files found.
hdlmake/srcfile.py
View file @
519edc38
...
@@ -38,11 +38,16 @@ class SourceFile(DepFile):
...
@@ -38,11 +38,16 @@ class SourceFile(DepFile):
assert
isinstance
(
path
,
basestring
)
assert
isinstance
(
path
,
basestring
)
assert
isinstance
(
module
,
Module
)
assert
isinstance
(
module
,
Module
)
self
.
library
=
library
self
.
library
=
library
if
not
library
:
self
.
library
=
"work"
DepFile
.
__init__
(
self
,
DepFile
.
__init__
(
self
,
file_path
=
path
,
file_path
=
path
,
module
=
module
,
module
=
module
,
include_paths
=
module
.
include_dirs
[:])
include_paths
=
module
.
include_dirs
[:])
def
__hash__
(
self
):
return
hash
(
self
.
path
+
self
.
library
)
class
VHDLFile
(
SourceFile
):
class
VHDLFile
(
SourceFile
):
def
__init__
(
self
,
path
,
module
,
library
=
None
,
vcom_opt
=
None
):
def
__init__
(
self
,
path
,
module
,
library
=
None
,
vcom_opt
=
None
):
...
@@ -64,8 +69,6 @@ class VHDLFile(SourceFile):
...
@@ -64,8 +69,6 @@ class VHDLFile(SourceFile):
class
VerilogFile
(
SourceFile
):
class
VerilogFile
(
SourceFile
):
def
__init__
(
self
,
path
,
module
,
library
=
None
,
vlog_opt
=
None
,
include_dirs
=
None
):
def
__init__
(
self
,
path
,
module
,
library
=
None
,
vlog_opt
=
None
,
include_dirs
=
None
):
if
not
library
:
library
=
"work"
SourceFile
.
__init__
(
self
,
path
=
path
,
module
=
module
,
library
=
library
)
SourceFile
.
__init__
(
self
,
path
=
path
,
module
=
module
,
library
=
library
)
if
not
vlog_opt
:
if
not
vlog_opt
:
self
.
vlog_opt
=
""
self
.
vlog_opt
=
""
...
...
hdlmake/vhdl_parser.py
View file @
519edc38
...
@@ -115,34 +115,33 @@ class VHDLParser(DepParser):
...
@@ -115,34 +115,33 @@ class VHDLParser(DepParser):
"arch_begin"
:
"^ *architecture +(
\
w+) +of +(
\
w+) +is +"
,
"arch_begin"
:
"^ *architecture +(
\
w+) +of +(
\
w+) +is +"
,
"arch_end"
:
"^ *end +(
\
w+) +;"
,
"arch_end"
:
"^ *end +(
\
w+) +;"
,
"instance"
:
"^ *(
\
w+) *
\
: *(
\
w+) *(port *map|generic *map| *;)"
,
"instance"
:
"^ *(
\
w+) *
\
: *(
\
w+) *(port *map|generic *map| *;)"
,
"instance_from_
work_library"
:
"^ *(
\
w+) *
\
: *entity *work
*
\
. *(
\
w+) *(port *map|generic *map| *;)"
"instance_from_
library"
:
"^ *(
\
w+) *
\
: *entity *(
\
w+)
*
\
. *(
\
w+) *(port *map|generic *map| *;)"
}
}
compiled_patterns
=
map
(
lambda
p
:
(
p
,
re
.
compile
(
patterns
[
p
])),
patterns
)
compiled_patterns
=
map
(
lambda
p
:
(
p
,
re
.
compile
(
patterns
[
p
])),
patterns
)
within_architecture
=
False
within_architecture
=
False
for
l
in
lines
:
for
l
in
lines
:
matches
=
filter
(
lambda
(
k
,
v
):
v
is
not
None
,
map
(
lambda
(
k
,
v
):
(
k
,
re
.
match
(
v
,
l
.
lower
())),
compiled_patterns
))
matches
=
filter
(
lambda
(
k
,
v
):
v
is
not
None
,
map
(
lambda
(
k
,
v
):
(
k
,
re
.
match
(
v
,
l
.
lower
())),
compiled_patterns
))
if
(
not
len
(
matches
)):
if
(
not
len
(
matches
)):
continue
continue
what
,
g
=
matches
[
0
]
what
,
g
=
matches
[
0
]
switch
=
{
if
(
what
==
"use"
):
if
(
what
==
"use"
):
logging
.
debug
(
"use package
%
s"
%
g
.
group
(
1
)
+
"."
+
g
.
group
(
2
)
)
if
(
g
.
group
(
1
)
.
lower
()
==
"work"
)
:
dep_file
.
add_relation
(
DepRelation
(
g
.
group
(
1
)
+
"."
+
g
.
group
(
2
),
DepRelation
.
USE
,
DepRelation
.
PACKAGE
))
logging
.
debug
(
"use package
%
s.
%
s"
%
(
dep_file
.
library
,
g
.
group
(
2
))
)
dep_file
.
add_relation
(
DepRelation
(
"
%
s.
%
s"
%
(
dep_file
.
library
,
g
.
group
(
2
))
,
DepRelation
.
USE
,
DepRelation
.
PACKAGE
))
#work is a current library in VHDL
else
:
logging
.
debug
(
"use package
%
s.
%
s"
%
(
g
.
group
(
1
),
g
.
group
(
2
))
)
dep_file
.
add_relation
(
DepRelation
(
"
%
s.
%
s"
%
(
g
.
group
(
1
),
g
.
group
(
2
)),
DepRelation
.
USE
,
DepRelation
.
PACKAGE
))
elif
(
what
==
"entity"
):
elif
(
what
==
"entity"
):
logging
.
debug
(
"found entity
%
s"
%
g
.
group
(
1
))
logging
.
debug
(
"found entity
%
s.
%
s"
%
(
dep_file
.
library
,
g
.
group
(
1
)
)
)
dep_file
.
add_relation
(
DepRelation
(
g
.
group
(
1
),
DepRelation
.
PROVIDE
,
DepRelation
.
ENTITY
))
dep_file
.
add_relation
(
DepRelation
(
"
%
s.
%
s"
%
(
dep_file
.
library
,
g
.
group
(
1
)),
dep_file
.
add_relation
(
DepRelation
(
"
%
s.
%
s"
%
(
dep_file
.
library
,
g
.
group
(
1
)),
DepRelation
.
PROVIDE
,
DepRelation
.
PROVIDE
,
DepRelation
.
ENTITY
))
DepRelation
.
ENTITY
))
elif
(
what
==
"package"
):
elif
(
what
==
"package"
):
logging
.
debug
(
"found package
%
s"
%
g
.
group
(
1
))
logging
.
debug
(
"found package
%
s.
%
s"
%
(
dep_file
.
library
,
g
.
group
(
1
)
))
dep_file
.
add_relation
(
DepRelation
(
g
.
group
(
1
),
DepRelation
.
PROVIDE
,
DepRelation
.
PACKAGE
))
dep_file
.
add_relation
(
DepRelation
(
"
%
s.
%
s"
%
(
dep_file
.
library
,
g
.
group
(
1
)),
dep_file
.
add_relation
(
DepRelation
(
"
%
s.
%
s"
%
(
dep_file
.
library
,
g
.
group
(
1
)),
DepRelation
.
PROVIDE
,
DepRelation
.
PROVIDE
,
DepRelation
.
PACKAGE
))
DepRelation
.
PACKAGE
))
...
@@ -151,10 +150,10 @@ class VHDLParser(DepParser):
...
@@ -151,10 +150,10 @@ class VHDLParser(DepParser):
within_architecture
=
True
within_architecture
=
True
elif
(
what
==
"arch_end"
and
within_architecture
and
g
.
group
(
1
)
==
arch_name
):
elif
(
what
==
"arch_end"
and
within_architecture
and
g
.
group
(
1
)
==
arch_name
):
within_architecture
=
False
within_architecture
=
False
elif
(
what
in
[
"instance"
,
"instance_from_
work_
library"
]
and
within_architecture
):
elif
(
what
in
[
"instance"
,
"instance_from_library"
]
and
within_architecture
):
logging
.
debug
(
"-> instantiates
%
s as
%
s"
%
(
g
.
group
(
1
),
g
.
group
(
2
))
)
logging
.
debug
(
"-> instantiates
%
s.
%
s as
%
s"
%
(
dep_file
.
library
,
g
.
group
(
2
),
g
.
group
(
1
))
)
dep_file
.
add_relation
(
DepRelation
(
g
.
group
(
2
),
dep_file
.
add_relation
(
DepRelation
(
"
%
s.
%
s"
%
(
dep_file
.
library
,
g
.
group
(
2
)
),
DepRelation
.
USE
,
DepRelation
.
USE
,
DepRelation
.
ENTITY
))
DepRelation
.
ENTITY
))
dep_file
.
is_parsed
=
True
dep_file
.
is_parsed
=
True
hdlmake/vlog_parser.py
View file @
519edc38
...
@@ -34,19 +34,11 @@ from srcfile import SourceFileFactory
...
@@ -34,19 +34,11 @@ from srcfile import SourceFileFactory
class
VerilogPreprocessor
(
object
):
class
VerilogPreprocessor
(
object
):
# Reserved verilog preprocessor keywords. The list is certainly not full
# Reserved verilog preprocessor keywords. The list is certainly not full
vpp_keywords
=
[
"define"
,
"line"
,
"include"
,
"elsif"
,
"ifdef"
,
"endif"
,
"else"
,
"undef"
,
"timescale"
]
vpp_keywords
=
[
"define"
,
"line"
,
"include"
,
"elsif"
,
"ifdef"
,
"endif"
,
"else"
,
"undef"
,
"timescale"
]
# List of `include search paths
# Verilog `define class
vpp_searchdir
=
[
"."
]
# List of macro definitions
vpp_macros
=
[]
# Dictionary of files sub-included by each file parsed
vpp_filedeps
=
{}
# Verilog `define class
class
VL_Define
(
object
):
class
VL_Define
(
object
):
def
__init__
(
self
,
name
,
args
,
expansion
):
def
__init__
(
self
,
name
,
args
,
expansion
):
self
.
name
=
name
self
.
name
=
name
...
@@ -73,6 +65,13 @@ class VerilogPreprocessor(object):
...
@@ -73,6 +65,13 @@ class VerilogPreprocessor(object):
def
__init__
(
self
):
def
__init__
(
self
):
self
.
vpp_stack
=
self
.
VL_Stack
()
self
.
vpp_stack
=
self
.
VL_Stack
()
self
.
vlog_file
=
None
self
.
vlog_file
=
None
# List of `include search paths
self
.
vpp_searchdir
=
[
"."
]
# List of macro definitions
self
.
vpp_macros
=
[]
# Dictionary of files sub-included by each file parsed
self
.
vpp_filedeps
=
{}
def
_find_macro
(
self
,
name
):
def
_find_macro
(
self
,
name
):
for
m
in
self
.
vpp_macros
:
for
m
in
self
.
vpp_macros
:
...
@@ -137,7 +136,7 @@ class VerilogPreprocessor(object):
...
@@ -137,7 +136,7 @@ class VerilogPreprocessor(object):
self
.
vpp_macros
.
append
(
mdef
)
self
.
vpp_macros
.
append
(
mdef
)
return
mdef
return
mdef
def
_preprocess_file
(
self
,
file_content
,
file_name
):
def
_preprocess_file
(
self
,
file_content
,
file_name
,
library
):
exps
=
{
"include"
:
re
.
compile
(
"^
\
s*`include
\
s+
\"
(.+)
\"
"
),
exps
=
{
"include"
:
re
.
compile
(
"^
\
s*`include
\
s+
\"
(.+)
\"
"
),
"define"
:
re
.
compile
(
"^
\
s*`define
\
s+(
\
w+)(?:
\
(([
\
w
\
s,]*)
\
))?(.*)"
),
"define"
:
re
.
compile
(
"^
\
s*`define
\
s+(
\
w+)(?:
\
(([
\
w
\
s,]*)
\
))?(.*)"
),
"ifdef_elsif"
:
re
.
compile
(
"^
\
s*`(ifdef|ifndef|elsif)
\
s+(
\
w+)
\
s*$"
),
"ifdef_elsif"
:
re
.
compile
(
"^
\
s*`(ifdef|ifndef|elsif)
\
s+(
\
w+)
\
s*$"
),
...
@@ -145,11 +144,11 @@ class VerilogPreprocessor(object):
...
@@ -145,11 +144,11 @@ class VerilogPreprocessor(object):
vl_macro_expand
=
re
.
compile
(
"`(
\
w+)(?:
\
(([
\
w
\
s,]*)
\
))?"
)
vl_macro_expand
=
re
.
compile
(
"`(
\
w+)(?:
\
(([
\
w
\
s,]*)
\
))?"
)
# init dependencies
# init dependencies
self
.
vpp_filedeps
[
file_name
]
=
[]
self
.
vpp_filedeps
[
file_name
+
library
]
=
[]
cur_iter
=
0
cur_iter
=
0
logging
.
debug
(
"preprocess file
%
s (of length
%
d)
"
%
(
file_name
,
len
(
file_content
)
))
logging
.
debug
(
"preprocess file
%
s (of length
%
d)
in library
%
s"
%
(
file_name
,
len
(
file_content
),
library
))
# print("BUF '%s'" %buf)
# print("BUF '%s'" %buf)
buf
=
self
.
_remove_comment
(
file_content
)
buf
=
self
.
_remove_comment
(
file_content
)
while
True
:
while
True
:
...
@@ -188,12 +187,12 @@ class VerilogPreprocessor(object):
...
@@ -188,12 +187,12 @@ class VerilogPreprocessor(object):
if
matches
[
"include"
]:
if
matches
[
"include"
]:
included_file_path
=
self
.
_search_include
(
last
.
group
(
1
),
os
.
path
.
dirname
(
file_name
))
included_file_path
=
self
.
_search_include
(
last
.
group
(
1
),
os
.
path
.
dirname
(
file_name
))
logging
.
debug
(
"File being parsed
%
s
includes
%
s"
%
(
file_name
,
included_file_path
))
logging
.
debug
(
"File being parsed
%
s
(library
%
s) includes
%
s"
%
(
file_name
,
library
,
included_file_path
))
line
=
self
.
_preprocess_file
(
file_content
=
open
(
included_file_path
,
"r"
)
.
read
(),
line
=
self
.
_preprocess_file
(
file_content
=
open
(
included_file_path
,
"r"
)
.
read
(),
file_name
=
included_file_path
)
file_name
=
included_file_path
,
library
=
library
)
self
.
vpp_filedeps
[
file_name
]
.
append
(
included_file_path
)
self
.
vpp_filedeps
[
file_name
+
library
]
.
append
(
included_file_path
)
# add the whole include chain to the dependencies of the currently parsed file
# add the whole include chain to the dependencies of the currently parsed file
self
.
vpp_filedeps
[
file_name
]
.
extend
(
self
.
vpp_filedeps
[
included_file_path
])
self
.
vpp_filedeps
[
file_name
+
library
]
.
extend
(
self
.
vpp_filedeps
[
included_file_path
+
library
])
new_buf
+=
line
+
'
\n
'
new_buf
+=
line
+
'
\n
'
n_expansions
+=
1
n_expansions
+=
1
continue
continue
...
@@ -235,7 +234,7 @@ class VerilogPreprocessor(object):
...
@@ -235,7 +234,7 @@ class VerilogPreprocessor(object):
self
.
vlog_file
=
vlog_file
self
.
vlog_file
=
vlog_file
file_path
=
vlog_file
.
file_path
file_path
=
vlog_file
.
file_path
buf
=
open
(
file_path
,
"r"
)
.
read
()
buf
=
open
(
file_path
,
"r"
)
.
read
()
return
self
.
_preprocess_file
(
file_content
=
buf
,
file_name
=
file_path
)
return
self
.
_preprocess_file
(
file_content
=
buf
,
file_name
=
file_path
,
library
=
vlog_file
.
library
)
def
_find_first
(
self
,
f
,
l
):
def
_find_first
(
self
,
f
,
l
):
x
=
filter
(
f
,
l
)
x
=
filter
(
f
,
l
)
...
@@ -535,6 +534,7 @@ class VerilogParser(DepParser):
...
@@ -535,6 +534,7 @@ class VerilogParser(DepParser):
return
buf2
return
buf2
def
parse
(
self
,
dep_file
):
def
parse
(
self
,
dep_file
):
i
=
0
;
if
dep_file
.
is_parsed
:
if
dep_file
.
is_parsed
:
return
return
logging
.
info
(
"Parsing
%
s"
%
dep_file
.
path
)
logging
.
info
(
"Parsing
%
s"
%
dep_file
.
path
)
...
@@ -561,15 +561,15 @@ class VerilogParser(DepParser):
...
@@ -561,15 +561,15 @@ class VerilogParser(DepParser):
#and HdlMake will anyway create dependency marking my_other_module as requested package
#and HdlMake will anyway create dependency marking my_other_module as requested package
import_pattern
=
re
.
compile
(
"(
\
w+) *::(
\
w+|
\\
*)"
)
import_pattern
=
re
.
compile
(
"(
\
w+) *::(
\
w+|
\\
*)"
)
def
do_imports
(
s
):
def
do_imports
(
s
):
logging
.
debug
(
"file
%
s imports/uses
%
s
package"
%
(
dep_file
.
path
,
s
.
group
(
1
)
)
)
logging
.
debug
(
"file
%
s imports/uses
%
s
.
%
s package"
%
(
dep_file
.
path
,
dep_file
.
library
,
s
.
group
(
1
)
)
)
dep_file
.
add_relation
(
DepRelation
(
s
.
group
(
1
)
,
DepRelation
.
USE
,
DepRelation
.
PACKAGE
))
dep_file
.
add_relation
(
DepRelation
(
"
%
s.
%
s"
%
(
dep_file
.
library
,
s
.
group
(
1
))
,
DepRelation
.
USE
,
DepRelation
.
PACKAGE
))
re
.
subn
(
import_pattern
,
do_imports
,
buf
)
re
.
subn
(
import_pattern
,
do_imports
,
buf
)
#packages
#packages
m_inside_package
=
re
.
compile
(
"package
\
s+(
\
w+)
\
s*(?:
\
(.*?
\
))?
\
s*(.+?)endpackage"
,
re
.
DOTALL
|
re
.
MULTILINE
)
m_inside_package
=
re
.
compile
(
"package
\
s+(
\
w+)
\
s*(?:
\
(.*?
\
))?
\
s*(.+?)endpackage"
,
re
.
DOTALL
|
re
.
MULTILINE
)
def
do_package
(
s
):
def
do_package
(
s
):
logging
.
debug
(
"found pacakge
%
s
"
%
s
.
group
(
1
)
)
logging
.
debug
(
"found pacakge
%
s
.
%
s"
%
(
dep_file
.
library
,
s
.
group
(
1
))
)
dep_file
.
add_relation
(
DepRelation
(
s
.
group
(
1
),
DepRelation
.
PROVIDE
,
DepRelation
.
PACKAGE
))
dep_file
.
add_relation
(
DepRelation
(
"
%
s.
%
s"
%
(
dep_file
.
library
,
s
.
group
(
1
)
),
DepRelation
.
PROVIDE
,
DepRelation
.
PACKAGE
))
re
.
subn
(
m_inside_package
,
do_package
,
buf
)
re
.
subn
(
m_inside_package
,
do_package
,
buf
)
#modules and instatniations
#modules and instatniations
...
@@ -577,15 +577,15 @@ class VerilogParser(DepParser):
...
@@ -577,15 +577,15 @@ class VerilogParser(DepParser):
m_instantiation
=
re
.
compile
(
"(?:
\
A|
\\
s*)
\
s*(
\
w+)
\
s+(?:#
\
s*
\
(.*?
\
)
\
s*)?(
\
w+)
\
s*
\
(.*?
\
)
\
s*"
,
re
.
DOTALL
|
re
.
MULTILINE
)
m_instantiation
=
re
.
compile
(
"(?:
\
A|
\\
s*)
\
s*(
\
w+)
\
s+(?:#
\
s*
\
(.*?
\
)
\
s*)?(
\
w+)
\
s*
\
(.*?
\
)
\
s*"
,
re
.
DOTALL
|
re
.
MULTILINE
)
def
do_module
(
s
):
def
do_module
(
s
):
logging
.
debug
(
"found module
%
s
"
%
s
.
group
(
1
))
logging
.
debug
(
"found module
%
s
.
%
s"
%
(
dep_file
.
library
,
s
.
group
(
1
)
))
dep_file
.
add_relation
(
DepRelation
(
s
.
group
(
1
),
DepRelation
.
PROVIDE
,
DepRelation
.
ENTITY
))
dep_file
.
add_relation
(
DepRelation
(
"
%
s.
%
s"
%
(
dep_file
.
library
,
s
.
group
(
1
)
),
DepRelation
.
PROVIDE
,
DepRelation
.
ENTITY
))
def
do_inst
(
s
):
def
do_inst
(
s
):
mod_name
=
s
.
group
(
1
)
mod_name
=
s
.
group
(
1
)
if
(
mod_name
in
self
.
reserved_words
):
if
(
mod_name
in
self
.
reserved_words
):
return
return
logging
.
debug
(
"-> instantiates
%
s
as
%
s"
%
(
s
.
group
(
1
),
s
.
group
(
2
)
))
logging
.
debug
(
"-> instantiates
%
s
.
%
s as
%
s"
%
(
dep_file
.
library
,
s
.
group
(
1
),
s
.
group
(
2
)
))
dep_file
.
add_relation
(
DepRelation
(
s
.
group
(
1
),
DepRelation
.
USE
,
DepRelation
.
ENTITY
))
dep_file
.
add_relation
(
DepRelation
(
"
%
s.
%
s"
%
(
dep_file
.
library
,
s
.
group
(
1
)
),
DepRelation
.
USE
,
DepRelation
.
ENTITY
))
re
.
subn
(
m_instantiation
,
do_inst
,
s
.
group
(
2
))
re
.
subn
(
m_instantiation
,
do_inst
,
s
.
group
(
2
))
re
.
subn
(
m_inside_module
,
do_module
,
buf
)
re
.
subn
(
m_inside_module
,
do_module
,
buf
)
...
...
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