Use relative imports; create sourcefiles directory and move modules.

513b7183 · Tristan Gingold · a768a46a · 513b7183 · 513b7183 · 513b7183
Commit 513b7183 authored Oct 04, 2019 by Tristan Gingold
34 changed files
--- a/hdlmake/action/action.py
+++ b/hdlmake/action/action.py
@@ -28,11 +28,11 @@ import os
 import logging
 import sys
-from hdlmake.tools.makefile_writer import load_syn_tool, load_sim_tool
+from ..tools.makefile_writer import load_syn_tool, load_sim_tool
-from hdlmake.util import shell
+from ..util import shell
-from hdlmake import new_dep_solver as dep_solver
+from ..sourcefiles import new_dep_solver as dep_solver
-from hdlmake.srcfile import SourceFileSet, VHDLFile, VerilogFile, SVFile
+from ..sourcefiles.srcfile import SourceFileSet, VHDLFile, VerilogFile, SVFile
-from hdlmake.module.module import Module, ModuleArgs
+from ..module.module import Module, ModuleArgs
 class Action(object):

--- a/hdlmake/action/commands.py
+++ b/hdlmake/action/commands.py
@@ -28,14 +28,13 @@ import os
 import sys
 import os.path
-import hdlmake.fetch as fetch
+from ..sourcefiles import new_dep_solver as dep_solver
-import hdlmake.new_dep_solver as dep_solver
+from ..util import path as path_mod
-from hdlmake.util import path as path_mod
+from ..fetch.svn import Svn
-from hdlmake.fetch.svn import Svn
+from ..fetch.git import Git, GitSM
-from hdlmake.fetch.git import Git, GitSM
+from ..fetch.local import Local
-from hdlmake.fetch.local import Local
 from .action import Action
-import hdlmake.util.shell as shell
+from ..util import shell
 class Commands(Action):

--- a/hdlmake/action/tree.py
+++ b/hdlmake/action/tree.py
@@ -22,12 +22,12 @@
 """Module providing graph funtionalities to HDLMake"""
 from __future__ import absolute_import
-from hdlmake.util import path
+from ..util import path
 import logging
 from .action import Action
-from hdlmake.dep_file import DepFile
+from ..sourcefiles.dep_file import DepFile
 class ActionTree(Action):
@@ -88,8 +88,8 @@ class ActionTree(Action):
            self.build_file_set()
            self.solve_file_set()
-            from hdlmake.srcfile import SourceFileSet
+            from ..sourcefiles.srcfile import SourceFileSet
-            from hdlmake.dep_file import DepRelation
+            from ..sourcefiles.dep_file import DepRelation
            assert isinstance(self.parseable_fileset, SourceFileSet)
            fset = self.parseable_fileset.filter(DepFile)
            # Find the file that provides the named top level entity

--- a/hdlmake/fetch/fetcher.py
+++ b/hdlmake/fetch/fetcher.py
@@ -23,7 +23,7 @@
 from __future__ import absolute_import
 import os
-from hdlmake.util import shell
+from ..util import shell
 class Fetcher(object):

--- a/hdlmake/fetch/git.py
+++ b/hdlmake/fetch/git.py
@@ -23,8 +23,8 @@
 from __future__ import absolute_import
 import os
-from hdlmake.util import path as path_utils
+from ..util import path as path_utils
-from hdlmake.util import shell
+from ..util import shell
 from subprocess import PIPE, Popen
 import logging
 from .fetcher import Fetcher

--- a/hdlmake/fetch/svn.py
+++ b/hdlmake/fetch/svn.py
@@ -24,7 +24,7 @@
 from __future__ import absolute_import
 import os
 import logging
-from hdlmake.util import path as path_utils
+from ..util import path as path_utils
 from .fetcher import Fetcher

--- a/hdlmake/main.py
+++ b/hdlmake/main.py
@@ -27,8 +27,8 @@ from __future__ import absolute_import
 import argparse
 import sys
 import logging
-from hdlmake.util import shell
+from .util import shell
-from hdlmake.util.termcolor import colored
+from .util.termcolor import colored
 from .manifest_parser.manifestparser import ManifestParser
 from .action.commands import Commands

--- a/hdlmake/module/content.py
+++ b/hdlmake/module/content.py
@@ -3,8 +3,8 @@ from files to required submodules"""
 from __future__ import absolute_import
 import logging
-from hdlmake.fetch.git import Git
+from ..fetch.git import Git
-from hdlmake.util import path as path_mod
+from ..util import path as path_mod
 from .core import ModuleConfig
 import six
 import os
@@ -53,7 +53,7 @@ class ModuleContent(ModuleConfig):
        Build a Source File Set containing the files indicated by the
        provided list of paths
        """
-        from hdlmake.srcfile import create_source_file, SourceFileSet
+        from ..sourcefiles.srcfile import create_source_file, SourceFileSet
        srcs = SourceFileSet()
        # Check if this is the top module and grab the include_dirs
        if self.parent is None:
@@ -81,7 +81,7 @@ class ModuleContent(ModuleConfig):
    def _process_manifest_files(self):
        """Process the files instantiated by the HDLMake module"""
-        from hdlmake.srcfile import SourceFileSet
+        from ..sourcefiles.srcfile import SourceFileSet
        # HDL files provided by the module
        if "files" not in self.manifest_dict:
            self.files = SourceFileSet()

--- a/hdlmake/module/core.py
+++ b/hdlmake/module/core.py
@@ -5,8 +5,7 @@ import os
 import sys
 import logging
-from hdlmake import fetch
+from ..util import path as path_mod
-from hdlmake.util import path as path_mod
 class ModuleArgs(object):

--- a/hdlmake/module/module.py
+++ b/hdlmake/module/module.py
@@ -32,9 +32,9 @@ from __future__ import absolute_import
 import os
 import logging
-from hdlmake.util import path as path_mod
+from ..util import path as path_mod
-from hdlmake.util import shell
+from ..util import shell
-from hdlmake.manifest_parser.manifestparser import ManifestParser
+from ..manifest_parser.manifestparser import ManifestParser
 from .content import ModuleContent
 from .core import ModuleArgs
 import six

--- a/hdlmake/sourcefiles/__init__.py
+++ b/hdlmake/sourcefiles/__init__.py
--- a/hdlmake/dep_file.py
+++ b/hdlmake/dep_file.py
@@ -26,7 +26,7 @@ from __future__ import print_function
 import os
 import logging
-from .util import path as path_mod
+from ..util import path as path_mod
 import six

--- a/hdlmake/new_dep_solver.py
+++ b/hdlmake/new_dep_solver.py
@@ -27,7 +27,7 @@ from __future__ import print_function
 from __future__ import absolute_import
 import logging
-from .dep_file import DepFile
+from ..sourcefiles.dep_file import DepFile
 class DepParser(object):
@@ -125,8 +125,8 @@ def make_dependency_sorted_list(fileset):
 def make_dependency_set(fileset, top_level_entity, extra_modules=None):
    """Create the set of all files required to build the named
     top_level_entity."""
-    from hdlmake.srcfile import SourceFileSet
+    from ..sourcefiles.srcfile import SourceFileSet
-    from hdlmake.dep_file import DepRelation
+    from ..sourcefiles.dep_file import DepRelation
    assert isinstance(fileset, SourceFileSet)
    fset = fileset.filter(DepFile)

--- a/hdlmake/srcfile.py
+++ b/hdlmake/srcfile.py
@@ -28,7 +28,7 @@ from __future__ import absolute_import
 import os
 import logging
-from .util import path as path_mod
+from ..util import path as path_mod
 from .dep_file import DepFile, File
 import six
@@ -60,7 +60,7 @@ class VHDLFile(SourceFile):
    def __init__(self, path, module, library=None):
        SourceFile.__init__(self, path=path, module=module, library=library)
-        from hdlmake.vhdl_parser import VHDLParser
+        from .vhdl_parser import VHDLParser
        self.parser = VHDLParser(self)
@@ -71,7 +71,7 @@ class VerilogFile(SourceFile):
    def __init__(self, path, module, library=None,
                 include_dirs=None, is_include=False):
        SourceFile.__init__(self, path=path, module=module, library=library)
-        from hdlmake.vlog_parser import VerilogParser
+        from .vlog_parser import VerilogParser
        self.include_dirs = []
        if include_dirs:
            self.include_dirs.extend(include_dirs)
@@ -185,7 +185,7 @@ class XCIFile(SourceFile):
    def __init__(self, path, module, library=None):
        SourceFile.__init__(self, path=path, module=module, library=library)
-        from hdlmake.xci_parser import XCIParser
+        from .xci_parser import XCIParser
        self.parser = XCIParser(self)
 XILINX_FILE_DICT = {

--- a/hdlmake/vhdl_parser.py
+++ b/hdlmake/vhdl_parser.py
--- a/hdlmake/vlog_parser.py
+++ b/hdlmake/vlog_parser.py
@@ -34,7 +34,7 @@ import logging
 from .new_dep_solver import DepParser
 from .dep_file import DepRelation
-from hdlmake.srcfile import create_source_file
+from .srcfile import create_source_file
 from collections import namedtuple
 import six
@@ -262,7 +262,6 @@ class VerilogPreprocessor(object):
        # init dependencies
        self.vpp_filedeps[file_name + library] = []
-        cur_iter = 0
        logging.debug("preprocess file %s (of length %d) in library %s",
                      file_name, len(file_content), library)
        buf = _filter_protected_regions(_remove_comment(file_content))

--- a/hdlmake/xci_parser.py
+++ b/hdlmake/xci_parser.py
@@ -28,7 +28,7 @@ from xml.etree import ElementTree as ET
 from .new_dep_solver import DepParser
 from .dep_file import DepRelation
-from hdlmake.srcfile import create_source_file
+from ..sourcefiles.srcfile import create_source_file
 class XCIParser(DepParser):
    """Class providing the Xilinx XCI parser"""

--- a/hdlmake/tools/active_hdl.py
+++ b/hdlmake/tools/active_hdl.py
@@ -25,7 +25,7 @@
 from __future__ import absolute_import
 from .makefilesim import MakefileSim
-from hdlmake.srcfile import VHDLFile, VerilogFile, SVFile
+from ..sourcefiles.srcfile import VHDLFile, VerilogFile, SVFile
 class ToolActiveHDL(MakefileSim):

--- a/hdlmake/tools/diamond.py
+++ b/hdlmake/tools/diamond.py
@@ -26,7 +26,7 @@
 from __future__ import absolute_import
 from .makefilesyn import MakefileSyn
-from hdlmake.srcfile import EDFFile, LPFFile, VHDLFile, VerilogFile
+from ..sourcefiles.srcfile import EDFFile, LPFFile, VHDLFile, VerilogFile
 class ToolDiamond(MakefileSyn):

--- a/hdlmake/tools/ghdl.py
+++ b/hdlmake/tools/ghdl.py
@@ -27,7 +27,7 @@ from __future__ import absolute_import
 import string
 from .makefilesim import MakefileSim
-from hdlmake.srcfile import VHDLFile
+from ..sourcefiles.srcfile import VHDLFile
 class ToolGHDL(MakefileSim):

--- a/hdlmake/tools/icestorm.py
+++ b/hdlmake/tools/icestorm.py
@@ -26,7 +26,7 @@
 from __future__ import absolute_import
 from .makefilesyn import MakefileSyn
-from hdlmake.srcfile import VerilogFile, PCFFile
+from ..sourcefiles.srcfile import VerilogFile, PCFFile
 class ToolIcestorm(MakefileSyn):

--- a/hdlmake/tools/ise.py
+++ b/hdlmake/tools/ise.py
@@ -29,9 +29,9 @@ import logging
 from .makefilesyn import MakefileSyn
-from hdlmake.util import shell
+from ..util import shell
-from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile,
+from ..sourcefiles.srcfile import (VHDLFile, VerilogFile, SVFile,
-                             UCFFile, CDCFile, NGCFile, BMMFile, XCOFile)
+                                   UCFFile, CDCFile, NGCFile, BMMFile, XCOFile)
 FAMILY_NAMES = {
    "XC6S": "Spartan6",

--- a/hdlmake/tools/isim.py
+++ b/hdlmake/tools/isim.py
@@ -31,8 +31,8 @@ import os.path
 import logging
 from .makefilesim import MakefileSim
-from hdlmake.util import shell
+from ..util import shell
-from hdlmake.srcfile import VerilogFile, VHDLFile
+from ..sourcefiles.srcfile import VerilogFile, VHDLFile
 class ToolISim(MakefileSim):

--- a/hdlmake/tools/iverilog.py
+++ b/hdlmake/tools/iverilog.py
@@ -27,7 +27,7 @@ from __future__ import absolute_import
 import string
 from .makefilesim import MakefileSim
-from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile
+from ..sourcefiles.srcfile import VerilogFile, VHDLFile, SVFile
 class ToolIVerilog(MakefileSim):

--- a/hdlmake/tools/libero.py
+++ b/hdlmake/tools/libero.py
@@ -26,7 +26,7 @@
 from __future__ import absolute_import
 from .makefilesyn import MakefileSyn
-from hdlmake.srcfile import VHDLFile, VerilogFile, SDCFile, PDCFile
+from ..sourcefiles.srcfile import VHDLFile, VerilogFile, SDCFile, PDCFile
 class ToolLibero(MakefileSyn):

--- a/hdlmake/tools/makefile.py
+++ b/hdlmake/tools/makefile.py
@@ -28,7 +28,7 @@ import os
 import logging
 import six
-from hdlmake.util import shell
+from ..util import shell
 class ToolMakefile(object):

--- a/hdlmake/tools/makefilesim.py
+++ b/hdlmake/tools/makefilesim.py
@@ -6,8 +6,8 @@ import sys
 import logging
 from .makefile import ToolMakefile
-from hdlmake.util import shell
+from ..util import shell
-from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile
+from ..sourcefiles.srcfile import VerilogFile, VHDLFile, SVFile
 def _check_simulation_manifest(manifest_dict):

--- a/hdlmake/tools/makefilesyn.py
+++ b/hdlmake/tools/makefilesyn.py
@@ -5,9 +5,9 @@ import os, sys
 import logging
 from .makefile import ToolMakefile
-from hdlmake.util import shell
+from ..util import shell
-from hdlmake.srcfile import VerilogFile, SVFile
+from ..sourcefiles.srcfile import VerilogFile, SVFile
 def _check_synthesis_manifest(manifest_dict):

--- a/hdlmake/tools/makefilevsim.py
+++ b/hdlmake/tools/makefilevsim.py
@@ -28,8 +28,8 @@ import os
 import string
 from .makefilesim import MakefileSim
-from hdlmake.util import shell
+from ..util import shell
-from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile
+from ..sourcefiles.srcfile import VerilogFile, VHDLFile, SVFile
 import six

--- a/hdlmake/tools/planahead.py
+++ b/hdlmake/tools/planahead.py
@@ -25,7 +25,7 @@
 from __future__ import absolute_import
 from .xilinx import ToolXilinx
-from hdlmake.srcfile import (UCFFile, NGCFile, XMPFile, XCOFile, BMMFile)
+from ..sourcefiles.srcfile import (UCFFile, NGCFile, XMPFile, XCOFile, BMMFile)
 class ToolPlanAhead(ToolXilinx):

--- a/hdlmake/tools/quartus.py
+++ b/hdlmake/tools/quartus.py
@@ -29,11 +29,11 @@ import sys
 import logging
 from .makefilesyn import MakefileSyn
-from hdlmake.util import path as path_mod
+from ..util import path as path_mod
-from hdlmake.util import shell
+from ..util import shell
-from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile, DPFFile,
+from ..sourcefiles.srcfile import (VHDLFile, VerilogFile, SVFile, DPFFile,
-                             SignalTapFile, SDCFile, QIPFile, QSYSFile,
+                                   SignalTapFile, SDCFile, QIPFile, QSYSFile,
-                             QSFFile, BSFFile, BDFFile, TDFFile, GDFFile)
+                                   QSFFile, BSFFile, BDFFile, TDFFile, GDFFile)
 class ToolQuartus(MakefileSyn):

--- a/hdlmake/tools/vivado.py
+++ b/hdlmake/tools/vivado.py
@@ -26,10 +26,10 @@
 from __future__ import absolute_import
 from .xilinx import ToolXilinx
-from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile,
+from ..sourcefiles.srcfile import (VHDLFile, VerilogFile, SVFile,
-                             XDCFile, XCIFile, NGCFile, XMPFile,
+                                   XDCFile, XCIFile, NGCFile, XMPFile,
-                             XCOFile, COEFile, BDFile, TCLFile, BMMFile,
+                                   XCOFile, COEFile, BDFile, TCLFile, BMMFile,
-                             MIFFile, RAMFile, VHOFile, VEOFile, XCFFile)
+                                   MIFFile, RAMFile, VHOFile, VEOFile, XCFFile)
 class ToolVivado(ToolXilinx):

--- a/hdlmake/tools/vivado_sim.py
+++ b/hdlmake/tools/vivado_sim.py
@@ -26,7 +26,7 @@
 from __future__ import absolute_import
 from .makefilesim import MakefileSim
-from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile
+from ..sourcefiles.srcfile import VerilogFile, VHDLFile, SVFile
 class ToolVivadoSim(MakefileSim):

--- a/hdlmake/tools/xilinx.py
+++ b/hdlmake/tools/xilinx.py
@@ -26,7 +26,7 @@
 from __future__ import absolute_import
 from .makefilesyn import MakefileSyn
-from hdlmake.srcfile import VHDLFile, VerilogFile, SVFile, TCLFile
+from ..sourcefiles.srcfile import VHDLFile, VerilogFile, SVFile, TCLFile
 import logging