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Hdlmake
Commit 50f030e3 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Module is now independent from simulation

parent 47c2d853
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Showing with 77 additions and 166 deletions
hdlmake/__main__.py
View file @ 50f030e3
......@@ -126,11 +126,11 @@ def _action_runner(modules_pool):
"Otherwise hdlmake doesn't know how to handle the project.")
quit()
if top_mod.action == "simulation":
if not top_mod.sim_tool:
if not top_mod.manifest_dict["sim_tool"]:
logging.error("`sim_tool' manifest variable has to be specified. "
"Otherwise hdlmake doesn't know how to simulate the project.")
quit()
top_mod.top_entity = top_mod.sim_top
top_mod.top_entity = top_mod.manifest_dict["sim_top"]
action = [
GenerateSimulationMakefile,
]
......
hdlmake/action/simulation.py
View file @ 50f030e3
......@@ -33,10 +33,10 @@ from .action import Action
class GenerateSimulationMakefile(Action):
def _check_manifest(self):
if not self.modules_pool.get_top_module().sim_top:
if not self.modules_pool.get_top_module().manifest_dict["sim_top"]:
logging.error("sim_top variable must be set in the top manifest.")
sys.exit("Exiting")
if not self.modules_pool.get_top_module().sim_tool:
if not self.modules_pool.get_top_module().manifest_dict["sim_tool"]:
logging.error("sim_tool variable must be set in the top manifest.")
sys.exit("Exiting")
......@@ -44,7 +44,7 @@ class GenerateSimulationMakefile(Action):
def run(self):
self._check_all_fetched_or_quit()
self._check_manifest()
tool_name = self.modules_pool.get_top_module().sim_tool
tool_name = self.modules_pool.get_top_module().manifest_dict["sim_tool"]
try:
tool_module = importlib.import_module("hdlmake.tools.%s.%s" % (tool_name, tool_name))
except Exception as e:
......
hdlmake/dep_file.py
View file @ 50f030e3
......@@ -140,7 +140,7 @@ class File(object):
class DepFile(File):
def __init__(self, file_path, module, include_paths=None):
def __init__(self, file_path, module):
from .module import Module
assert isinstance(file_path, basestring)
assert isinstance(module, Module)
......@@ -152,14 +152,9 @@ class DepFile(File):
self._outputs = set()
self.depends_on = set() # set of files that the file depends on, items of type DepFile
self.dep_level = None
self.is_parsed = False
if include_paths is None:
include_paths = []
else:
pass
self.file_path = file_path
self.include_paths = include_paths
self.include_paths = []
def parse_if_needed(self):
logging.debug("Parse %s if needed!!!" % self.file_path)
......
hdlmake/manifest_parser.py
View file @ 50f030e3
......@@ -126,9 +126,6 @@ class ManifestParser(ConfigParser):
#Adding option for including makefile snippets
self.add_option('incl_makefiles', default=[], help="List of .mk files appended to toplevel makefile", type=[])
self.add_type('incl_makefiles', type='')
# Disallow certain files in Xilinx Synthesis flow but use in simulation
self.add_option('sim_only_files', default=[], help="List of files that are used only in simulation", type=[])
self.add_type('sim_only_files', type='')
def add_manifest(self, path):
manifest = self._search_for_manifest(path)
......
hdlmake/module/__init__.py
View file @ 50f030e3
"""Package providing the Module functionality to HDLMake"""
from .core import ModuleCore
from .synthesis import ModuleSynthesis
from .simulation import ModuleSimulation
from .content import ModuleContent
from .altera import ModuleAltera
from .module import Module, ModuleArgs
......
hdlmake/module/module.py
View file @ 50f030e3
......@@ -31,9 +31,9 @@ from __future__ import print_function
import os
import logging
from hdlmake.util import path as path_mod
from hdlmake.manifest_parser import ManifestParser
from hdlmake.module import (ModuleSynthesis,
ModuleSimulation, ModuleContent, ModuleAltera)
from hdlmake.module import ModuleContent, ModuleAltera
class ModuleArgs(object):
......@@ -56,8 +56,7 @@ class ModuleArgs(object):
return self.parent, self.url, self.source, self.fetchto
class Module(ModuleSynthesis,
ModuleSimulation, ModuleContent, ModuleAltera):
class Module(ModuleContent, ModuleAltera):
"""
This is the class providing the HDLMake module, the basic element
providing the modular behavior allowing for structured designs.
......@@ -125,13 +124,40 @@ class Module(ModuleSynthesis,
def _set_simulation_options(self):
"""This set the simulation option for all the files in the Module"""
from hdlmake.srcfile import VerilogFile, VHDLFile
include_dirs_list = self.get_include_dirs_list()
for file_aux in self.files:
if isinstance(file_aux, VerilogFile):
file_aux.vsim_opt = self.sim_opt.vsim_opt
file_aux.include_dirs = self.include_dirs
file_aux.vsim_opt = self.manifest_dict["vsim_opt"]
file_aux.include_dirs = include_dirs_list
elif isinstance(file_aux, VHDLFile):
file_aux.vcom_opt = self.sim_opt.vcom_opt
file_aux.include_dirs = self.include_dirs
file_aux.vcom_opt = self.manifest_dict["vcom_opt"]
def get_include_dirs_list(self):
"""Private method that processes the included directory list"""
# Include dirs
include_dirs = []
if self.manifest_dict["include_dirs"] is not None:
if isinstance(self.manifest_dict["include_dirs"], basestring):
dir_list = path_mod.compose(
self.path, self.manifest_dict["include_dirs"])
include_dirs.append(dir_list)
else:
dir_list = [path_mod.compose(self.path, x) for
x in self.manifest_dict["include_dirs"]]
include_dirs.extend(dir_list)
# Analyze included dirs and report if any issue is found
for dir_ in include_dirs:
if path_mod.is_abs_path(dir_):
logging.warning(
"%s contains absolute path to an include directory: %s",
self.path, dir_)
if not os.path.exists(dir_):
logging.warning(self.path +
" has an unexisting include directory: " + dir_)
return include_dirs
def parse_manifest(self):
......
hdlmake/module/simulation.py deleted 100644 → 0
View file @ 47c2d853
"""This module is in charge of providing everything related with simulation
at the Module level"""
import os
import logging
from .core import ModuleCore
from hdlmake.util import path as path_mod
class SimulatorOptions(object):
"""Class providing a storage for simulator options"""
def __init__(self):
self.vsim_opt = None
self.vmap_opt = None
self.vlog_opt = None
self.vcom_opt = None
self.iverilog_opt = None
def set_standard_options(self, vsim_opt, vmap_opt, vlog_opt, vcom_opt):
"""Set the standard simulator options, i.e. vsim, vmap, vlog, vcom"""
self.vsim_opt = vsim_opt
self.vmap_opt = vmap_opt
self.vlog_opt = vlog_opt
self.vcom_opt = vcom_opt
def set_iverilog_options(self, iverilog_opt):
"""Set the specific options for Icarus Verilog"""
self.iverilog_opt = iverilog_opt
class ModuleSimulation(ModuleCore):
"""This Class provides the HDLMake properties and methods
the Module requires for the simulation action"""
def __init__(self):
# Manifest Simulation Properties
self.sim_top = None
self.sim_tool = None
self.sim_pre_cmd = None
self.sim_post_cmd = None
self.sim_only_files = None
self.sim_opt = SimulatorOptions()
# Includes Manifest Properties
self.include_dirs = None
super(ModuleSimulation, self).__init__()
def process_manifest(self):
"""Method that processes the simulation section in the manifest"""
self._process_manifest_simulation()
self._process_manifest_includes()
super(ModuleSimulation, self).process_manifest()
def _process_manifest_simulation(self):
"""Private method that processes options and universal sim keys"""
from hdlmake.srcfile import SourceFileSet
# Simulation properties
self.sim_tool = self.manifest_dict["sim_tool"]
self.sim_top = self.manifest_dict["sim_top"]
self.sim_pre_cmd = self.manifest_dict["sim_pre_cmd"]
self.sim_post_cmd = self.manifest_dict["sim_post_cmd"]
self.sim_opt.vsim_opt = self.manifest_dict["vsim_opt"]
self.sim_opt.vmap_opt = self.manifest_dict["vmap_opt"]
self.sim_opt.vlog_opt = self.manifest_dict["vlog_opt"]
self.sim_opt.vcom_opt = self.manifest_dict["vcom_opt"]
self.sim_opt.set_standard_options(
self.manifest_dict["vsim_opt"],
self.manifest_dict["vmap_opt"],
self.manifest_dict["vlog_opt"],
self.manifest_dict["vcom_opt"]
)
self.sim_opt.set_iverilog_options(self.manifest_dict["iverilog_opt"])
if len(self.manifest_dict["sim_only_files"]) == 0:
self.sim_only_files = SourceFileSet()
else:
self.manifest_dict["sim_only_files"] = path_mod.flatten_list(
self.manifest_dict["sim_only_files"])
paths = self._make_list_of_paths(
self.manifest_dict["sim_only_files"])
self.sim_only_files = self._create_file_list_from_paths(
paths=paths)
def _process_manifest_includes(self):
"""Private method that processes the included directory list"""
# Include dirs
self.include_dirs = []
if self.manifest_dict["include_dirs"] is not None:
if isinstance(self.manifest_dict["include_dirs"], basestring):
dir_list = path_mod.compose(
self.path, self.manifest_dict["include_dirs"])
self.include_dirs.append(dir_list)
else:
dir_list = [path_mod.compose(self.path, x) for
x in self.manifest_dict["include_dirs"]]
self.include_dirs.extend(dir_list)
# Analyze included dirs and report if any issue is found
for dir_ in self.include_dirs:
if path_mod.is_abs_path(dir_):
logging.warning(
"%s contains absolute path to an include directory: %s",
self.path, dir_)
if not os.path.exists(dir_):
logging.warning(self.path +
" has an unexisting include directory: " + dir_)
hdlmake/srcfile.py
View file @ 50f030e3
......@@ -32,7 +32,7 @@ from .dep_file import DepFile, File
class SourceFile(DepFile):
cur_index = 0
def __init__(self, path, module, library=None):
def __init__(self, path, module, library):
from .dep_file import DepFile
assert isinstance(path, basestring)
assert isinstance(module, Module)
......@@ -41,8 +41,7 @@ class SourceFile(DepFile):
self.library = "work"
DepFile.__init__(self,
file_path=path,
module=module,
include_paths=module.include_dirs[:])
module=module)
def __hash__(self):
return hash(self.path + self.library)
......
hdlmake/tools/aldec/aldec.py
View file @ 50f030e3
......@@ -107,16 +107,17 @@ mrproper: clean
""")
if top_module.sim_pre_cmd:
sim_pre_cmd = top_module.sim_pre_cmd
if top_module.manifest_dict["sim_pre_cmd"]:
sim_pre_cmd = top_module.manifest_dict["sim_pre_cmd"]
else:
sim_pre_cmd = ''
if top_module.sim_post_cmd:
sim_post_cmd = top_module.sim_post_cmd
if top_module.manifest_dict["sim_post_cmd"]:
sim_post_cmd = top_module.manifest_dict["sim_post_cmd"]
else:
sim_post_cmd = ''
makefile_text_2 = makefile_tmplt_2.substitute(
sim_pre_cmd=sim_pre_cmd,
sim_post_cmd=sim_post_cmd,
......
hdlmake/tools/common/sim_makefile_support.py
View file @ 50f030e3
......@@ -75,10 +75,10 @@ class VsimMakefileWriter(MakefileWriter):
mkdir_command = "mkdir -p"
slash_char = "/"
self.vlog_flags.append(self.__get_rid_of_vsim_incdirs(top_module.sim_opt.vlog_opt))
self.vcom_flags.append(top_module.sim_opt.vcom_opt)
self.vmap_flags.append(top_module.sim_opt.vmap_opt)
self.vsim_flags.append(top_module.sim_opt.vsim_opt)
self.vlog_flags.append(self.__get_rid_of_vsim_incdirs(top_module.manifest_dict["vlog_opt"]))
self.vcom_flags.append(top_module.manifest_dict["vcom_opt"])
self.vmap_flags.append(top_module.manifest_dict["vmap_opt"])
self.vsim_flags.append(top_module.manifest_dict["vsim_opt"])
tmp = """## variables #############################
PWD := $(shell pwd)
......@@ -148,15 +148,17 @@ sim_post_cmd:
\t\t${sim_post_cmd}
""")
if top_module.sim_pre_cmd:
sim_pre_cmd = top_module.sim_pre_cmd
if top_module.manifest_dict["sim_pre_cmd"]:
sim_pre_cmd = top_module.manifest_dict["sim_pre_cmd"]
else:
sim_pre_cmd = ''
if top_module.sim_post_cmd:
sim_post_cmd = top_module.sim_post_cmd
if top_module.manifest_dict["sim_post_cmd"]:
sim_post_cmd = top_module.manifest_dict["sim_post_cmd"]
else:
sim_post_cmd = ''
simcommands = simcommands.substitute(sim_pre_cmd=sim_pre_cmd,
sim_post_cmd=sim_post_cmd)
self.write(simcommands)
......
hdlmake/tools/ghdl/ghdl.py
View file @ 50f030e3
......@@ -100,16 +100,17 @@ mrproper: clean
""")
if top_module.sim_pre_cmd:
sim_pre_cmd = top_module.sim_pre_cmd
if top_module.manifest_dict["sim_pre_cmd"]:
sim_pre_cmd = top_module.manifest_dict["sim_pre_cmd"]
else:
sim_pre_cmd = ''
if top_module.sim_post_cmd:
sim_post_cmd = top_module.sim_post_cmd
if top_module.manifest_dict["sim_post_cmd"]:
sim_post_cmd = top_module.manifest_dict["sim_post_cmd"]
else:
sim_post_cmd = ''
makefile_text_2 = makefile_tmplt_2.substitute(
sim_pre_cmd=sim_pre_cmd,
sim_post_cmd=sim_post_cmd,
......
hdlmake/tools/isim/isim.py
View file @ 50f030e3
......@@ -87,7 +87,7 @@ XILINX_INI_PATH := """ + self.__get_xilinxsim_ini_dir(top_module.pool.env) + """
VHPCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini
ISIM_FLAGS :=
VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini """ + self.__get_rid_of_isim_incdirs(top_module.sim_opt.vlog_opt) + """
VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini """ + self.__get_rid_of_isim_incdirs(top_module.manifest_dict["vlog_opt"]) + """
"""
make_preambule_p2 = string.Template("""## rules #################################
local: sim_pre_cmd simulation sim_post_cmd
......@@ -152,13 +152,13 @@ isim.wdb isim_proj isim_proj.*
self.write(' '.join([lib+"/."+lib for lib in libs]))
self.write('\n')
if top_module.sim_pre_cmd:
sim_pre_cmd = top_module.sim_pre_cmd
if top_module.manifest_dict["sim_pre_cmd"]:
sim_pre_cmd = top_module.manifest_dict["sim_pre_cmd"]
else:
sim_pre_cmd = ''
if top_module.sim_post_cmd:
sim_post_cmd = top_module.sim_post_cmd
if top_module.manifest_dict["sim_post_cmd"]:
sim_post_cmd = top_module.manifest_dict["sim_post_cmd"]
else:
sim_post_cmd = ''
......
hdlmake/tools/iverilog/iverilog.py
View file @ 50f030e3
......@@ -92,7 +92,7 @@ simulation:
self.writeln("\t\techo \"# IVerilog command file, generated by HDLMake\" > run.command")
for inc in top_module.include_dirs:
for inc in top_module.get_include_dirs_list():
self.writeln("\t\techo \"+incdir+" + inc + "\" >> run.command")
for vl in fileset.filter(VerilogFile):
......@@ -125,21 +125,22 @@ mrproper: clean
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
""")
if top_module.sim_opt.iverilog_opt:
iverilog_opt = top_module.sim_opt.iverilog_opt
if top_module.manifest_dict["iverilog_opt"]:
iverilog_opt = top_module.manifest_dict["iverilog_opt"]
else:
iverilog_opt = ''
if top_module.sim_pre_cmd:
sim_pre_cmd = top_module.sim_pre_cmd
if top_module.manifest_dict["sim_pre_cmd"]:
sim_pre_cmd = top_module.manifest_dict["sim_pre_cmd"]
else:
sim_pre_cmd = ''
if top_module.sim_post_cmd:
sim_post_cmd = top_module.sim_post_cmd
if top_module.manifest_dict["sim_post_cmd"]:
sim_post_cmd = top_module.manifest_dict["sim_post_cmd"]
else:
sim_post_cmd = ''
makefile_text_2 = makefile_tmplt_2.substitute(
iverilog_opt=iverilog_opt,
sim_pre_cmd=sim_pre_cmd,
......
hdlmake/util/configparser.py
View file @ 50f030e3
......@@ -238,7 +238,7 @@ class ConfigParser(object):
assert isinstance(extra_context, dict) or extra_context is None
# These hdlmake keys wont be inherited
key_purge_list = ["modules", "files", "include_dirs", "sim_only_files",
key_purge_list = ["modules", "files", "include_dirs",
"inc_makefiles", "library"]
for key_to_be_deleted in key_purge_list:
extra_context.pop(key_to_be_deleted, None)
......
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