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Hdlmake
Commits
4ecc0baa
Commit
4ecc0baa
authored
Aug 01, 2013
by
Paweł Szostek
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makefile writer: write single mkfile per hdlmake run
parent
190d9fb9
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Showing
6 changed files
with
61 additions
and
41 deletions
+61
-41
action.py
hdlmake/action/action.py
+8
-7
ise_makefile.py
hdlmake/action/ise_makefile.py
+3
-2
remote_synthesis.py
hdlmake/action/remote_synthesis.py
+2
-1
simulation.py
hdlmake/action/simulation.py
+4
-3
global_mod.py
hdlmake/global_mod.py
+3
-0
makefile_writer.py
hdlmake/makefile_writer.py
+41
-28
No files found.
hdlmake/action/action.py
View file @
4ecc0baa
...
...
@@ -10,7 +10,6 @@ class Action(object):
self
.
modules_pool
=
modules_pool
self
.
options
=
options
self
.
env
=
env
self
.
make_writer
=
MakefileWriter
()
self
.
_check_manifest
()
self
.
_check_env
()
...
...
@@ -35,15 +34,17 @@ class Action(object):
def
_check_all_fetched_or_quit
(
self
):
pool
=
self
.
modules_pool
if
not
pool
.
is_everything_fetched
():
logging
.
error
(
"A module remains unfetched. "
"Fetching must be done prior to makefile generation"
)
print
(
str
([
str
(
m
)
for
m
in
self
.
modules_pool
if
not
m
.
isfetched
]))
sys
.
exit
(
"Exiting."
)
logging
.
error
(
"At least one module remains unfetched. "
"Fetching must be done before makefile generation."
)
print
(
"
\n
Unfetched modules:"
)
print
(
'
\n
'
.
join
([
str
(
m
)
for
m
in
self
.
modules_pool
if
not
m
.
isfetched
]))
sys
.
exit
(
"
\n
Exiting."
)
def
_check_manifest_variable_is_set
(
self
,
name
):
if
getattr
(
self
.
top_module
,
name
)
is
None
:
logging
.
error
(
"Variable
%
s must be set in the manifest to perform current action"
,
name
)
sys
.
exit
(
"Exiting"
)
logging
.
error
(
"Variable
%
s must be set in the manifest to perform current action (
%
s)"
%
(
name
,
self
.
__class__
.
__name__
))
sys
.
exit
(
"
\n
Exiting"
)
def
_check_manifest_variable_is_equal_to
(
self
,
name
,
value
):
ok
=
False
...
...
hdlmake/action/ise_makefile.py
View file @
4ecc0baa
from
__future__
import
print_function
from
action
import
Action
import
logging
import
global_mod
class
GenerateISEMakefile
(
Action
):
...
...
@@ -9,7 +10,7 @@ class GenerateISEMakefile(Action):
global_mod
.
mod_pool
=
self
.
modules_pool
logging
.
info
(
"Generating makefile for local synthesis."
)
ise_path
=
global_mod
.
env
[
"ise_path"
]
ise_path
=
global_mod
.
env
[
"ise_path"
]
self
.
mak
e_writer
.
generate_ise_makefile
(
top_mod
=
self
.
modules_pool
.
get_top_module
(),
global_mod
.
makefil
e_writer
.
generate_ise_makefile
(
top_mod
=
self
.
modules_pool
.
get_top_module
(),
ise_path
=
ise_path
)
hdlmake/action/remote_synthesis.py
View file @
4ecc0baa
...
...
@@ -3,6 +3,7 @@ from action import Action
import
logging
import
os
import
sys
import
global_mod
from
srcfile
import
SourceFileFactory
...
...
@@ -24,7 +25,7 @@ class GenerateRemoteSynthesisMakefile(Action):
files
.
add
(
sff
.
new
(
tcl
,
module
=
None
))
files
.
add
(
sff
.
new
(
top_mod
.
syn_project
,
module
=
None
))
self
.
mak
e_writer
.
generate_remote_synthesis_makefile
(
files
=
files
,
name
=
top_mod
.
syn_name
,
global_mod
.
makefil
e_writer
.
generate_remote_synthesis_makefile
(
files
=
files
,
name
=
top_mod
.
syn_name
,
cwd
=
os
.
getcwd
(),
user
=
self
.
env
[
"rsynth_user"
],
server
=
self
.
env
[
"rsynth_server"
])
...
...
hdlmake/action/simulation.py
View file @
4ecc0baa
...
...
@@ -4,6 +4,7 @@ from action import Action
import
logging
import
dep_solver
import
sys
import
global_mod
class
GenerateSimulationMakefile
(
Action
):
...
...
@@ -39,7 +40,7 @@ class GenerateSimulationMakefile(Action):
top_module
=
pool
.
get_top_module
()
flist
=
pool
.
build_global_file_list
()
flist_sorted
=
dep_solver
.
solve
(
flist
)
self
.
mak
e_writer
.
generate_vsim_makefile
(
flist_sorted
,
top_module
)
global_mod
.
makefil
e_writer
.
generate_vsim_makefile
(
flist_sorted
,
top_module
)
def
_generate_isim_makefile
(
self
):
# p.info("Generating makefile for simulation.")
...
...
@@ -54,7 +55,7 @@ class GenerateSimulationMakefile(Action):
flist
=
pool
.
build_global_file_list
()
flist_sorted
=
dep_solver
.
solve
(
flist
)
self
.
mak
e_writer
.
generate_isim_makefile
(
flist_sorted
,
top_module
)
global_mod
.
makefil
e_writer
.
generate_isim_makefile
(
flist_sorted
,
top_module
)
def
_generate_iverilog_makefile
(
self
):
if
self
.
env
[
"iverilog_path"
]
is
None
:
...
...
@@ -68,4 +69,4 @@ class GenerateSimulationMakefile(Action):
tm
=
pool
.
get_top_module
()
flist
=
pool
.
build_global_file_list
()
flist_sorted
=
dep_solver
.
solve
(
flist
)
self
.
mak
e_writer
.
generate_iverilog_makefile
(
flist_sorted
,
tm
,
pool
)
global_mod
.
makefil
e_writer
.
generate_iverilog_makefile
(
flist_sorted
,
tm
,
pool
)
hdlmake/global_mod.py
View file @
4ecc0baa
...
...
@@ -21,12 +21,15 @@
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
#
from
makefile_writer
import
MakefileWriter
options
=
None
top_module
=
None
global_target
=
"''"
mod_pool
=
None
sim_tool
=
None
env
=
None
makefile_writer
=
MakefileWriter
()
#######
#this var is modified by the build makefile - DON'T TOUCH IT!
BUILD_ID
=
"2013Feb22:341efe"
...
...
hdlmake/makefile_writer.py
View file @
4ecc0baa
...
...
@@ -27,6 +27,12 @@ import global_mod
from
string
import
Template
class
_Box
():
pass
_m
=
_Box
()
_m
.
initialized
=
False
class
MakefileWriter
(
object
):
def
__init__
(
self
,
filename
=
None
):
self
.
_file
=
None
...
...
@@ -34,26 +40,27 @@ class MakefileWriter(object):
self
.
_filename
=
filename
else
:
self
.
_filename
=
"Makefile"
self
.
_is_initialized
=
False
self
.
initialize
()
def
__del__
(
self
):
if
self
.
_is_initialized
:
self
.
_file
.
close
()
self
.
_file
.
close
()
def
initialize
(
self
):
if
not
self
.
_is_initialized
:
if
global_mod
.
options
.
append
is
True
:
self
.
_file
=
open
(
self
.
_filename
,
"a+"
)
else
:
self
.
_file
=
open
(
self
.
_filename
,
"w"
)
if
not
_m
.
initialized
:
if
os
.
path
.
exists
(
self
.
_filename
):
if
os
.
path
.
isfile
(
self
.
_filename
):
os
.
remove
(
self
.
_filename
)
elif
os
.
path
.
isdir
(
self
.
_filename
):
os
.
rmdir
(
self
.
_filename
)
self
.
_file
=
open
(
self
.
_filename
,
"a+"
)
if
not
_m
.
initialized
:
self
.
writeln
(
"########################################"
)
self
.
writeln
(
"# This file was generated by hdlmake #"
)
self
.
writeln
(
"# http://ohwr.org/projects/hdl-make/ #"
)
self
.
writeln
(
"########################################"
)
self
.
writeln
()
self
.
_is_initialized
=
True
else
:
pass
_m
.
initialized
=
True
def
write
(
self
,
line
=
None
):
self
.
_file
.
write
(
line
)
...
...
@@ -69,29 +76,34 @@ class MakefileWriter(object):
self
.
_file
=
open
(
filename
,
"w"
)
def
generate_remote_synthesis_makefile
(
self
,
files
,
name
,
cwd
,
user
,
server
):
from
subprocess
import
PIPE
,
Popen
if
name
is
None
:
import
random
name
=
''
.
join
(
random
.
choice
(
string
.
ascii_letters
+
string
.
digits
)
for
x
in
range
(
8
))
whoami
=
Popen
(
'whoami'
,
shell
=
True
,
stdin
=
PIPE
,
stdout
=
PIPE
,
close_fds
=
True
)
name
=
whoami
.
stdout
.
readlines
()[
0
]
.
strip
()
+
'/'
+
name
user_tmpl
=
"USER:={0}"
server_tmpl
=
"SERVER:={0}"
ise_path_tmpl
=
"ISE_PATH:={0}"
port_tmpl
=
"PORT:=22"
remote_name_tmpl
=
"R_NAME:={0}"
files_tmpl
=
"FILES := {0}"
if
user
is
None
:
user_tmpl
=
user_tmpl
.
format
(
"$(HDLMAKE_RSYNTH_USER)#take the value from the environment"
)
test_tmpl
=
"""__test_for_remote_synthesis_variables:
user_tmpl
=
user_tmpl
.
format
(
"$(HDLMAKE_RSYNTH_USER)#take the value from the environment"
)
test_tmpl
=
"""__test_for_remote_synthesis_variables:
ifeq (x$(USER),x)
\t
@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile." && false
\t
@echo "Remote synthesis user is not set.
You can set it by editing variable USER in the makefile or setting env. variable HDLMAKE_RSYNTH_USER." && false
endif
ifeq (x$(SERVER),x)
\t
@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile." && false
\t
@echo "Remote synthesis server is not set.
You can set it by editing variable SERVER in the makefile or setting env. variable HDLMAKE_RSYNTH_SERVER." && false
endif
ifeq (x$(ISE_PATH),x)
\t
@echo "Remote synthesis server is not set.
You can set it by editing variable ISE_PATH in the makefile or setting env. variable HDLMAKE_RSYNTH_ISE_PATH." && false
endif
"""
else
:
user_tmpl
=
user_tmpl
.
format
(
user
)
test_tmpl
=
"__test_for_remote_synthesis_variables:
\n\t\t
true #dummy
\n
"
if
server
is
None
:
server_tmpl
=
server_tmpl
.
format
(
"$(HDLMAKE_RSYNTH_SERVER)#take the value from the environment"
)
else
:
...
...
@@ -101,6 +113,7 @@ endif
self
.
initialize
()
self
.
writeln
(
user_tmpl
)
self
.
writeln
(
server_tmpl
)
self
.
writeln
(
ise_path_tmpl
.
format
(
"$(HDLMAKE_RSYNTH_ISE_PATH)"
))
self
.
writeln
(
remote_name_tmpl
)
self
.
writeln
(
port_tmpl
)
self
.
writeln
()
...
...
@@ -125,7 +138,7 @@ endif
tcl
=
"run.tcl"
synthesis_cmd
=
"""__do_synthesis:
ifeq (x$(HDLMAKE_RSYNTH_USE_SCREEN), x1)
\t\t
ssh $(USER)@$(SERVER) 'screen bash -c "cd $(R_NAME)$(CWD) && $(HDLMAKE_RSYNTH_ISE_PATH)/xtclsh {0}"'
\t\t
ssh
-t
$(USER)@$(SERVER) 'screen bash -c "cd $(R_NAME)$(CWD) && $(HDLMAKE_RSYNTH_ISE_PATH)/xtclsh {0}"'
else
\t\t
ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && $(HDLMAKE_RSYNTH_ISE_PATH)/xtclsh {0}'
endif
...
...
@@ -193,15 +206,15 @@ webtalk.log \
webtalk_pn.xml
\
run.tcl
syn_post_cmd: local
\t\t
${syn_post_cmd}
#target for performing local synthesis
local: syn_pre_cmd
\t\t
echo "project open $$(PROJECT)" > run.tcl
\t\t
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
\t\t
${ise_path}/xtclsh run.tcl
syn_post_cmd: local
\t\t
${syn_post_cmd}
syn_pre_cmd:
\t\t
${syn_pre_cmd}
...
...
@@ -266,14 +279,14 @@ mrproper:
self
.
write
(
"
\t\t
mkdir -p
%
s
\n
"
%
rp
(
module
.
fetchto
))
self
.
write
(
"
\t\t
"
)
self
.
write
(
"PWD=$(shell pwd) "
)
self
.
write
(
"cd "
+
rp
(
module
.
fetchto
)
+
'
;
'
)
self
.
write
(
"cd "
+
rp
(
module
.
fetchto
)
+
'
&&
'
)
self
.
write
(
"if [ -d "
+
basename
+
" ]; then cd "
+
basename
+
' && '
)
self
.
write
(
"git pull "
)
if
module
.
revision
:
self
.
write
(
" && git checkout "
+
module
.
revision
+
''
)
self
.
write
(
"else git clone "
+
module
.
url
+
'
; fi ;
'
)
self
.
write
(
" && git checkout "
+
module
.
revision
+
'
;
'
)
self
.
write
(
"else git clone "
+
module
.
url
+
'
&&
'
)
if
module
.
revision
:
self
.
write
(
"
\t\t
git checkout "
+
module
.
revision
)
self
.
write
(
"
cd "
+
basename
+
" && git checkout "
+
module
.
revision
+
'; fi; '
)
self
.
write
(
"cd $(PWD)
\n\n
"
)
def
generate_iverilog_makefile
(
self
,
fileset
,
top_module
,
modules_pool
):
...
...
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