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Projects
Hdlmake
Commits
4e3713cc
Commit
4e3713cc
authored
Aug 06, 2016
by
Javier D. Garcia-Lasheras
Browse files
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Massive code style refactoring and (yet) unused code purge
parent
39c8a38a
Hide whitespace changes
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Showing
22 changed files
with
130 additions
and
475 deletions
+130
-475
__main__.py
hdlmake/__main__.py
+0
-10
__init__.py
hdlmake/action/__init__.py
+0
-1
check.py
hdlmake/action/check.py
+0
-103
synthesis.py
hdlmake/action/synthesis.py
+0
-91
env.py
hdlmake/env.py
+0
-19
manifest_parser.py
hdlmake/manifest_parser.py
+0
-6
module_pool.py
hdlmake/module_pool.py
+2
-3
active_hdl.py
hdlmake/tools/active_hdl.py
+0
-4
diamond.py
hdlmake/tools/diamond.py
+0
-4
ghdl.py
hdlmake/tools/ghdl.py
+0
-4
ise.py
hdlmake/tools/ise.py
+0
-37
isim.py
hdlmake/tools/isim.py
+40
-66
iverilog.py
hdlmake/tools/iverilog.py
+0
-13
libero.py
hdlmake/tools/libero.py
+0
-4
modelsim.py
hdlmake/tools/modelsim.py
+0
-4
planahead.py
hdlmake/tools/planahead.py
+0
-4
quartus.py
hdlmake/tools/quartus.py
+33
-31
riviera.py
hdlmake/tools/riviera.py
+0
-3
sim_makefile_support.py
hdlmake/tools/sim_makefile_support.py
+31
-59
vivado.py
hdlmake/tools/vivado.py
+0
-4
xilinx.py
hdlmake/tools/xilinx.py
+0
-4
path.py
hdlmake/util/path.py
+24
-1
No files found.
hdlmake/__main__.py
View file @
4e3713cc
...
...
@@ -109,9 +109,6 @@ def _action_runner(modules_pool):
if
options
.
command
==
"check-env"
:
modules_pool
.
env
.
check_env
(
verbose
=
True
)
quit
()
elif
options
.
command
==
"check-manifest"
:
modules_pool
.
check_manifest
()
quit
()
elif
options
.
command
==
"manifest-help"
:
ManifestParser
()
.
print_help
()
quit
()
...
...
@@ -174,13 +171,6 @@ def _get_parser():
description
=
"Look for environmental variables specific for HDLMAKE.
\n
"
"Hdlmake will examine presence of supported synthesis and simulation"
"tools.
\n
"
)
check_manifest
=
subparsers
.
add_parser
(
"check-manifest"
,
help
=
"check manifest for formal correctness"
)
check_manifest
.
add_argument
(
"--top"
,
help
=
"indicate path to the top manifest"
,
default
=
None
)
manifest_help
=
subparsers
.
add_parser
(
"manifest-help"
,
help
=
"print manifest file variables description"
)
...
...
hdlmake/action/__init__.py
View file @
4e3713cc
...
...
@@ -24,7 +24,6 @@
from
.action
import
Action
from
.check
import
ActionCheck
from
.core
import
ActionCore
from
.tree
import
ActionTree
...
...
hdlmake/action/check.py
deleted
100644 → 0
View file @
39c8a38a
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
#
# This file is part of Hdlmake.
#
# Hdlmake is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# Hdlmake is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
"""Module providing generic checking actions. This needs to be implemented"""
from
__future__
import
print_function
import
logging
import
sys
import
re
from
.action
import
Action
class
ActionCheck
(
Action
):
"""Class providing the method to check general properties"""
def
__init__
(
self
,
*
args
):
super
(
ActionCheck
,
self
)
.
__init__
(
*
args
)
def
check_manifest
(
self
):
"""Method that checks the manifest dict"""
logging
.
warning
(
"Problems with top_module at
%
s"
,
self
.
top_module
.
path
)
logging
.
error
(
"This action is not implemented yet!"
)
quit
()
def
check_condition
(
self
):
"""Method that checks if a supplied condition is OK"""
logging
.
error
(
"This action is not implemented yet!"
)
quit
()
def
_compare
(
local
,
reference
,
cond
):
"""Function that provides the actual condition line"""
if
cond
==
"=="
:
return
local
==
reference
elif
cond
==
"<"
:
return
local
<
reference
elif
cond
==
">"
:
return
local
>
reference
elif
cond
==
"<="
:
return
local
<=
reference
elif
cond
==
">="
:
return
local
>=
reference
else
:
sys
.
exit
(
1
)
tool
=
self
.
env
.
options
.
tool
if
tool
==
"ise"
:
ver
=
self
.
env
[
"ise_version"
]
if
not
ver
:
sys
.
exit
(
1
)
ref
=
self
.
env
.
options
.
reference
ver
=
float
(
ver
)
ref
=
float
(
ref
)
elif
tool
==
"quartus"
:
ver
=
self
.
env
[
"quartus_version"
]
if
not
ver
:
sys
.
exit
(
1
)
ref
=
self
.
env
.
options
.
reference
elif
tool
==
"modelsim"
:
ver
=
self
.
env
[
"modelsim_version"
]
if
not
ver
:
sys
.
exit
(
1
)
ref
=
self
.
env
.
options
.
reference
elif
tool
==
"iverilog"
:
ver
=
self
.
env
[
"iverilog_version"
]
if
not
ver
:
sys
.
exit
(
1
)
ref
=
self
.
env
.
options
.
reference
ver
=
int
(
ver
.
replace
(
'.'
,
''
))
ref
=
int
(
ref
.
replace
(
'.'
,
''
))
elif
tool
==
"isim"
:
ver
=
self
.
env
[
"ise_version"
]
if
not
ver
:
sys
.
exit
(
1
)
ref
=
self
.
env
.
options
.
reference
ver
=
re
.
sub
(
"[a-zA-Z]"
,
''
,
ver
)
ref
=
re
.
sub
(
"[a-zA-Z]"
,
''
,
ref
)
else
:
logging
.
error
(
"Unknown tool:
%
s"
,
tool
)
sys
.
exit
(
"
\n
Exiting"
)
comparison
=
_compare
(
ver
,
ref
,
self
.
env
.
options
.
condition
)
sys
.
exit
(
int
(
not
comparison
))
hdlmake/action/synthesis.py
View file @
4e3713cc
...
...
@@ -26,9 +26,6 @@ from __future__ import print_function
import
logging
import
sys
from
hdlmake.srcfile
import
SourceFileFactory
from
hdlmake.util
import
path
from
hdlmake.tools
import
(
ToolISE
,
ToolPlanAhead
,
ToolVivado
,
ToolQuartus
,
ToolDiamond
,
ToolLibero
)
...
...
@@ -61,74 +58,6 @@ class ActionSynthesis(ToolISE, ToolPlanAhead, ToolVivado,
logging
.
error
(
"Synthesis tool not recognized:
%
s"
,
tool_name
)
return
tool_object
def
_write_project_vhd
(
self
,
tool
,
version
):
"""Create a VHDL file containing a SDB compatible design description"""
from
string
import
Template
from
datetime
import
date
import
getpass
today
=
date
.
today
()
date_string
=
today
.
strftime
(
"
%
Y
%
m
%
d"
)
template
=
Template
(
"""library ieee;
use work.wishbone_pkg.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package sdb_meta_pkg is
------------------------------------------------------------------------------
-- Meta-information sdb records
------------------------------------------------------------------------------
-- Top module repository url
constant c_SDB_REPO_URL : t_sdb_repo_url := (
-- url (string, 63 char)
repo_url => "$repo_url");
-- Synthesis informations
constant c_SDB_SYNTHESIS : t_sdb_synthesis := (
-- Top module name (string, 16 char)
syn_module_name => "$syn_module_name",
-- Commit ID (hex string, 128-bit = 32 char)
-- git log -1 --format="
%
H" | cut -c1-32
syn_commit_id => "$syn_commit_id",
-- Synthesis tool name (string, 8 char)
syn_tool_name => "$syn_tool_name",
-- Synthesis tool version (bcd encoded, 32-bit)
syn_tool_version => "$syn_tool_version", -- $syn_tool_version_str
-- Synthesis date (bcd encoded, 32-bit)
syn_date => "$syn_date", -- $syn_date_str
-- Synthesised by (string, 15 char)
syn_username => "$syn_username");
end sdb_meta_pkg;
package body sdb_meta_pkg is
end sdb_meta_pkg;"""
)
project_vhd
=
open
(
"project.vhd"
,
'w'
)
date_std_logic_vector
=
[]
import
re
for
digit
in
date_string
:
date_std_logic_vector
.
append
(
"{0:04b}"
.
format
(
int
(
digit
)))
syn_tool_version
=
version
syn_tool_version
=
re
.
sub
(
r"\D"
,
""
,
syn_tool_version
)
syn_tool_std_logic_vector
=
[]
for
digit
in
syn_tool_version
:
syn_tool_std_logic_vector
.
append
(
"{0:04b}"
.
format
(
int
(
digit
)))
template
.
substitute
(
repo_url
=
self
.
top_module
.
url
,
syn_module_name
=
self
.
top_module
.
manifest_dict
[
"syn_top"
],
syn_commit_id
=
self
.
top_module
.
revision
,
syn_tool_name
=
tool
.
upper
(),
syn_tool_version
=
"0000"
*
(
8
-
len
(
syn_tool_std_logic_vector
))
+
''
.
join
(
syn_tool_std_logic_vector
),
syn_tool_version_str
=
syn_tool_version
,
syn_date
=
''
.
join
(
date_std_logic_vector
),
syn_date_str
=
date_string
,
syn_username
=
getpass
.
getuser
())
project_vhd
.
write
(
template
)
project_vhd
.
close
()
def
_check_synthesis_project
(
self
):
"""Check the manifest contains all the keys for a synthesis project"""
manifest
=
self
.
get_top_module
()
.
manifest_dict
...
...
@@ -157,13 +86,10 @@ end sdb_meta_pkg;""")
"""Generate a project for the specific synthesis tool"""
self
.
_check_all_fetched_or_quit
()
self
.
_check_synthesis_project
()
tool_object
=
self
.
_load_synthesis_tool
()
tool_info
=
tool_object
.
TOOL_INFO
path_key
=
tool_info
[
'id'
]
+
'_path'
version_key
=
tool_info
[
'id'
]
+
'_version'
name
=
tool_info
[
'name'
]
id_value
=
tool_info
[
'id'
]
env
=
self
.
env
env
.
check_general
()
env
.
check_tool
(
tool_object
)
...
...
@@ -172,18 +98,6 @@ end sdb_meta_pkg;""")
tool_path
=
env
[
path_key
]
else
:
tool_path
=
""
if
not
self
.
env
.
options
.
force
:
if
self
.
env
[
path_key
]
is
None
:
logging
.
error
(
"Can't generate the "
+
name
+
" project. "
+
name
+
" not found."
)
quit
()
if
version_key
not
in
env
or
not
env
[
version_key
]:
logging
.
error
(
name
+
" version cannot be deduced. Cannot generate "
+
name
+
" project file properly. Please use syn_"
+
id_value
+
"_version in the manifest or set"
)
sys
.
exit
(
"Exiting"
)
logging
.
info
(
"Generating project for "
+
name
+
" v.
%
s"
,
env
[
version_key
])
top_mod
=
self
.
get_top_module
()
fileset
=
self
.
build_file_set
(
top_mod
.
manifest_dict
[
"syn_top"
])
sup_files
=
self
.
build_complete_file_set
()
...
...
@@ -196,11 +110,6 @@ end sdb_meta_pkg;""")
logging
.
info
(
"Detected
%
d supported files that are not parseable"
,
len
(
privative_files
))
fileset
.
add
(
privative_files
)
sff
=
SourceFileFactory
()
if
self
.
env
.
options
.
generate_project_vhd
:
self
.
_write_project_vhd
(
id_value
,
env
[
version_key
])
fileset
.
add
([
sff
.
new
(
path
=
path
.
rel2abs
(
"project.vhd"
),
module
=
self
.
get_module_by_path
(
"."
))])
tool_object
.
makefile_includes
(
top_module
)
tool_object
.
makefile_syn_top
(
top_module
,
tool_path
)
tool_object
.
makefile_syn_tcl
(
top_module
)
...
...
hdlmake/env.py
View file @
4e3713cc
...
...
@@ -131,7 +131,6 @@ class Env(dict):
bin_name
=
tool_info
[
'linux_bin'
]
path_key
=
tool_info
[
'id'
]
+
'_path'
version_key
=
tool_info
[
'id'
]
+
'_version'
name
=
tool_info
[
'name'
]
print
(
"
\n
### "
+
name
+
" tool environment information ###"
)
...
...
@@ -153,9 +152,6 @@ class Env(dict):
self
[
path_key
])
else
:
print
(
name
+
" "
+
_red
(
"cannnot"
)
+
" be found."
)
if
self
[
path_key
]
is
not
None
:
self
[
version_key
]
=
info_class
.
detect_version
(
self
[
path_key
])
print
(
"Detected "
+
name
+
" version
%
s"
%
self
[
version_key
])
def
_report_and_set_hdlmake_var
(
self
,
name
):
name
=
name
.
upper
()
...
...
@@ -173,21 +169,6 @@ class Env(dict):
self
[
name
.
lower
()]
=
None
return
False
# TODO: TRANSFORM THIS INTO A GENERAL VERSION FORCE/CHECK MECHANISM OR SUPRESS???
# def check_env_wrt_manifest(self, verbose=False):
# determine ISE version
# if self.top_module:
# if self.top_module.syn_ise_version is not None:
# ise_version = self.top_module.syn_ise_version
# print("ise_version set in the manifest: %s" % ise_version)
# self["ise_version"] = ise_version
# elif self["ise_version"] is not None:
# iv = self["ise_version"]
# print("syn_ise_version not set in the manifest,"
# " guessed ISE version: %s.%s." % (iv[0], iv[1]))
if
__name__
==
"__main__"
:
ec
=
Env
({},
{})
ec
.
check
()
hdlmake/manifest_parser.py
View file @
4e3713cc
...
...
@@ -108,12 +108,6 @@ class ManifestParser(ConfigParser):
default
=
None
,
help
=
"Project file (.xise, .ise, .qpf)"
,
type
=
''
)
self
.
add_option
(
'syn_ise_version'
,
default
=
None
,
help
=
"Force particular ISE version"
,
type
=
float
)
self
.
add_type
(
'syn_ise_version'
,
type
=
''
)
self
.
add_option
(
'syn_pre_cmd'
,
default
=
''
,
...
...
hdlmake/module_pool.py
View file @
4e3713cc
...
...
@@ -23,13 +23,13 @@
"""This is the Python module providing the container for the HDL Modules"""
from
.action
import
(
ActionC
heck
,
ActionC
ore
,
from
.action
import
(
ActionCore
,
ActionTree
,
ActionSimulation
,
ActionSynthesis
,
QsysHwTclUpdate
)
class
ModulePool
(
ActionC
heck
,
ActionC
ore
,
class
ModulePool
(
ActionCore
,
ActionTree
,
ActionSimulation
,
ActionSynthesis
,
QsysHwTclUpdate
):
...
...
@@ -40,7 +40,6 @@ class ModulePool(ActionCheck, ActionCore,
"""
def
__init__
(
self
,
*
args
):
ActionCheck
.
__init__
(
self
,
*
args
)
ActionCore
.
__init__
(
self
,
*
args
)
ActionTree
.
__init__
(
self
,
*
args
)
ActionSimulation
.
__init__
(
self
,
*
args
)
...
...
hdlmake/tools/active_hdl.py
View file @
4e3713cc
...
...
@@ -48,10 +48,6 @@ class ToolActiveHDL(ToolSim):
self
.
_hdl_files
.
extend
(
ToolActiveHDL
.
HDL_FILES
)
self
.
_clean_targets
.
update
(
ToolActiveHDL
.
CLEAN_TARGETS
)
def
detect_version
(
self
,
path
):
"""Get the version from the Aldec-HDL binary program"""
pass
def
makefile_sim_compilation
(
self
,
fileset
,
top_module
):
"""Print Makefile compilation target for Aldec Active-HDL simulator"""
self
.
writeln
(
"simulation:"
)
...
...
hdlmake/tools/diamond.py
View file @
4e3713cc
...
...
@@ -70,10 +70,6 @@ class ToolDiamond(ToolSyn):
self
.
_clean_targets
.
update
(
ToolDiamond
.
CLEAN_TARGETS
)
self
.
_tcl_controls
.
update
(
ToolDiamond
.
TCL_CONTROLS
)
def
detect_version
(
self
,
path
):
"""Get version from the Lattice Diamond program"""
return
'unknown'
def
makefile_syn_tcl
(
self
,
top_module
):
"""Create a Diamond synthesis project by TCL"""
syn_device
=
top_module
.
manifest_dict
[
"syn_device"
]
...
...
hdlmake/tools/ghdl.py
View file @
4e3713cc
...
...
@@ -52,10 +52,6 @@ class ToolGHDL(ToolSim):
self
.
_hdl_files
.
extend
(
ToolGHDL
.
HDL_FILES
)
self
.
_clean_targets
.
update
(
ToolGHDL
.
CLEAN_TARGETS
)
def
detect_version
(
self
,
path
):
"""Get tool version for GHDL"""
pass
def
makefile_sim_options
(
self
,
top_module
):
"""Print the GHDL options to the Makefile"""
if
top_module
.
manifest_dict
[
"ghdl_opt"
]:
...
...
hdlmake/tools/ise.py
View file @
4e3713cc
...
...
@@ -24,20 +24,13 @@
"""Module providing the classes that are used to handle Xilinx ISE"""
from
__future__
import
print_function
import
xml.dom.minidom
import
xml.parsers.expat
import
logging
import
re
from
subprocess
import
Popen
,
PIPE
from
.make_syn
import
ToolSyn
from
hdlmake.util
import
path
as
path_mod
from
hdlmake.srcfile
import
(
VHDLFile
,
VerilogFile
,
SVFile
,
UCFFile
,
CDCFile
,
NGCFile
)
XML_IMPL
=
xml
.
dom
.
minidom
.
getDOMImplementation
()
FAMILY_NAMES
=
{
"XC6S"
:
"Spartan6"
,
"XC3S"
:
"Spartan3"
,
...
...
@@ -106,36 +99,6 @@ class ToolISE(ToolSyn):
self
.
_clean_targets
.
update
(
ToolISE
.
CLEAN_TARGETS
)
self
.
_tcl_controls
.
update
(
ToolISE
.
TCL_CONTROLS
)
def
detect_version
(
self
,
path
):
"""Method returning a string with the Xilinx ISE version from path"""
is_windows
=
path_mod
.
check_windows
()
version_pattern
=
re
.
compile
(
r'.*?(?P<major>\d|\d\d)[^\d](?P<minor>\d|\d\d).*'
)
# First check if we have version in path
match
=
re
.
match
(
version_pattern
,
path
)
if
match
:
ise_version
=
"
%
s.
%
s"
%
(
match
.
group
(
'major'
),
match
.
group
(
'minor'
))
else
:
# If it is not the case call the "xst -h" to get version
xst_output
=
Popen
(
'xst -h'
,
shell
=
True
,
stdin
=
PIPE
,
stdout
=
PIPE
,
close_fds
=
not
is_windows
)
xst_output
=
xst_output
.
stdout
.
readlines
()[
0
]
xst_output
=
xst_output
.
strip
()
version_pattern
=
re
.
compile
(
r'Release\s(?P<major>\d|\d\d)[^\d](?P<minor>\d|\d\d)\s.*'
)
match
=
re
.
match
(
version_pattern
,
xst_output
)
if
match
:
ise_version
=
"
%
s.
%
s"
%
(
match
.
group
(
'major'
),
match
.
group
(
'minor'
))
else
:
logging
.
error
(
"xst output is not in expected format:
%
s
\n
"
,
xst_output
+
"Can't determine ISE version"
)
return
None
return
ise_version
def
makefile_syn_tcl
(
self
,
top_module
):
"""Create a Xilinx synthesis project by TCL"""
tmp
=
"{0}set {1} {2}"
...
...
hdlmake/tools/isim.py
View file @
4e3713cc
...
...
@@ -27,11 +27,9 @@
import
os
import
os.path
from
subprocess
import
Popen
,
PIPE
import
logging
import
sys
from
hdlmake.util
import
path
as
path_mod
from
.make_sim
import
ToolSim
from
hdlmake.srcfile
import
VerilogFile
,
VHDLFile
...
...
@@ -67,40 +65,62 @@ class ToolISim(ToolSim):
self
.
_hdl_files
.
extend
(
ToolISim
.
HDL_FILES
)
self
.
_clean_targets
.
update
(
ToolISim
.
CLEAN_TARGETS
)
def
detect_version
(
self
,
path
):
"""Get version from Xilinx ISim simulator program"""
is_windows
=
path_mod
.
check_windows
()
isim
=
Popen
(
"
%
s --version | awk '{print $2}'"
%
os
.
path
.
join
(
path
,
"vlogcomp"
),
shell
=
True
,
close_fds
=
not
is_windows
,
stdin
=
PIPE
,
stdout
=
PIPE
)
print
os
.
path
.
join
(
path
,
"vlogcomp"
)
try
:
isim_version
=
isim
.
stdout
.
readlines
()[
0
]
.
strip
()
except
:
return
None
return
isim_version
def
makefile_sim_top
(
self
,
top_module
):
"""Print the top section of the Makefile for Xilinx ISim"""
def
__get_xilinxsim_ini_dir
(
env
):
"""Get Xilinx ISim ini simulation file"""
if
env
[
"isim_path"
]:
xilinx_dir
=
str
(
os
.
path
.
join
(
env
[
"isim_path"
],
".."
,
".."
))
else
:
logging
.
error
(
"Cannot calculate xilinx tools base directory"
)
quit
()
hdl_language
=
'vhdl'
# 'verilog'
if
sys
.
platform
==
'cygwin'
:
os_prefix
=
'nt'
else
:
os_prefix
=
'lin'
if
env
[
"architecture"
]
==
32
:
arch_sufix
=
''
else
:
arch_sufix
=
'64'
xilinx_ini_path
=
str
(
os
.
path
.
join
(
xilinx_dir
,
hdl_language
,
"hdp"
,
os_prefix
+
arch_sufix
))
# Ensure the path is absolute and normalized
return
os
.
path
.
abspath
(
xilinx_ini_path
)
self
.
writeln
(
"""## variables #############################
PWD := $(shell pwd)
TOP_MODULE := """
+
top_module
.
manifest_dict
[
"sim_top"
]
+
"""
FUSE_OUTPUT ?= isim_proj
XILINX_INI_PATH := """
+
self
.
__get_xilinxsim_ini_dir
(
top_module
.
pool
.
env
)
+
XILINX_INI_PATH := """
+
__get_xilinxsim_ini_dir
(
top_module
.
pool
.
env
)
+
"""
"""
)
def
makefile_sim_options
(
self
,
top_module
):
"""Print the Xilinx ISim simulation options in the Makefile"""
def
__get_rid_of_isim_incdirs
(
vlog_opt
):
"""Clean the vlog options from include dirs"""
if
not
vlog_opt
:
vlog_opt
=
""
vlogs
=
vlog_opt
.
split
(
' '
)
ret
=
[]
skip
=
False
for
vlog_option
in
vlogs
:
if
skip
:
skip
=
False
continue
if
not
vlog_option
.
startswith
(
"-i"
):
ret
.
append
(
vlog_option
)
else
:
skip
=
True
return
' '
.
join
(
ret
)
self
.
writeln
(
"""VHPCOMP_FLAGS := -intstyle default
\
-incremental -initfile xilinxsim.ini
ISIM_FLAGS :=
VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini """
+
self
.
__get_rid_of_isim_incdirs
(
__get_rid_of_isim_incdirs
(
top_module
.
manifest_dict
[
"vlog_opt"
])
+
"""
"""
)
...
...
@@ -117,9 +137,7 @@ fuse:
\t\t
fuse work.$(TOP_MODULE) -intstyle ise -incremental -o $(FUSE_OUTPUT)
"""
libs
=
set
(
f
.
library
for
f
in
fileset
)
self
.
write
(
'LIBS := '
)
self
.
write
(
' '
.
join
(
libs
))
self
.
write
(
'
\n
'
)
...
...
@@ -127,9 +145,7 @@ fuse:
self
.
write
(
'LIB_IND := '
)
self
.
write
(
' '
.
join
([
lib
+
"/."
+
lib
for
lib
in
libs
]))
self
.
write
(
'
\n
'
)
self
.
writeln
(
make_preambule_p2
)
# ISim does not have a vmap command to insert additional libraries in
#.ini file.
for
lib
in
libs
:
...
...
@@ -147,11 +163,9 @@ fuse:
"xilinxsim.ini) "
]))
self
.
write
(
' '
.
join
([
"||"
,
"rm -rf"
,
lib
,
"
\n
"
]))
self
.
write
(
'
\n
'
)
# Modify xilinxsim.ini file by including the extra local libraries
# self.write(' '.join(["\t(echo """, lib+"="+lib+"/."+lib, ">>",
# "${XILINX_INI_PATH}/xilinxsim.ini"]))
# rules for all _primary.dat files for sv
# incdir = ""
objs
=
[]
...
...
@@ -189,7 +203,6 @@ fuse:
self
.
write
(
"
\t\t
@mkdir -p $(dir $@)"
)
self
.
writeln
(
" && touch $@
\n\n
"
)
self
.
write
(
"
\n
"
)
# list rules for all _primary.dat files for vhdl
for
vhdl_file
in
fileset
.
filter
(
VHDLFile
):
lib
=
vhdl_file
.
library
...
...
@@ -240,42 +253,3 @@ fuse:
self
.
write
(
'
\n
'
)
self
.
writeln
(
"
\t\t
@mkdir -p $(dir $@) && touch $@
\n
"
)
def
__get_rid_of_isim_incdirs
(
self
,
vlog_opt
):
"""Clean the vlog options from include dirs"""
if
not
vlog_opt
:
vlog_opt
=
""
vlogs
=
vlog_opt
.
split
(
' '
)
ret
=
[]
skip
=
False
for
vlog_option
in
vlogs
:
if
skip
:
skip
=
False
continue
if
not
vlog_option
.
startswith
(
"-i"
):
ret
.
append
(
vlog_option
)
else
:
skip
=
True
return
' '
.
join
(
ret
)
def
__get_xilinxsim_ini_dir
(
self
,
env
):
"""Get Xilinx ISim ini simulation file"""
if
env
[
"isim_path"
]:
xilinx_dir
=
str
(
os
.
path
.
join
(
env
[
"isim_path"
],
".."
,
".."
))
else
:
logging
.
error
(
"Cannot calculate xilinx tools base directory"
)
quit
()
hdl_language
=
'vhdl'
# 'verilog'
if
sys
.
platform
==
'cygwin'
:
os_prefix
=
'nt'
else
:
os_prefix
=
'lin'
if
env
[
"architecture"
]
==
32
:
arch_sufix
=
''
else
:
arch_sufix
=
'64'
xilinx_ini_path
=
str
(
os
.
path
.
join
(
xilinx_dir
,
hdl_language
,
"hdp"
,
os_prefix
+
arch_sufix
))
# Ensure the path is absolute and normalized
return
os
.
path
.
abspath
(
xilinx_ini_path
)
hdlmake/tools/iverilog.py
View file @
4e3713cc
...
...
@@ -23,10 +23,8 @@
"""Module providing support for IVerilog (Icarus Verilog) simulator"""
from
subprocess
import
Popen
,
PIPE
import
string
from
hdlmake.util
import
path
as
path_mod
from
.make_sim
import
ToolSim
from
hdlmake.srcfile
import
VerilogFile
,
VHDLFile
,
SVFile
...
...
@@ -59,17 +57,6 @@ class ToolIVerilog(ToolSim):
self
.
_hdl_files
.
extend
(
ToolIVerilog
.
HDL_FILES
)
self
.
_clean_targets
.
update
(
ToolIVerilog
.
CLEAN_TARGETS
)
def
detect_version
(
self
,
path
):
"""Get version from Icarus Verilog program"""
is_windows
=
path_mod
.
check_windows
()
iverilog
=
Popen
(
"iverilog -v 2>/dev/null| awk '{if(NR==1) print $4}'"
,
shell
=
True
,
stdin
=
PIPE
,
stdout
=
PIPE
,
close_fds
=
not
is_windows
)
version
=
iverilog
.
stdout
.
readlines
()[
0
]
.
strip
()
return
version
def
makefile_sim_compilation
(
self
,
fileset
,
top_module
):
"""Generate compile simulation Makefile target for IVerilog"""
...
...
hdlmake/tools/libero.py
View file @
4e3713cc
...
...
@@ -72,10 +72,6 @@ class ToolLibero(ToolSyn):
self
.
_clean_targets
.
update
(
ToolLibero
.
CLEAN_TARGETS
)
self
.
_tcl_controls
.
update
(
ToolLibero
.
TCL_CONTROLS
)
def
detect_version
(
self
,
path
):
"""Get version for Microsemi Libero IDE synthesis"""
return
'unknown'
def
makefile_syn_tcl
(
self
,
top_module
):
"""Create a Libero synthesis project by TCL"""
syn_project
=
top_module
.
manifest_dict
[
"syn_project"
]
...
...
hdlmake/tools/modelsim.py
View file @
4e3713cc
...
...
@@ -55,10 +55,6 @@ class ToolModelsim(VsimMakefileWriter):
self
.
_tool_info
.
update
(
ToolModelsim
.
TOOL_INFO
)
self
.
_clean_targets
.
update
(
ToolModelsim
.
CLEAN_TARGETS
)
def
detect_version
(
self
,
path
):
"""Get version from the Mentor Modelsim program"""
pass
def
makefile_sim_options
(
self
,
top_module
):
"""Print the Modelsim options to the Makefile"""
if
top_module
.
pool
.
env
[
"modelsim_path"
]:
...
...
hdlmake/tools/planahead.py
View file @
4e3713cc
...
...
@@ -57,7 +57,3 @@ class ToolPlanAhead(ToolXilinx):
self
.
_clean_targets
.
update
(
ToolPlanAhead
.
CLEAN_TARGETS
)
self
.
_tcl_controls
.
update
(
ToolPlanAhead
.
TCL_CONTROLS
)
def
detect_version
(
self
,
path
):
"""Get the Xilinx PlanAhead program version"""
return
'unknown'
hdlmake/tools/quartus.py
View file @
4e3713cc
...
...
@@ -91,10 +91,6 @@ class ToolQuartus(ToolSyn):
self
.
_clean_targets
.
update
(
ToolQuartus
.
CLEAN_TARGETS
)
self
.
_tcl_controls
.
update
(
ToolQuartus
.
TCL_CONTROLS
)
def
detect_version
(
self
,
path
):
"""Get Altera Quartus version from the binary program"""
return
'unknown'
def
makefile_syn_tcl
(
self
,
top_module
):
"""Add initial properties to the Altera Quartus project"""
import
re
...
...
@@ -120,41 +116,47 @@ class ToolQuartus(ToolSyn):
words
.
append
(
"-section_id"
)
words
.
append
(
section_id
)
return
' '
.
join
(
words
)
family_names
=
{
"^EP2AGX.*$"
:
"Arria II GX"
,
"^EP3C.*$"
:
"Cyclone III"
,
"^EP4CE.*$"
:
"Cyclone IV E"
,
"^EP4CGX.*$"
:
"Cyclone IV GX"
,
"^5S.*$"
:
"Stratix V"
,
}
syn_device
=
top_module
.
manifest_dict
[
"syn_device"
]
syn_family
=
top_module
.
manifest_dict
[
"syn_family"
]
syn_grade
=
top_module
.
manifest_dict
[
"syn_grade"
]
syn_package
=
top_module
.
manifest_dict
[
"syn_package"
]
syn_top
=
top_module
.
manifest_dict
[
"syn_top"
]
if
syn_family
is
None
:
for
key
in
family_names
:
if
re
.
match
(
key
,
syn_device
.
upper
()):
syn_family
=
family_names
[
key
]
logging
.
debug
(
"Auto-guessed syn_family to be
%
s (
%
s =>
%
s)"
,
syn_family
,
syn_device
,
key
)
if
syn_family
is
None
:
logging
.
error
(
"Could not auto-guess device family, please "
"specify in Manifest.py using syn_family!"
)
sys
.
exit
(
"
\n
Exiting"
)
devstring
=
(
syn_device
+
syn_package
+
syn_grade
)
.
upper
()
def
__get_family_string
(
family
=
None
,
device
=
None
):
"""Function that looks for a existing device family name and
try to guess the value from the device string if not defined"""
family_names
=
{
"^EP2AGX.*$"
:
"Arria II GX"
,
"^EP3C.*$"
:
"Cyclone III"
,
"^EP4CE.*$"
:
"Cyclone IV E"
,
"^EP4CGX.*$"
:
"Cyclone IV GX"
,
"^5S.*$"
:
"Stratix V"
}
if
family
is
None
:
for
key
in
family_names
:
if
re
.
match
(
key
,
device
.
upper
()):
family
=
family_names
[
key
]
logging
.
debug
(
"Auto-guessed syn_family to be
%
s (
%
s =>
%
s)"
,
family
,
device
,
key
)
if
family
is
None
:
logging
.
error
(
"Could not auto-guess device family, please "
"specify in Manifest.py using syn_family!"
)
sys
.
exit
(
"
\n
Exiting"
)
return
family
# Set the core Quartus project properties
family_string
=
__get_family_string
(
family
=
top_module
.
manifest_dict
[
"syn_family"
],
device
=
top_module
.
manifest_dict
[
"syn_device"
])
device_string
=
(
top_module
.
manifest_dict
[
"syn_device"
]
+
top_module
.
manifest_dict
[
"syn_package"
]
+
top_module
.
manifest_dict
[
"syn_grade"
])
.
upper
()
command_list
=
[]
command_list
.
append
(
self
.
_tcl_controls
[
"create"
])
command_list
.
append
(
_emit_property
(
self
.
SET_GLOBAL_ASSIGNMENT
,
name_type
=
'FAMILY'
,
name
=
'"'
+
syn_family
+
'"'
))
name
=
'"'
+
family_string
+
'"'
))
command_list
.
append
(
_emit_property
(
self
.
SET_GLOBAL_ASSIGNMENT
,
name_type
=
'DEVICE'
,
name
=
devstring
))
name
=
dev
ice_
string
))
command_list
.
append
(
_emit_property
(
self
.
SET_GLOBAL_ASSIGNMENT
,
name_type
=
'TOP_LEVEL_ENTITY'
,
name
=
syn_top
))
name
=
top_module
.
manifest_dict
[
"syn_top"
]))
# Insert the Quartus standard control TCL files
if
top_module
.
manifest_dict
[
"quartus_preflow"
]
is
not
None
:
path
=
path_mod
.
compose
(
top_module
.
manifest_dict
[
"quartus_preflow"
],
top_module
.
path
)
...
...
hdlmake/tools/riviera.py
View file @
4e3713cc
...
...
@@ -81,6 +81,3 @@ class ToolRiviera(VsimMakefileWriter):
self
.
_tool_info
.
update
(
ToolRiviera
.
TOOL_INFO
)
self
.
_clean_targets
.
update
(
ToolRiviera
.
CLEAN_TARGETS
)
def
detect_version
(
self
,
path
):
"""Get version from Aldec Riviera-PRO binary program"""
pass
hdlmake/tools/sim_makefile_support.py
View file @
4e3713cc
...
...
@@ -24,10 +24,10 @@
"""Module providing common stuff for Modelsim, Vsim... like simulators"""
import
os
import
platform
import
string
from
.make_sim
import
ToolSim
from
hdlmake.util
import
path
as
path_mod
from
hdlmake.srcfile
import
VerilogFile
,
VHDLFile
,
SVFile
...
...
@@ -59,20 +59,26 @@ class VsimMakefileWriter(ToolSim):
self
.
copy_rules
=
{}
self
.
_hdl_files
.
extend
(
VsimMakefileWriter
.
HDL_FILES
)
def
makefile_sim_options
(
self
,
top_module
):
"""Print the vsim options to the Makefile"""
self
.
vlog_flags
.
append
(
self
.
__get_rid_of_vsim_incdirs
(
top_module
.
manifest_dict
[
"vlog_opt"
]))
def
__get_rid_of_vsim_incdirs
(
vlog_opt
=
""
):
"""Parse the VLOG options and purge the included dirs"""
if
not
vlog_opt
:
vlog_opt
=
""
vlogs
=
vlog_opt
.
split
(
' '
)
ret
=
[]
for
vlog_aux
in
vlogs
:
if
not
vlog_aux
.
startswith
(
"+incdir+"
):
ret
.
append
(
vlog_aux
)
return
' '
.
join
(
ret
)
self
.
vlog_flags
.
append
(
__get_rid_of_vsim_incdirs
(
top_module
.
manifest_dict
[
"vlog_opt"
]))
self
.
vcom_flags
.
append
(
top_module
.
manifest_dict
[
"vcom_opt"
])
self
.
vmap_flags
.
append
(
top_module
.
manifest_dict
[
"vmap_opt"
])
self
.
vsim_flags
.
append
(
top_module
.
manifest_dict
[
"vsim_opt"
])
for
var
,
value
in
self
.
custom_variables
.
iteritems
():
self
.
writeln
(
"
%
s :=
%
s"
%
(
var
,
value
))
self
.
writeln
()
self
.
writeln
(
"VCOM_FLAGS :=
%
s"
%
(
' '
.
join
(
self
.
vcom_flags
)))
self
.
writeln
(
"VSIM_FLAGS :=
%
s"
%
(
' '
.
join
(
self
.
vsim_flags
)))
self
.
writeln
(
"VLOG_FLAGS :=
%
s"
%
(
' '
.
join
(
self
.
vlog_flags
)))
...
...
@@ -83,29 +89,24 @@ class VsimMakefileWriter(ToolSim):
The Makefile format is shared, but flags, dependencies, clean rules,
etc are defined by the specific tool.
"""
if
platform
.
system
()
==
'Windows'
:
del_command
=
"rm -rf"
mkdir_command
=
"mkdir"
slash_char
=
"
\\
"
else
:
del_command
=
"rm -rf"
mkdir_command
=
"mkdir -p"
slash_char
=
"/"
# self.writeln("INCLUDE_DIRS := +incdir+%s" %
# ('+'.join(top_module.include_dirs)))
def
__create_copy_rule
(
name
,
src
):
"""Get a Makefile rule named name, which depends on src,
copying it to the local directory."""
rule
=
"""
%
s:
%
s
\t\t
%
s $< . 2>&1
"""
%
(
name
,
src
,
path_mod
.
copy_command
())
return
rule
#self.writeln("INCLUDE_DIRS := +incdir+%s" %
# ('+'.join(top_module.include_dirs)))
libs
=
set
(
f
.
library
for
f
in
fileset
)
self
.
write
(
'LIBS := '
)
self
.
write
(
' '
.
join
(
libs
))
self
.
write
(
'
\n
'
)
# tell how to make libraries
self
.
write
(
'LIB_IND := '
)
self
.
write
(
' '
.
join
([
lib
+
slash_char
+
"."
+
lib
for
lib
in
libs
]))
self
.
write
(
' '
.
join
([
lib
+
path_mod
.
slash_char
()
+
"."
+
lib
for
lib
in
libs
]))
self
.
write
(
'
\n
'
)
self
.
writeln
()
self
.
writeln
(
"simulation:
%
s $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)"
%
...
...
@@ -116,19 +117,15 @@ class VsimMakefileWriter(ToolSim):
' '
.
join
(
self
.
additional_deps
))
self
.
writeln
()
for
filename
,
filesource
in
self
.
copy_rules
.
iteritems
():
self
.
write
(
self
.
__create_copy_rule
(
filename
,
filesource
))
self
.
write
(
__create_copy_rule
(
filename
,
filesource
))
for
lib
in
libs
:
self
.
write
(
lib
+
slash_char
+
"."
+
lib
+
":
\n
"
)
self
.
write
(
lib
+
path_mod
.
slash_char
()
+
"."
+
lib
+
":
\n
"
)
vmap_command
=
"vmap $(VMAP_FLAGS)"
self
.
write
(
' '
.
join
([
"
\t
(vlib"
,
lib
,
"&&"
,
vmap_command
,
lib
,
"&&"
,
"touch"
,
lib
+
slash_char
+
"."
+
lib
,
")"
]))
self
.
write
(
' '
.
join
([
"||"
,
del_command
,
lib
,
"
\n
"
]))
self
.
write
(
' '
.
join
([
"
\t
(vlib"
,
lib
,
"&&"
,
vmap_command
,
lib
,
"&&"
,
"touch"
,
lib
+
path_mod
.
slash_char
()
+
"."
+
lib
,
")"
]))
self
.
write
(
' '
.
join
([
"||"
,
path_mod
.
del_command
(),
lib
,
"
\n
"
]))
self
.
write
(
'
\n\n
'
)
# rules for all _primary.dat files for sv
for
vlog
in
fileset
.
filter
(
VerilogFile
):
self
.
write
(
"
%
s:
%
s"
%
(
os
.
path
.
join
(
...
...
@@ -146,7 +143,6 @@ class VsimMakefileWriter(ToolSim):
else
:
# the file is included -> we depend directly on the file
self
.
write
(
"
\\\n
"
+
dep_file
.
rel_path
())
self
.
writeln
()
# self.write("\t\tvlog -work "+vlog.library)
# self.write(" $(VLOG_FLAGS) ")
# if isinstance(vl, SVFile):
...
...
@@ -156,7 +152,6 @@ class VsimMakefileWriter(ToolSim):
# incdir += " "
# self.write(incdir)
# self.writeln(vlog.vlog_opt+" $<")
compile_template
=
string
.
Template
(
"
\t\t
vlog -work ${library} $$(VLOG_FLAGS) "
"${sv_option} $${INCLUDE_DIRS} $$<"
)
...
...
@@ -164,10 +159,9 @@ class VsimMakefileWriter(ToolSim):
library
=
vlog
.
library
,
sv_option
=
"-sv"
if
isinstance
(
vlog
,
SVFile
)
else
""
)
self
.
writeln
(
compile_line
)
self
.
write
(
"
\t\t
@"
+
mkdir_command
+
" $(dir $@)"
)
self
.
write
(
"
\t\t
@"
+
path_mod
.
mkdir_command
()
+
" $(dir $@)"
)
self
.
writeln
(
" && touch $@
\n\n
"
)
self
.
writeln
()
# list rules for all _primary.dat files for vhdl
for
vhdl
in
fileset
.
filter
(
VHDLFile
):
lib
=
vhdl
.
library
...
...
@@ -189,28 +183,6 @@ class VsimMakefileWriter(ToolSim):
self
.
writeln
()
self
.
writeln
(
' '
.
join
([
"
\t\t
vcom $(VCOM_FLAGS)"
,
vhdl
.
vcom_opt
,
"-work"
,
lib
,
"$< "
]))
self
.
writeln
(
"
\t\t
@"
+
mkdir_command
+
self
.
writeln
(
"
\t\t
@"
+
path_mod
.
mkdir_command
()
+
" $(dir $@) && touch $@
\n\n
"
)
def
__create_copy_rule
(
self
,
name
,
src
):
"""Get a Makefile rule named name, which depends on src, copying it to
the local directory."""
if
platform
.
system
()
==
'Windows'
:
copy_command
=
"copy"
else
:
copy_command
=
"cp"
rule
=
"""
%
s:
%
s
\t\t
%
s $< . 2>&1
"""
%
(
name
,
src
,
copy_command
)
return
rule
def
__get_rid_of_vsim_incdirs
(
self
,
vlog_opt
=
""
):
"""Parse the VLOG options and purge the included dirs"""
if
not
vlog_opt
:
vlog_opt
=
""
vlogs
=
vlog_opt
.
split
(
' '
)
ret
=
[]
for
vlog_aux
in
vlogs
:
if
not
vlog_aux
.
startswith
(
"+incdir+"
):
ret
.
append
(
vlog_aux
)
return
' '
.
join
(
ret
)
hdlmake/tools/vivado.py
View file @
4e3713cc
...
...
@@ -62,7 +62,3 @@ class ToolVivado(ToolXilinx):
self
.
_clean_targets
.
update
(
ToolVivado
.
CLEAN_TARGETS
)
self
.
_tcl_controls
.
update
(
ToolVivado
.
TCL_CONTROLS
)
def
detect_version
(
self
,
path
):
"""Get version from Xilinx Vivado binary program"""
return
'unknown'
hdlmake/tools/xilinx.py
View file @
4e3713cc
...
...
@@ -60,10 +60,6 @@ class ToolXilinx(ToolSyn):
self
.
_clean_targets
.
update
(
ToolXilinx
.
CLEAN_TARGETS
)
self
.
_tcl_controls
.
update
(
ToolXilinx
.
TCL_CONTROLS
)
def
detect_version
(
self
,
path
):
"""Get version from Xilinx Vivado binary program"""
return
'unknown'
def
makefile_syn_tcl
(
self
,
top_module
):
"""Create a Xilinx synthesis project by TCL"""
tmp
=
"set_property {0} {1} [{2}]"
...
...
hdlmake/util/path.py
View file @
4e3713cc
...
...
@@ -169,8 +169,31 @@ def check_windows():
return
False
def
del_command
():
"""Get a string with the delete command"""
"""Get a string with the
O.S. specific
delete command"""
if
check_windows
():
return
"rm -rf"
else
:
return
"rm -rf"
def
copy_command
():
"""Get a string with the O.S. specific copy command"""
if
check_windows
():
return
"copy"
else
:
return
"cp"
def
mkdir_command
():
"""Get a string with the O.S. specific mkdir command"""
if
check_windows
():
return
"mkdir"
else
:
return
"mkdir -p"
def
slash_char
():
"""Get a string with the O.S. specific path separator"""
if
check_windows
():
return
"
\\
"
else
:
return
"/"
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