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Hdlmake
Commit 49ff96a4 authored by Paweł Szostek's avatar Paweł Szostek
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Removed unnecessary imports and undefined variable

parent f4a08680
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Showing with 27 additions and 56 deletions
hdlmake
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src/__main__.py
View file @ 49ff96a4
#!/usr/bin/python
# -*- coding: utf-8 -*-
import fileinput
import sys
import path
import time
import os
from connection import Connection
......@@ -22,9 +19,6 @@ def main():
parser.add_option("--manifest-help", action="store_true",
dest="manifest_help", help="print manifest file variables description")
# parser.add_option("-k", "--make", dest="make", action="store_true",
# default=None, help="generate an universal Makefile")
parser.add_option("--make-sim", dest="make_sim", action="store_true",
default=None, help="generate a simulation Makefile")
......@@ -88,7 +82,6 @@ def main():
global_mod.modules_pool = ModulePool(global_mod.top_module)
global_mod.ssh = Connection(ssh_user=options.synth_user, ssh_server=options.synth_server)
tm = global_mod.top_module
pool = global_mod.modules_pool
ssh = global_mod.ssh
from hdlmake_kernel import HdlmakeKernel
......
src/configparser.py
View file @ 49ff96a4
......@@ -138,7 +138,7 @@ class ConfigParser(object):
if name in self.__names():
return [x for x in self.options if x!= None and x.name == name][0]
else:
raise RuntimeException("No such option as " + str(name))
raise RuntimeError("No such option as " + str(name))
def help(self):
p.rawprint("Variables available in a manifest:")
......@@ -154,7 +154,7 @@ class ConfigParser(object):
tmp_def = '""'
line = line.format(opt.name, str(opt.types), opt.help,', default=', tmp_def)
except AttributeError: #no default value
line = line.format(key, str(opt.types), opt.help, "","")
line = line.format(opt.name, str(opt.types), opt.help, "","")
p.rawprint(line)
def add_option(self, name, **others):
......
src/fetch.py
View file @ 49ff96a4
......@@ -93,7 +93,7 @@ class ModuleFetcher:
if rev and rval:
os.chdir(basename)
cmd = "git checkout " + revision
cmd = "git checkout " + rev
p.vprint(cmd)
if os.system(cmd) != 0:
rval = False
......@@ -158,7 +158,7 @@ class ModulePool(list):
cur_dir = os.getcwd()
os.chdir(fetchto)
url, rev = __parse_repo_url(module.url)
url, rev = self.__parse_repo_url(module.url)
basename = path.url_basename(url)
......@@ -212,7 +212,7 @@ class ModulePool(list):
if rev and rval:
os.chdir(basename)
cmd = "git checkout " + revision
cmd = "git checkout " + rev
p.vprint(cmd)
if os.system(cmd) != 0:
rval = False
......
src/flow.py
View file @ 49ff96a4
......@@ -2,6 +2,7 @@
# -*- coding: utf-8 -*-
import xml.dom.minidom as xml
import msg as p
xmlimpl = xml.getDOMImplementation()
......@@ -51,11 +52,11 @@ class ISEProject:
self.props.append(prop)
def __parse_props(self):
for p in self.xml_project.getElementsByTagName("properties")[0].getElementsByTagName("property"):
for xmlp in self.xml_project.getElementsByTagName("properties")[0].getElementsByTagName("property"):
prop = ISEProjectProperty(
p.getAttribute("xil_pn:name"),
p.getAttribute("xil_pn:value"),
p.getAttribute("xil_pn:valueState") == "default"
xmlp.getAttribute("xil_pn:name"),
xmlp.getAttribute("xil_pn:value"),
xmlp.getAttribute("xil_pn:valueState") == "default"
)
self.props.append(prop)
......@@ -70,6 +71,7 @@ class ISEProject:
f = open(filename)
self.xml_doc = xml.parse(f)
self.xml_project = self.xml_doc.getElementsByTagName("project")[0];
import sys
try:
self.__parse_props()
except xml.parsers.expat.ExpatError:
......
src/hdlmake_kernel.py
View file @ 49ff96a4
#!/usr/bin/python
# -*- coding: utf-8 -*-
import re
import fileinput
import sys
import path
import path
import time
import os
from connection import Connection
import random
import string
import global_mod
import msg as p
import optparse
from module import Module
from helper_classes import Manifest, ManifestParser
from fetch import ModulePool
from makefile_writer import MakefileWriter
class HdlmakeKernel(object):
......@@ -25,8 +11,12 @@ class HdlmakeKernel(object):
self.connection = connection
self.make_writer = MakefileWriter("Makefile")
@property
def top_module(self):
return self.modules_pool.get_top_module()
def run(self):
tm = self.modules_pool.get_top_module()
tm = self.top_module
if tm.action == "simulation":
self.generate_modelsim_makefile()
......@@ -65,7 +55,7 @@ class HdlmakeKernel(object):
self.make_writer.generate_ise_makefile(top_mod=self.modules_pool.get_top_module())
def generate_remote_synthesis_makefile(self):
from srcfile import SourceFileFactory, VerilogFile
from srcfile import SourceFileFactory
if self.connection.ssh_user == None or self.connection.ssh_server == None:
p.rawprint("Connection data is not given. Accessing environmental variables in the makefile")
p.rawprint("Generating makefile for remote synthesis...")
......@@ -88,8 +78,6 @@ class HdlmakeKernel(object):
cwd=os.getcwd(), user=self.connection.ssh_user, server=self.connection.ssh_server)
def generate_ise_project(self):
from flow import ISEProject, ISEProjectProperty
top_mod = self.modules_pool.get_top_module()
p.rawprint("Generating/updating ISE project...")
if self.__is_xilinx_screwed():
p.rawprint("Xilinx environment variable is unset or is wrong.\nCannot generate ise project")
......@@ -98,7 +86,7 @@ class HdlmakeKernel(object):
p.echo("A module remains unfetched. Fetching must be done prior to makefile generation")
quit()
ise = self.__check_ise_version()
if os.path.exists(top_mod.syn_project):
if os.path.exists(self.top_module.syn_project):
self.__update_existing_ise_project(ise=ise)
else:
self.__create_new_ise_project(ise=ise)
......@@ -123,7 +111,7 @@ class HdlmakeKernel(object):
def __update_existing_ise_project(self, ise):
from dep_solver import DependencySolver
from flow import ISEProject, ISEProjectProperty
from flow import ISEProject
top_mod = self.modules_pool.get_top_module()
fileset = top_mod.build_global_file_list()
......@@ -172,7 +160,7 @@ class HdlmakeKernel(object):
p.echo("Target " + tm.target + " is not synthesizable")
def run_remote_synthesis(self):
from srcfile import SourceFileFactory, TCLFile
from srcfile import SourceFileFactory
ssh = self.connection
tm = self.modules_pool.get_top_module()
cwd = os.getcwd()
......
src/helper_classes.py
View file @ 49ff96a4
# -*- coding: utf-8 -*-
import path as path_mod
import msg as p
import os
from configparser import ConfigParser
......@@ -59,14 +58,15 @@ class ManifestParser(ConfigParser):
self.add_option('files', default=[], help="List of files from the current module", type='')
self.add_type('files', type=[])
self.add_option('root', default=None, type='', help="Root catalog for local modules")
def add_manifest(self, manifest):
return self.add_config_file(manifest.path)
def parse(self):
return ConfigParser.parse(self)
def print_help():
self.parser.print_help()
def print_help(self):
self.ConfigParser.print_help()
def search_for_package(self):
"""
......
src/makefile_writer.py
View file @ 49ff96a4
......@@ -2,7 +2,6 @@
# -*- coding: utf-8 -*-
import os
import string
import msg as p
class MakefileWriter(object):
def __init__(self, filename):
......@@ -38,7 +37,6 @@ class MakefileWriter(object):
remote_name_tmpl = "R_NAME := {0}"
files_tmpl = "FILES := {0}"
file = self._file
if user == None:
user_tmpl = user_tmpl.format("$(HDLMAKE_USER)")
else:
......@@ -152,9 +150,7 @@ mrproper:
self.write(mk_text);
def generate_fetch_makefile(self, modules_pool, file=None):
import path
rp = os.path.relpath
file = self._file
self.write("#target for fetching all modules stored in repositories\n")
self.write("fetch: ")
self.write(' \\\n'.join(["__"+m.basename()+"_fetch" for m in modules_pool if m.source in ["svn","git"]]))
......@@ -162,7 +158,6 @@ mrproper:
for module in modules_pool:
basename = module.basename()
dir = os.path.join(module.fetchto, basename)
if module.source == "svn":
self.write("__"+basename+"_fetch:\n")
self.write("\t\t")
......@@ -193,7 +188,6 @@ mrproper:
def generate_modelsim_makefile(self, fileset, top_module, file=None):
from time import gmtime, strftime
from srcfile import VerilogFile, VHDLFile
import path
date = strftime("%a, %d %b %Y %H:%M:%S", gmtime())
notices = """#######################################################################
# This makefile has been automatically generated by hdl-make
......@@ -224,7 +218,6 @@ clean:
"""
#open the file and write the above preambule (part 1)
file = self._file
self.write(notices)
self.write(make_preambule_p1)
......@@ -257,8 +250,6 @@ clean:
self.write('\n')
self.write(make_preambule_p2)
vlo = top_module.vlog_opt
vmo = top_module.vmap_opt
for lib in libs:
self.write(lib+"/."+lib+":\n")
self.write(' '.join(["\t(vlib", lib, "&&", "vmap", "-modelsimini modelsim.ini",
......@@ -279,7 +270,6 @@ clean:
vco = top_module.vcom_opt
for vhdl in fileset.filter(VHDLFile):
lib = vhdl.library
basename = vhdl.name
purename = vhdl.purename
#each .dat depends on corresponding .vhd file
self.write(os.path.join(lib, purename, "."+purename) + ": "+vhdl.rel_path()+'\n')
......
src/module.py
View file @ 49ff96a4
......@@ -2,12 +2,9 @@
import path as path_mod
import msg as p
import os
import configparser
import global_mod
from helper_classes import Manifest, ManifestParser
from srcfile import *
from fetch import ModuleFetcher, ModulePool
from srcfile import SourceFileSet, SourceFileFactory
class ManifestOptions(object):
def __init__(self):
......@@ -63,7 +60,7 @@ class Module(object):
self.options["files"] = files
if manifest != None and fetchto == None:
options["fetchto"] = os.path.dirname(manifest.path)
self.options["fetchto"] = os.path.dirname(manifest.path)
if manifest != None and url == None and path == None:
self.options["url"] = os.path.dirname(manifest.path)
......@@ -189,6 +186,7 @@ class Module(object):
#derivate fetchto from the root_module
import sys
if opt_map["root_module"] != None:
self.fetchto = self.root_module.fetchto
else:
......
src/path.py
View file @ 49ff96a4
#!/usr/bin/python
# -*- coding: utf-8 -*-
import os
import msg as p
def url_basename(url):
"""
......@@ -78,6 +77,7 @@ def search_for_manifest(search_path):
"""
Look for manifest in the given folder
"""
import msg as p
p.vprint("Looking for manifest in " + search_path)
for filename in os.listdir(search_path):
if filename == "manifest.py" and not os.path.isdir(filename):
......
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