Commit 3fb85633 authored by David Belohrad's avatar David Belohrad

added support for intel Quartus QSYS files

QSYS files are defined in the same way as QIP. User has to provide
tuple of (<qsys_filename>, <qsys_top_level_module>) in Manifest to
fully declare the module. QIP files generated by QSYS are not needed
in the manifest as Quartus will automatically lauch IP core production
from QSYS if the folder does not exist
parent 12a9d95d
......@@ -319,7 +319,7 @@ class QIPFile(ManualFile):
pass
class QSYSFile(File):
class QSYSFile(ManualFile):
"""Qsys - Altera's System Integration Tool"""
pass
......@@ -405,7 +405,7 @@ def create_source_file(path, module, include_dirs=None):
extension = extension[1:]
logging.debug("add file " + path)
if extension in ("ngc", "qip"):
if extension in ("ngc", "qip", "qsys"):
logging.warning("file %s in %s has no explicit provided units, rewrite as '(filename, unit)'",
path, module)
new_file = File(path=path, module=module)
......@@ -457,4 +457,6 @@ def create_source_file_with_deps(path, module, provide, depends):
return NGCFile(path, module, provide, depends)
elif extension in ['qip', ]:
return QIPFile(path, module, provide, depends)
elif extension in ['qsys', ]:
return QSYSFile(path, module, provide, depends)
raise Exception("Unknown extension '{}' for file {} (with deps)".format(extension, path))
......@@ -72,6 +72,7 @@ class ToolQuartus(MakefileSyn):
VHDLFile: _QUARTUS_SOURCE.format('VHDL_FILE') + _QUARTUS_LIBRARY,
VerilogFile: _QUARTUS_SOURCE.format('VERILOG_FILE') + _QUARTUS_LIBRARY,
SVFile: _QUARTUS_SOURCE.format('SYSTEMVERILOG_FILE') + _QUARTUS_LIBRARY,
QSYSFile: _QUARTUS_SOURCE.format('QSYS_FILE') + _QUARTUS_LIBRARY,
QIPFile: _QUARTUS_SOURCE.format("QIP_FILE") + _QUARTUS_LIBRARY}
CLEAN_TARGETS = {'clean': ["*.rpt", "*.smsg", "*.summary",
......
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