Add Xilinx Coefficient and Memory Initialization files

parent 879eca7f
......@@ -167,6 +167,16 @@ class XDCFile(File):
pass
class COEFile(File):
"""Xilinx Coefficient File"""
pass
class MIFFile(File):
"""Xilinx Memory Initialization File"""
pass
class XCIFile(File):
"""Xilinx Core IP File"""
pass
......@@ -184,6 +194,8 @@ XILINX_FILE_DICT = {
'bd': BDFile,
'xco': XCOFile,
'xdc': XDCFile,
'coe': COEFile,
'mif': MIFFile,
'xci': XCIFile}
......
......@@ -28,7 +28,8 @@ from __future__ import absolute_import
from .xilinx import ToolXilinx
from .make_sim import ToolSim
from hdlmake.srcfile import (XDCFile, XCIFile, NGCFile, XMPFile,
XCOFile, BDFile, TCLFile)
XCOFile, COEFile, BDFile, TCLFile,
MIFFile)
class ToolVivado(ToolXilinx, ToolSim):
......@@ -46,7 +47,8 @@ class ToolVivado(ToolXilinx, ToolSim):
STANDARD_LIBS = ['ieee', 'std']
SUPPORTED_FILES = [XDCFile, XCIFile, NGCFile, XMPFile,
XCOFile, BDFile, TCLFile]
XCOFile, COEFile, BDFile, TCLFile,
MIFFile]
CLEAN_TARGETS = {'clean': ["run.tcl", ".Xil", "*.jou", "*.log", "*.pb",
"$(PROJECT).cache", "$(PROJECT).data", "work",
......
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