@@ -596,6 +596,15 @@ So, once ``hdlmake`` has already generated the project and the Makefile, issuing
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@@ -596,6 +596,15 @@ So, once ``hdlmake`` has already generated the project and the Makefile, issuing
Note that ``hdlmake`` and the examples included in the ``counter`` test have been designed in order to be regular across the different toolchains. In this way, every top Manifest.py for synthesis in the ``syn`` folder can be executed to build a valid bitstream by using the same command sequence we have seen in this section.
Note that ``hdlmake`` and the examples included in the ``counter`` test have been designed in order to be regular across the different toolchains. In this way, every top Manifest.py for synthesis in the ``syn`` folder can be executed to build a valid bitstream by using the same command sequence we have seen in this section.
.. note:: If you are using Xilinx ISE for synthesis, you are now able to make extra more fine-grainde targets for each
of the synthesis stages that ISE supports (remember, ISE will execute by its own the dependent synthesis stages if the associated
targets has not been previously executed):
- ``synthesize``: Synthesize the design.
- ``translate``: Translate to Xilinx format.
- ``map``: Map the translated design into FPGA building blocks.
- ``par``: Execute Place & Route for the selected FPGA device.
- ``bitstream``: Generate the bitstream for FPGA programming.
Handling remote modules
Handling remote modules
-----------------------
-----------------------
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@@ -687,11 +696,38 @@ In order to add external commands to a synthesis top makefile, the following par
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@@ -687,11 +696,38 @@ In order to add external commands to a synthesis top makefile, the following par
If you are using Xilinx ISE synthesis, now you are able to run specific pre/post commands for all the new fine grained synthesis targets: ``{synthesize, translate, map, par, bitstream}``