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Commit 21d46f96 authored by Tristan Gingold's avatar Tristan Gingold
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quartus: avoid writing empty command (minor cleanup).

parent 45af6a31
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Showing with 2 additions and 83 deletions
hdlmake/tools/quartus.py
View file @ 21d46f96
......@@ -243,5 +243,6 @@ class ToolQuartus(MakefileSyn):
command_list.append(self._emit_property(self.SET_GLOBAL_ASSIGNMENT,
{'name': 'POST_FLOW_SCRIPT_FILE',
'value': postflow}))
self._tcl_controls["files"] = '\n'.join(command_list)
if command_list:
self._tcl_controls["files"] = '\n'.join(command_list)
super(ToolQuartus, self)._makefile_syn_files()
testsuite/015quartus/Makefile.ref
View file @ 21d46f96
......@@ -30,7 +30,6 @@ SOURCES_VHDLFile := \
../files/gate.vhdl
files.tcl:
@echo >> $@
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo "set_global_assignment -name VHDL_FILE $(sourcefile) -library work" >> $@ &)
SYN_PRE_PROJECT_CMD :=
......
testsuite/016quartus_nofam/Makefile.ref
View file @ 21d46f96
......@@ -30,7 +30,6 @@ SOURCES_VHDLFile := \
../files/gate.vhdl
files.tcl:
@echo >> $@
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo "set_global_assignment -name VHDL_FILE $(sourcefile) -library work" >> $@ &)
SYN_PRE_PROJECT_CMD :=
......
testsuite/034quartus_prop/Makefile deleted 100644 → 0
View file @ 45af6a31
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
PROJECT := gate_prj
PROJECT_FILE := $(PROJECT).qpf
TOOL_PATH :=
TCL_INTERPRETER := quartus_sh -t
ifneq ($(strip $(TOOL_PATH)),)
TCL_INTERPRETER := $(TOOL_PATH)/$(TCL_INTERPRETER)
endif
SYN_FAMILY := Arria V
SYN_DEVICE := 5agxmb1g4f40c4
SYN_PACKAGE := 40
SYN_GRADE := c4
TCL_CREATE := project_new $(PROJECT)
TCL_OPEN := project_open $(PROJECT)
ifneq ($(wildcard $(PROJECT_FILE)),)
TCL_CREATE := $(TCL_OPEN)
endif
#target for performing local synthesis
all: bitstream
SOURCES_VHDLFile := \
../files/gate.vhdl
files.tcl:
@echo >> $@
@$(foreach sourcefile, $(SOURCES_VHDLFile), echo "set_global_assignment -name VHDL_FILE $(sourcefile) -library work" >> $@ &)
SYN_PRE_PROJECT_CMD :=
SYN_POST_PROJECT_CMD :=
SYN_PRE_BITSTREAM_CMD :=
SYN_POST_BITSTREAM_CMD :=
project.tcl:
echo load_package flow >> $@
echo $(TCL_CREATE) >> $@
echo remove_all_global_assignments -name *_FILE >> $@
echo source files.tcl >> $@
echo set_global_assignment -name FAMILY \"$(SYN_FAMILY)\" >> $@
echo set_global_assignment -name DEVICE \"$(SYN_DEVICE)\" >> $@
echo set_global_assignment -name TOP_LEVEL_ENTITY \"$(TOP_MODULE)\" >> $@
echo set_global_assignment vwaht -name vname \"vval\" -from vfrom -tag vtag -to vto -section_id vsid >> $@
echo set_global_assignment -name SEARCH_PATH \".\" >> $@
project: files.tcl project.tcl
$(SYN_PRE_PROJECT_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_PROJECT_CMD)
touch $@
bitstream.tcl:
echo load_package flow >> $@
echo $(TCL_OPEN) >> $@
echo execute_flow -compile >> $@
bitstream: project bitstream.tcl
$(SYN_PRE_BITSTREAM_CMD)
$(TCL_INTERPRETER) $@.tcl
$(SYN_POST_BITSTREAM_CMD)
touch $@
CLEAN_TARGETS := $(LIBS) *.rpt *.smsg *.summary *.done *.jdi *.pin *.qws db incremental_db $(PROJECT).qsf *.qpf
clean:
rm -rf $(CLEAN_TARGETS)
rm -rf project synthesize translate map par bitstream
rm -rf project.tcl synthesize.tcl translate.tcl map.tcl par.tcl bitstream.tcl files.tcl
mrproper: clean
rm -rf *.sof *.pof *.jam *.jbc *.ekp *.jic
.PHONY: mrproper clean all
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