Skip to content

H
Hdlmake
Commit 199e423f authored by Paweł Szostek's avatar Paweł Szostek
Browse files
Options

make writer: make sure to initialize the makefile

parent 32cebda7
Hide whitespace changes
Inline Side-by-side
Showing with 20 additions and 29 deletions
hdlmake/makefile_writer.py
View file @ 199e423f
......@@ -21,10 +21,9 @@
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
import os
import string
import logging
import global_mod
from string import Template
import string
import fetch
class _StaticClassVariable():
......@@ -47,14 +46,15 @@ class MakefileWriter(object):
self._file.close()
def initialize(self):
if os.path.exists(self._filename):
if os.path.isfile(self._filename):
os.remove(self._filename)
elif os.path.isdir(self._filename):
os.rmdir(self._filename)
self._file = open(self._filename, "a+")
if not _m.initialized:
if os.path.exists(self._filename):
if os.path.isfile(self._filename):
os.remove(self._filename)
elif os.path.isdir(self._filename):
os.rmdir(self._filename)
self._file = open(self._filename, "a+")
_m.initialized = True
self.writeln("########################################")
self.writeln("# This file was generated by hdlmake #")
self.writeln("# http://ohwr.org/projects/hdl-make/ #")
......@@ -64,14 +64,13 @@ class MakefileWriter(object):
def write(self, line=None):
if not _m.initialized:
self.initialize()
_m.initialized = True
self._file.write(line)
def writeln(self, text=None):
if text is None:
self._file.write("\n")
self.write("\n")
else:
self._file.write(text+"\n")
self.write(text+"\n")
def reset_file(self, filename):
self._file.close()
......@@ -81,7 +80,7 @@ class MakefileWriter(object):
from subprocess import PIPE, Popen
if name is None:
import random
name = ''.join(random.choice(string.ascii_letters + string.digits) for x in range(8))
name = ''.join(random.choice(string.ascii_letters + string.digits) for _ in range(8))
whoami = Popen('whoami', shell=True, stdin=PIPE, stdout=PIPE, close_fds=True)
name = whoami.stdout.readlines()[0].strip() + '/' + name
user_tmpl = "USER:={0}"
......@@ -161,7 +160,7 @@ endif
pass
def generate_ise_makefile(self, top_mod, ise_path):
makefile_tmplt = Template("""PROJECT := ${project_name}
makefile_tmplt = string.Template("""PROJECT := ${project_name}
ISE_CRAP := \
*.b \
${syn_top}_summary.html \
......@@ -235,7 +234,6 @@ mrproper:
.PHONY: mrproper clean syn_pre_scipt syn_post_cmd local check_tool
""")
self.initialize()
if top_mod.syn_pre_cmd:
syn_pre_cmd = top_mod.syn_pre_cmd
else:
......@@ -269,15 +267,14 @@ mrproper:
def generate_fetch_makefile(self, modules_pool):
rp = os.path.relpath
self.initialize()
self.write("#target for fetching all modules stored in repositories\n")
self.write("fetch: ")
self.write(' \\\n'.join(["__"+m.basename+"_fetch" for m in modules_pool if m.source in (SVN, GIT)]))
self.write(' \\\n'.join(["__"+m.basename+"_fetch" for m in modules_pool if m.source in (fetch.SVN, fetch.GIT)]))
self.write("\n\n")
for module in modules_pool:
basename = module.basename
if module.source == SVN:
if module.source == fetch.SVN:
self.write("__"+basename+"_fetch:\n")
self.write("\t\tmkdir -p %s\n" % rp(module.fetchto))
self.write("\t\tPWD=$(shell pwd) ")
......@@ -290,7 +287,7 @@ mrproper:
self.write(c)
self.write("; cd $(PWD) \n\n")
elif module.source == GIT:
elif module.source == fetch.GIT:
self.write("__"+basename+"_fetch:\n")
self.write("\t\tmkdir -p %s\n" % rp(module.fetchto))
self.write("\t\t")
......@@ -307,13 +304,11 @@ mrproper:
def generate_iverilog_makefile(self, fileset, top_module, modules_pool):
from srcfile import VerilogFile
#open the file and write the above preambule (part 1)
self.initialize()
import global_mod
#open the file and write the above preambule (part 1)
# for m in global_mod.mod_pool:
for f in global_mod.top_module.incl_makefiles:
self.writeln("include " + f)
libs = set(f.library for f in fileset)
target_list = []
for vl in fileset.filter(VerilogFile):
rel_dir_path = os.path.dirname(vl.rel_path())
......@@ -345,12 +340,10 @@ mrproper:
for m in global_mod.mod_pool:
for f in m.sim_only_files:
sim_only_files.append(f.name)
top_name = global_mod.top_module.syn_top
top_name_syn_deps = []
bit_targets = []
for m in global_mod.mod_pool:
bit_targets = bit_targets + m.bit_file_targets
bit_targets = bit_targets + list(m.bit_file_targets)
for bt in bit_targets:
bt = bt.purename
bt_syn_deps = []
......@@ -384,7 +377,7 @@ VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini """ + self.__get_rid_of_incdirs(top_module.vlog_opt) + """
"""
make_preambule_p2 = Template("""## rules #################################
make_preambule_p2 = string.Template("""## rules #################################
sim: sim_pre_cmd modelsim.ini $$(LIB_IND) $$(VERILOG_OBJ) $$(VHDL_OBJ)
$$(VERILOG_OBJ): $$(VHDL_OBJ)
$$(VHDL_OBJ): $$(LIB_IND) modelsim.ini
......@@ -403,7 +396,6 @@ clean:
""")
#open the file and write the above preambule (part 1)
self.initialize()
self.write(make_preambule_p1)
self.write("VERILOG_SRC := ")
......@@ -526,7 +518,6 @@ isim.wdb
"""
#open the file and write the above preambule (part 1)
self.initialize()
self.write(make_preambule_p1)
self.write("VERILOG_SRC := ")
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment