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Hdlmake
Commit 0c0a06d8 authored by garcialasheras's avatar garcialasheras
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Relocate XilinxsiminiReader Class

parent 8effe74c
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Showing with 81 additions and 74 deletions
hdlmake/__main__.py
View file @ 0c0a06d8
......@@ -37,7 +37,7 @@ from action import (CheckCondition, CleanModules, FetchModules, GenerateFetchMak
ListModules, MergeCores, GenerateSimulationMakefile,
GenerateSynthesisMakefile, GenerateRemoteSynthesisMakefile, GenerateSynthesisProject)
from argument_parser import get_argument_parser
#from argument_parser import get_argument_parser
#try:
# from build_hash import BUILD_ID
......@@ -150,7 +150,7 @@ def main():
logging.error("`sim_tool' manifest variable has to be specified. "
"Otherwise hdlmake doesn't know how to simulate the project")
quit()
action = GenerateSimulationMakefile
action = [ GenerateSimulationMakefile ]
elif top_mod.action == "synthesis":
if not top_mod.syn_tool:
logging.error("`syn_tool' manifest variable has to be specified. "
......
hdlmake/tools/ise/ise.py
View file @ 0c0a06d8
......@@ -564,74 +564,3 @@ class ISEProjectProperty:
return prop
class XilinxsiminiReader(object):
def __init__(self, path=None):
if path is None:
path = self.xilinxsim_ini_dir() + "/xilinxsim.ini"
self.path = path
# Parse the xilinxsim.ini file to get the referenced libraries
def get_libraries(self):
libs = []
try:
ini = open(self.path, "r")
except Exception:
raise RuntimeError("Can't open existing xilinxsim.ini file")
#p.info("Reading 'xilinxsim.ini' located in: '"+ str(self.path))
# Read loggical libraries name, skipping comments and other
#possible sections
for line in ini:
# Read line by line, skipping comments and striping newline
line = line.split('--')[0].strip()
# Still in comments section
if line == "":
continue
# Not in comments section. Library section:
#<logical_library> = <phisical_path>
line = line.split('=')
lib = line[0].strip()
libs.append(lib.lower())
return libs
@staticmethod
def xilinxsim_ini_dir():
# Does not really need this
# try:
# host_platform = os.environ["HOST_PLATFORM"]
# except KeyError:
# logging.error("Please set the environment variable HOST_PLATFORM")
# quit()
#if global_mod.env["xilinx"]:
# xilinx_dir = global_mod.env["xilinx"]
if global_mod.env["isim_path"]:
xilinx_dir = str(os.path.join(global_mod.env["isim_path"],"..",".."))
else:
logging.error("Cannot calculate xilinx tools base directory")
quit()
hdl_language = 'vhdl' #'verilog'
if sys.platform == 'cygwin':
os_prefix = 'nt'
else:
os_prefix = 'lin'
if global_mod.env["architecture"] == 32:
arch_sufix = ''
else:
arch_sufix = '64'
xilinx_ini_path = str(os.path.join(xilinx_dir,
hdl_language,
"hdp",
os_prefix + arch_sufix))
# Ensure the path is absolute and normalized
return os.path.abspath(xilinx_ini_path)
hdlmake/tools/isim/isim.py
View file @ 0c0a06d8
......@@ -26,9 +26,13 @@
import os.path
from subprocess import Popen, PIPE
import os
import sys
import string
from string import Template
import fetch
import global_mod
from makefile_writer import MakefileWriter
......@@ -69,7 +73,7 @@ class ToolControls(MakefileWriter):
def generate_simulation_makefile(self, fileset, top_module):
from srcfile import VerilogFile, VHDLFile
from tools.ise import XilinxsiminiReader
#from tools.ise import XilinxsiminiReader
make_preambule_p1 = """## variables #############################
PWD := $(shell pwd)
TOP_MODULE := """ + top_module.top_module + """
......@@ -236,3 +240,77 @@ isim.wdb isim_proj isim_proj.*
else:
skip = True
return ' '.join(ret)
class XilinxsiminiReader(object):
def __init__(self, path=None):
if path is None:
path = self.xilinxsim_ini_dir() + "/xilinxsim.ini"
self.path = path
# Parse the xilinxsim.ini file to get the referenced libraries
def get_libraries(self):
libs = []
try:
ini = open(self.path, "r")
except Exception:
raise RuntimeError("Can't open existing xilinxsim.ini file")
#p.info("Reading 'xilinxsim.ini' located in: '"+ str(self.path))
# Read loggical libraries name, skipping comments and other
#possible sections
for line in ini:
# Read line by line, skipping comments and striping newline
line = line.split('--')[0].strip()
# Still in comments section
if line == "":
continue
# Not in comments section. Library section:
#<logical_library> = <phisical_path>
line = line.split('=')
lib = line[0].strip()
libs.append(lib.lower())
return libs
@staticmethod
def xilinxsim_ini_dir():
# Does not really need this
# try:
# host_platform = os.environ["HOST_PLATFORM"]
# except KeyError:
# logging.error("Please set the environment variable HOST_PLATFORM")
# quit()
#if global_mod.env["xilinx"]:
# xilinx_dir = global_mod.env["xilinx"]
if global_mod.env["isim_path"]:
xilinx_dir = str(os.path.join(global_mod.env["isim_path"],"..",".."))
else:
logging.error("Cannot calculate xilinx tools base directory")
quit()
hdl_language = 'vhdl' #'verilog'
if sys.platform == 'cygwin':
os_prefix = 'nt'
else:
os_prefix = 'lin'
if global_mod.env["architecture"] == 32:
arch_sufix = ''
else:
arch_sufix = '64'
xilinx_ini_path = str(os.path.join(xilinx_dir,
hdl_language,
"hdp",
os_prefix + arch_sufix))
# Ensure the path is absolute and normalized
return os.path.abspath(xilinx_ini_path)
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