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Commit 02b4244e authored by Tristan Gingold's avatar Tristan Gingold
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Merge branch 'ltgt_bug_#115_b' into 'develop' 

Add VHDL Library support to GHDL Synthesis

See merge request !8
parents 5a66869d 6a9c1933
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Showing with 70 additions and 16 deletions
hdlmake/tools/ghdl_syn.py
View file @ 02b4244e
......@@ -29,8 +29,8 @@ class GhdlSyn(ToolMakefile):
'linux_bin': 'ghdl',
'project_ext': ''}
CLEAN_TARGETS = {'clean': [],
'mrproper': []}
CLEAN_TARGETS = {'clean': ["files.tcl", "*.vhd"],
'mrproper': ["files.tcl", "*.vhd"]}
SYSTEM_LIBS = ['vhdl']
HDL_FILES = {VHDLFile: '$(sourcefile)'}
......@@ -38,6 +38,7 @@ class GhdlSyn(ToolMakefile):
def __init__(self):
super(GhdlSyn, self).__init__()
self._tcl_controls = {}
self.default_library = "work"
def write_makefile(self, top_manifest, fileset, filename=None):
"""Generate a Makefile for the specific synthesis tool"""
......@@ -68,19 +69,21 @@ class GhdlSyn(ToolMakefile):
sources_list = []
fileset_dict.update(self.HDL_FILES)
fileset_dict.update(self.SUPPORTED_FILES)
file_list = []
for filetype in fileset_dict:
file_list = []
for file_aux in self.fileset:
for file_aux in self.fileset.sort():
if isinstance(file_aux, filetype):
if filetype == VerilogFile and isinstance(file_aux, SVFile):
# Discard SVerilog files for verilog type.
continue
file_list.append(shell.tclpath(file_aux.rel_path()))
#file_list.append(shell.tclpath(file_aux.rel_path()))
libname = '--work={0} '.format(file_aux.library)
filename = shell.tclpath(file_aux.rel_path())
out_string = libname + filename
logging.info(self.TOOL_INFO['name'] + "OK: " + out_string)
file_list.append( out_string)
# need to change the above to have a prefix of: --work=<libname>
if not file_list == []:
ret.append(
'SOURCES_{0} := \\\n'
'{1}\n'.format(filetype.__name__,
' \\\n'.join(file_list)))
if not fileset_dict[filetype] is None:
sources_list.append(filetype)
self.writeln('\n'.join(ret))
......@@ -94,14 +97,14 @@ class GhdlSyn(ToolMakefile):
if shell.check_windows_commands():
command_string = command_string.replace("'", "")
self.writeln(command_string)
for filetype in sources_list:
filetype_string = ('\t\t@$(foreach sourcefile,'
' $(SOURCES_{0}), echo "{1}" >> $@ &)'.format(
filetype.__name__, fileset_dict[filetype]))
if shell.check_windows_commands():
filetype_string = filetype_string.replace(
'"', '')
self.writeln(filetype_string)
for srcfile_str in file_list:
filetype_string = '\t\t@echo ' + srcfile_str + ' >> $@'
if shell.check_windows_commands():
filetype_string = filetype_string.replace(
'"', '')
self.writeln(filetype_string)
self.writeln()
def _makefile_syn_local(self):
......@@ -111,6 +114,7 @@ class GhdlSyn(ToolMakefile):
def _makefile_syn_build(self):
"""Generate the synthesis Makefile targets for handling design build"""
# HOW to set a file to write the synthesis result into....
self.writeln("""\
synthesis: files.tcl
\t$(GHDL) --synth $(GHDL_OPT) @files.tcl -e $(TOP_MODULE)
......
testsuite/115_ghdlsyn_libraries/Makefile.ref 0 → 100644
View file @ 02b4244e
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := lib_c.repinned_top
TOOL_PATH := /usr/local/bin
GHDL := ghdl
GHDL_OPT :=
#target for performing local synthesis
all: synthesis
files.tcl:
@echo --work=lib_a ../113_ise_libraries/rtl/lib_a/axi_regs.vhd >> $@
@echo --work=lib_a ../113_ise_libraries/rtl/lib_a/register_access_fns_pkg.vhd >> $@
@echo --work=lib_a ../113_ise_libraries/rtl/lib_a/register_types_pkg.vhd >> $@
@echo --work=lib_b ../113_ise_libraries/rtl/lib_b/axi_regs.vhd >> $@
@echo --work=lib_b ../113_ise_libraries/rtl/lib_b/register_access_fns_pkg.vhd >> $@
@echo --work=lib_b ../113_ise_libraries/rtl/lib_b/register_types_pkg.vhd >> $@
@echo --work=lib_c ../113_ise_libraries/rtl/lib_c/merged_top.vhd >> $@
@echo --work=lib_c ../113_ise_libraries/rtl/lib_c/repinned_top.vhd >> $@
synthesis: files.tcl
$(GHDL) --synth $(GHDL_OPT) @files.tcl -e $(TOP_MODULE)
CLEAN_TARGETS := $(LIBS) files.tcl *.vhd
clean:
rm -rf $(CLEAN_TARGETS)
mrproper: clean
rm -rf files.tcl *.vhd
.PHONY: mrproper clean all
testsuite/115_ghdlsyn_libraries/Manifest.py 0 → 100644
View file @ 02b4244e
#target = "altera"
action = "synthesis"
syn_top = "lib_c.repinned_top"
syn_project = "demo"
syn_tool = "ghdl"
modules = {
"local" : [ "../113_ise_libraries/rtl/lib_c" ],
}
testsuite/test_all.py
View file @ 02b4244e
......@@ -546,6 +546,9 @@ def test_vhdl_libraries_ise_113():
run_compare(path="113_ise_libraries")
def test_vhdl_libraries_GHDLSyn_115():
run_compare(path="115_ghdlsyn_libraries")
@pytest.mark.xfail
def test_xfail():
......
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