Commits · 8cd9c99cab1f2c5f50e468592d55602d39772a8d · Projects / Hdlmake · GitLab

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Apr 27, 2015
- Fixed issue with vcom, vmap and vsim options · 8cd9c99c
  Javier D. Garcia-Lasheras authored 9 years ago
  
  8cd9c99c
Apr 24, 2015
- Merge remote-tracking branch 'origin/release-2.1' · d342f521
  Javier D. Garcia-Lasheras authored 9 years ago
  
  2.1
  
  d342f521
Mar 28, 2015
- Added Aldec Riviera support for simulation. · 8bd44158
  Josh Smith authored 9 years ago
  
  8bd44158
- Fix Copyright notice in VHDL Parser · 832a1f6e
  Javier D. Garcia-Lasheras authored 9 years ago
  
  832a1f6e
- Merge remote-tracking branch 'origin/VHDL_parser_fix' into release-2.1 · c86ec698
  Javier D. Garcia-Lasheras authored 9 years ago
  
  c86ec698
Mar 27, 2015
- Fix bug 1073. · 187e97e8
  Adrian Fiergolski authored 9 years ago
```
Deep modifications of the VHDL parser.
```
  187e97e8
Mar 16, 2015
- Improve the support for unknown options definition from outside the Top Manifest.py · 66d11884
  Javier D. Garcia-Lasheras authored 10 years ago
  
  66d11884
Feb 09, 2015
- Add incremental and remote ISE synthesis docs · 64bc3983
  Garcia-Lasheras authored 10 years ago
  
  64bc3983
Feb 08, 2015
- Fix minor issues in custom variables and conditional execution docs · e3122f5e
  Garcia-Lasheras authored 10 years ago
  
  e3122f5e
- Explain custom variables and conditional execution in docs · 270ac2f3
  Garcia-Lasheras authored 10 years ago
  
  270ac2f3
- Explain pre and post commands in docs · 4f3563f0
  Garcia-Lasheras authored 10 years ago
  
  4f3563f0
- Fix tables missaligment in docs · 90b060c8
  Garcia-Lasheras authored 10 years ago
  
  90b060c8
- Put all the Manifest variables inside a table · e6c6d48a
  Garcia-Lasheras authored 10 years ago
  
  e6c6d48a
- Use an standard table for top manifest variables · 7fae4ef1
  Garcia-Lasheras authored 10 years ago
  
  7fae4ef1
- Initial CSV table for manifest variables (2) · d9c09fe7
  Garcia-Lasheras authored 10 years ago
  
  d9c09fe7
- Initial CSV table for manifest variables · a2e6daef
  Garcia-Lasheras authored 10 years ago
  
  a2e6daef
- Bumping Sphinx versions to 2.1 · 022bb5b3
  Garcia-Lasheras authored 10 years ago
  
  022bb5b3
- Bumping documentation to 2.1 · d1f71ba1
  Garcia-Lasheras authored 10 years ago
  
  d1f71ba1
- Bumped version number to 2.1 · 3b727474
  Garcia-Lasheras authored 10 years ago
  
  3b727474
- Fix an ugly error message · 8704a0b0
  Garcia-Lasheras authored 10 years ago
  
  8704a0b0
- Check for action, syn_tool and sim_tool before trying to load the tool module · 9e3ea524
  Garcia-Lasheras authored 10 years ago
  
  9e3ea524
- Vivado cannot be used with an Spartan6 device: remove SPEC v4 Vivado test · 427aa7bd
  Garcia-Lasheras authored 10 years ago
  
  427aa7bd
- Merge branch 'tune-ise-remote-synthesis' into develop · 90a22a00
  Garcia-Lasheras authored 10 years ago
  
  90a22a00
- Support for remote incremental build · 3975ca9c
  Garcia-Lasheras authored 10 years ago
  
  3975ca9c
- Split synthesis command and TCL file generation · c4939ca7
  Garcia-Lasheras authored 10 years ago
  
  c4939ca7
- Update supported Xilinx 7 Series families list · ef8c0ba6
  Garcia-Lasheras authored 10 years ago
  
  ef8c0ba6
Feb 07, 2015
- Merge branch 'iverilog-vhdl-counter-test' into develop · fa0d59ac
  Garcia-Lasheras authored 10 years ago
  
  fa0d59ac
- Set ivl_vhdl_work as an object to be cleaned · c3aecb01
  Garcia-Lasheras authored 10 years ago
  
  c3aecb01
- Add IVerilog VHDL based counter test · e8d09edb
  Garcia-Lasheras authored 10 years ago
  
  e8d09edb
- Merge branch 'reorder-external-sim-commands' into develop · 6d4d3661
  Garcia-Lasheras authored 10 years ago
  
  6d4d3661
- Reorder simulation and external commands targets · 50fc9d35
  Garcia-Lasheras authored 10 years ago
  
  50fc9d35
- Merge branch 'syn-external-commands' into develop (fix) · 928c2c7b
  Garcia-Lasheras authored 10 years ago
  
  928c2c7b
- Add synthesis Makefile target to PHONY · 5fd96307
  Garcia-Lasheras authored 10 years ago
  
  5fd96307
- Merge branch 'syn-external-commands' into develop · 5ae64076
  Garcia-Lasheras authored 10 years ago
  
  5ae64076
- Fix pre and post synthesis commands and reorder Makefiles · e9dcbfd4
  Garcia-Lasheras authored 10 years ago
  
  e9dcbfd4
- Merge branch 'javi-vivado' into develop · 136a9380
  Garcia-Lasheras authored 10 years ago
  
  136a9380
- Add test counter example for Vivado · 32db68e1
  Garcia-Lasheras authored 10 years ago
  
  32db68e1
- Merge branch 'adrian_instantiation_sensitiveness' into develop · de91d33a
  Garcia-Lasheras authored 10 years ago
  
  de91d33a
- Merge branch 'javi-incremental-ise-build' into develop · fa7350bc
  Garcia-Lasheras authored 10 years ago
  
  fa7350bc
Jan 02, 2015
- Add missing TCLFile import in Vivado · dc0e2dd8
  Javier D. Garcia-Lasheras authored 10 years ago
  
  dc0e2dd8