Add missing TCLFile import in Vivado

hdlmake/tools/vivado/vivado.py

@@ -228,7 +228,7 @@ mrproper:
         tmp = "add_files -norecurse {0}"
         tcl = "source {0}"
         ret = []
-        from srcfile import VHDLFile, VerilogFile, SVFile, UCFFile, NGCFile, XMPFile, XCOFile, BDFile
+        from srcfile import VHDLFile, VerilogFile, SVFile, UCFFile, NGCFile, XMPFile, XCOFile, BDFile, TCLFile
         for f in self.files:
             if isinstance(f, VHDLFile) or isinstance(f, VerilogFile) or isinstance(f, SVFile) or isinstance(f, UCFFile) or isinstance(f, NGCFile) or isinstance(f, XMPFile) or isinstance(f, XCOFile) or isinstance(f, BDFile):
                 line = tmp.format(f.rel_path())