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Hdlmake
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136a9380021df8add1c98a07f4f53cde96067380
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hdl-make
tests
counter
syn
spec_v4_vivado
vhdl
Manifest.py
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Feb 07, 2015
Add test counter example for Vivado
· 32db68e1
Garcia-Lasheras
authored
10 years ago
32db68e1
Sep 16, 2014
Simple 8-bit counter test for syn/sim, VHDL/Verilog
· cc56877a
garcialasheras
authored
10 years ago
cc56877a
