Commits · 136a9380021df8add1c98a07f4f53cde96067380 · Projects / Hdlmake · GitLab

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Feb 07, 2015
- Add test counter example for Vivado · 32db68e1
  Garcia-Lasheras authored 10 years ago
  
  32db68e1
Nov 13, 2014
- Fix bug 1028. · d82dc290
  Adrian Fiergolski authored 10 years ago
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Fix bugs in test files.
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  d82dc290
- Fix test for bug 1028. · e42a630a
  Adrian Fiergolski authored 10 years ago
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Add logs for found primitives in vlog_parser.
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  e42a630a
- Add test for bug 1028. · b7f4c066
  Adrian Fiergolski authored 10 years ago
  
  b7f4c066
Oct 10, 2014
- Disable optimisations in order to have visibility of counter's signal. · aabe6c84
  Adrian Fiergolski authored 10 years ago
  
  2.0
  
  aabe6c84
Oct 09, 2014
- Change sim_tool variable in Questa test from vsim to modelsim · 840f19e3
  Javier D. Garcia-Lasheras authored 10 years ago
  
  840f19e3
- Test for UVM and SystemVerilog support on Questa · 5a293d83
  Adrian Fiergolski authored 10 years ago
  
  5a293d83
Sep 16, 2014
- Simple 8-bit counter test for syn/sim, VHDL/Verilog · cc56877a
  garcialasheras authored 10 years ago
  
  cc56877a
Apr 28, 2014
- Add a new test for Verilog remote synthesis · 9e679858
  Javier D. Garcia-Lasheras authored 10 years ago
  
  9e679858
- Add a new test for vhdl remote synthesis · 7c2e1944
  Javier D. Garcia-Lasheras authored 10 years ago
  
  7c2e1944
- Add some verilog tests to filter · 5e78f2a2
  Javier D. Garcia-Lasheras authored 10 years ago
  
  5e78f2a2
Apr 27, 2014
- Fix a problem in simulation isim test · 87e3bbc5
  Javier D. Garcia-Lasheras authored 10 years ago
  
  87e3bbc5
- Create a sim folder in filter test · f176dcf3
  Javier D. Garcia-Lasheras authored 10 years ago
  
  f176dcf3
Apr 26, 2014
- Tests for simulation and synthesis · 89fa25b6
  Javier D. Garcia-Lasheras authored 10 years ago
  
  89fa25b6
Jul 20, 2013
- beginning of start of bootstrapping of ... of tests · ee56d9bb
  Paweł Szostek authored 11 years ago
  
  ee56d9bb