hdl: simplify l2p_dma_master fifo reset logic

fd964ff1 · Dimitris Lampridis · b60a5cf2 · fd964ff1
Commit fd964ff1 authored Oct 27, 2023 by Dimitris Lampridis
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Showing with 6 additions and 19 deletions

l2p_dma_master.vhd hdl/rtl/l2p_dma_master.vhd +6 -19

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--- a/hdl/rtl/l2p_dma_master.vhd
+++ b/hdl/rtl/l2p_dma_master.vhd
@@ -147,9 +147,6 @@ architecture arch of l2p_dma_master is
  signal data_fifo_full_next : std_logic;
  signal data_fifo_rst_wr_n  : std_logic;
  signal data_fifo_rst_rd_n  : std_logic;
-  signal fsm_fifo_rst_sync_n : std_logic;
-  signal rst_sync_n          : std_logic;
-  signal wb_dma_rst_sync_n   : std_logic;

 begin

@@ -486,29 +483,19 @@ begin
  -- Flow Control FIFO (cross-clock domain)
  -----------------------------------------

-  cmp_wb_dma_rst_n_sync : gc_sync
+  cmp_data_fifo_rst_rd_n_sync : gc_sync
    port map (
      clk_i     => clk_i,
-      rst_n_a_i => '1',
+      rst_n_a_i => fsm_fifo_rst_n,
      d_i       => wb_dma_rst_n_i,
-      q_o       => wb_dma_rst_sync_n);
+      q_o       => data_fifo_rst_rd_n);

-  cmp_fsm_fifo_rst_n_sync : gc_sync
+  cmp_data_fifo_rst_wr_n_sync : gc_sync
    port map (
      clk_i     => wb_dma_clk_i,
-      rst_n_a_i => '1',
+      rst_n_a_i => wb_dma_rst_n_i,
      d_i       => fsm_fifo_rst_n,
-      q_o       => fsm_fifo_rst_sync_n);
-
-  cmp_rst_n_sync : gc_sync
-    port map (
-      clk_i     => wb_dma_clk_i,
-      rst_n_a_i => '1',
-      d_i       => rst_n_i,
-      q_o       => rst_sync_n);
-
-  data_fifo_rst_wr_n <= wb_dma_rst_n_i and fsm_fifo_rst_sync_n and rst_sync_n;
-  data_fifo_rst_rd_n <= wb_dma_rst_sync_n and fsm_fifo_rst_n and rst_n_i;
+      q_o       => data_fifo_rst_wr_n);

  p_fifo_full_delay_reg : process (wb_dma_clk_i) is
  begin