csr wishbone master takes stall into account. Should now be compatible with classic slaves.

f5a7bea2 · Matthieu Cattin · c90f1f36 · f5a7bea2 · f5a7bea2 · f5a7bea2
Commit f5a7bea2 authored Aug 02, 2011 by Matthieu Cattin
4 changed files
--- a/hdl/gn4124core/rtl/wbmaster32.vhd
+++ b/hdl/gn4124core/rtl/wbmaster32.vhd
@@ -419,7 +419,9 @@ begin
          wishbone_current_state <= WB_WAIT_ACK;

        when WB_WAIT_ACK =>
-          wb_stb_t <= '0';
+          if wb_stall_t = '0' then
+            wb_stb_t <= '0';
+          end if;
          if (wb_ack_t = '1') then
            -- for read cycles write read data to fifo
            if (wb_we_t = '0') then

--- a/hdl/spec/rtl/spec_gn4124_test.vhd
+++ b/hdl/spec/rtl/spec_gn4124_test.vhd
@@ -528,7 +528,8 @@ begin
      dummy_stat_reg_switch_i => dummy_stat_reg_switch
      );

-  wb_stall(2 downto 1) <= "00";
+  wb_stall(1) <= '0' when wb_cyc(1) = '0' else not(wb_ack(1));
+  wb_stall(2) <= '0' when wb_cyc(2) = '0' else not(wb_ack(2));

  dummy_stat_reg_1      <= X"DEADBABE";
  dummy_stat_reg_2      <= X"BEEFFACE";

--- a/hdl/spec/rtl/wb_addr_decoder.vhd
+++ b/hdl/spec/rtl/wb_addr_decoder.vhd
@@ -148,10 +148,10 @@ begin
  end process p_ack_mux;

  -- Select stall line of the active peripheral
-  p_stall_mux : process (wb_stall_i, wb_periph_addr)
+  p_stall_mux : process (wb_stall_i, s_wb_periph_addr)
  begin
-    if (to_integer(unsigned(wb_periph_addr)) < g_WB_SLAVES_NB) then
-      wbm_stall_o <= wb_stall_i(to_integer(unsigned(wb_periph_addr)));
+    if (to_integer(unsigned(s_wb_periph_addr)) < g_WB_SLAVES_NB) then
+      wbm_stall_o <= wb_stall_i(to_integer(unsigned(s_wb_periph_addr)));
    else
      wbm_stall_o <= '0';
    end if;

--- a/hdl/spec/syn/spec_gn4124_test.bin
+++ b/hdl/spec/syn/spec_gn4124_test.bin