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Gennum GN4124 core
Commit c90f1f36 authored by Matthieu Cattin's avatar Matthieu Cattin
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csr wishbone address decoder removed from gennum core.

parent be664f3d
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hdl/gn4124core/rtl/spartan6/gn4124_core.vhd
View file @ c90f1f36
......@@ -40,12 +40,7 @@ use UNISIM.vcomponents.all;
--==============================================================================
entity gn4124_core is
generic(
g_IS_SPARTAN6 : boolean := true; -- This generic is used to instanciate spartan6 specific primitives
g_BAR0_APERTURE : integer := 20; -- BAR0 aperture, defined in GN4124 PCI_BAR_CONFIG register (0x80C)
-- => number of bits to address periph on the board
g_CSR_WB_SLAVES_NB : integer := 1; -- Number of CSR wishbone slaves
g_DMA_WB_SLAVES_NB : integer := 1; -- Number of DMA wishbone slaves
g_DMA_WB_ADDR_WIDTH : integer := 26 -- DMA wishbone address bus width
g_IS_SPARTAN6 : boolean := true -- This generic is used to instanciate spartan6 specific primitives
);
port
(
......@@ -84,8 +79,8 @@ entity gn4124_core is
l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
l2p_dframe_o : out std_logic; -- Transmit Data Frame
l2p_valid_o : out std_logic; -- Transmit Data Valid
l2p_edb_o : out std_logic; -- Packet termination and discard
-- L2P Control
l2p_edb_o : out std_logic; -- Packet termination and discard
l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
......@@ -98,29 +93,43 @@ entity gn4124_core is
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
---------------------------------------------------------
-- Target interface (CSR wishbone master)
wb_clk_i : in std_logic;
wb_adr_o : out std_logic_vector(g_BAR0_APERTURE-log2_ceil(g_CSR_WB_SLAVES_NB+1)-1 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic;
wb_we_o : out std_logic;
wb_cyc_o : out std_logic_vector(g_CSR_WB_SLAVES_NB-1 downto 0);
wb_dat_i : in std_logic_vector((32*g_CSR_WB_SLAVES_NB)-1 downto 0); -- Data in
wb_ack_i : in std_logic_vector(g_CSR_WB_SLAVES_NB-1 downto 0);
-- DMA registers wishbone interface (slave classic)
dma_reg_clk_i : in std_logic;
dma_reg_adr_i : in std_logic_vector(31 downto 0);
dma_reg_dat_i : in std_logic_vector(31 downto 0);
dma_reg_sel_i : in std_logic_vector(3 downto 0);
dma_reg_stb_i : in std_logic;
dma_reg_we_i : in std_logic;
dma_reg_cyc_i : in std_logic;
dma_reg_dat_o : out std_logic_vector(31 downto 0);
dma_reg_ack_o : out std_logic;
dma_reg_stall_o : out std_logic;
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
csr_clk_i : in std_logic;
csr_adr_o : out std_logic_vector(31 downto 0);
csr_dat_o : out std_logic_vector(31 downto 0);
csr_sel_o : out std_logic_vector(3 downto 0);
csr_stb_o : out std_logic;
csr_we_o : out std_logic;
csr_cyc_o : out std_logic;
csr_dat_i : in std_logic_vector(31 downto 0);
csr_ack_i : in std_logic;
csr_stall_i : in std_logic;
---------------------------------------------------------
-- DMA interface (Pipelined wishbone master)
-- DMA wishbone interface (master pipelined)
dma_clk_i : in std_logic;
dma_adr_o : out std_logic_vector(31 downto 0);
dma_dat_o : out std_logic_vector(31 downto 0); -- Data out
dma_sel_o : out std_logic_vector(3 downto 0); -- Byte select
dma_dat_o : out std_logic_vector(31 downto 0);
dma_sel_o : out std_logic_vector(3 downto 0);
dma_stb_o : out std_logic;
dma_we_o : out std_logic;
dma_cyc_o : out std_logic; --_vector(g_DMA_WB_SLAVES_NB-1 downto 0);
dma_dat_i : in std_logic_vector((32*g_DMA_WB_SLAVES_NB)-1 downto 0); -- Data in
dma_ack_i : in std_logic; --_vector(g_DMA_WB_SLAVES_NB-1 downto 0);
dma_stall_i : in std_logic--_vector(g_DMA_WB_SLAVES_NB-1 downto 0) -- for pipelined Wishbone
dma_cyc_o : out std_logic;
dma_dat_i : in std_logic_vector(31 downto 0);
dma_ack_i : in std_logic;
dma_stall_i : in std_logic
);
end gn4124_core;
......@@ -284,16 +293,7 @@ architecture rtl of gn4124_core is
------------------------------------------------------------------------------
-- CSR wishbone bus
------------------------------------------------------------------------------
signal wb_adr : std_logic_vector(g_BAR0_APERTURE-log2_ceil(g_CSR_WB_SLAVES_NB+1)-1 downto 0);
signal wb_dat_s2m : std_logic_vector((32*(g_CSR_WB_SLAVES_NB+1))-1 downto 0);
signal wb_dat_m2s : std_logic_vector(31 downto 0);
signal wb_sel : std_logic_vector(3 downto 0);
signal wb_cyc : std_logic_vector(g_CSR_WB_SLAVES_NB downto 0);
signal wb_stb : std_logic;
signal wb_we : std_logic;
signal wb_ack : std_logic_vector(g_CSR_WB_SLAVES_NB downto 0);
signal wb_ack_dma_ctrl : std_logic;
signal wb_dat_s2m_dma_ctrl : std_logic_vector(31 downto 0);
signal csr_adr : std_logic_vector(30 downto 0);
------------------------------------------------------------------------------
-- DMA wishbone bus
......@@ -469,11 +469,6 @@ begin
-- Wishbone master
-----------------------------------------------------------------------------
cmp_wbmaster32 : wbmaster32
generic map
(
g_BAR0_APERTURE => g_BAR0_APERTURE,
g_WB_SLAVES_NB => (g_CSR_WB_SLAVES_NB + 1) -- +1 for the DMA controller (wb slave always present)
)
port map
(
---------------------------------------------------------
......@@ -517,25 +512,20 @@ begin
---------------------------------------------------------
-- Wishbone Interface
wb_clk_i => wb_clk_i,
wb_adr_o => wb_adr,
wb_dat_i => wb_dat_s2m,
wb_dat_o => wb_dat_m2s,
wb_sel_o => wb_sel,
wb_cyc_o => wb_cyc,
wb_stb_o => wb_stb,
wb_we_o => wb_we,
wb_ack_i => wb_ack
wb_clk_i => csr_clk_i,
wb_adr_o => csr_adr,
wb_dat_i => csr_dat_i,
wb_dat_o => csr_dat_o,
wb_sel_o => csr_sel_o,
wb_cyc_o => csr_cyc_o,
wb_stb_o => csr_stb_o,
wb_we_o => csr_we_o,
wb_ack_i => csr_ack_i,
wb_stall_i => csr_stall_i
);
wb_adr_o <= wb_adr;
wb_dat_s2m <= wb_dat_i & wb_dat_s2m_dma_ctrl;
wb_dat_o <= wb_dat_m2s;
wb_sel_o <= wb_sel;
wb_cyc_o <= wb_cyc(g_CSR_WB_SLAVES_NB downto 1); -- wb_cyc(0) is for DMA controller
wb_stb_o <= wb_stb;
wb_we_o <= wb_we;
wb_ack <= wb_ack_i & wb_ack_dma_ctrl;
-- Adapt address bus width for top level
csr_adr_o <= '0' & csr_adr;
-----------------------------------------------------------------------------
-- DMA controller
......@@ -569,17 +559,20 @@ begin
next_item_attrib_i => next_item_attrib,
next_item_valid_i => next_item_valid,
wb_clk_i => wb_clk_i,
wb_adr_i => wb_adr(3 downto 0),
wb_dat_o => wb_dat_s2m_dma_ctrl,
wb_dat_i => wb_dat_m2s,
wb_sel_i => wb_sel,
wb_cyc_i => wb_cyc(0),
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_ack_o => wb_ack_dma_ctrl
wb_clk_i => dma_reg_clk_i,
wb_adr_i => dma_reg_adr_i(3 downto 0),
wb_dat_o => dma_reg_dat_o,
wb_dat_i => dma_reg_dat_i,
wb_sel_i => dma_reg_sel_i,
wb_cyc_i => dma_reg_cyc_i,
wb_stb_i => dma_reg_stb_i,
wb_we_i => dma_reg_we_i,
wb_ack_o => dma_reg_ack_o
);
-- DMA registers is a classic wishbone slave supporting single pipelined cycles
dma_reg_stall_o <= '0';
-- Status signals from DMA masters
dma_ctrl_done <= dma_ctrl_l2p_done or dma_ctrl_p2l_done;
dma_ctrl_error <= dma_ctrl_l2p_error or dma_ctrl_p2l_error;
......
hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd
View file @ c90f1f36
......@@ -149,12 +149,6 @@ package gn4124_core_pkg is
-----------------------------------------------------------------------------
component wbmaster32
generic
(
g_BAR0_APERTURE : integer := 20; -- BAR0 aperture, defined in GN4124 PCI_BAR_CONFIG register (0x80C)
-- => number of bits to address periph on the board
g_WB_SLAVES_NB : integer := 2
);
port
(
---------------------------------------------------------
......@@ -198,15 +192,16 @@ package gn4124_core_pkg is
---------------------------------------------------------
-- CSR wishbone interface
wb_clk_i : in std_logic; -- Wishbone bus clock
wb_adr_o : out std_logic_vector(g_BAR0_APERTURE-log2_ceil(g_WB_SLAVES_NB)-1 downto 0); -- Address
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic; -- Strobe
wb_we_o : out std_logic; -- Write
wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle
wb_dat_i : in std_logic_vector((32*g_WB_SLAVES_NB)-1 downto 0); -- Data in
wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Acknowledge
wb_clk_i : in std_logic; -- Wishbone bus clock
wb_adr_o : out std_logic_vector(30 downto 0); -- Address
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic; -- Strobe
wb_we_o : out std_logic; -- Write
wb_cyc_o : out std_logic; -- Cycle
wb_dat_i : in std_logic_vector(31 downto 0); -- Data in
wb_ack_i : in std_logic; -- Acknowledge
wb_stall_i : in std_logic -- Stall
);
end component; -- wbmaster32
......
hdl/gn4124core/rtl/wbmaster32.vhd
View file @ c90f1f36
......@@ -36,12 +36,6 @@ use work.genram_pkg.all;
entity wbmaster32 is
generic
(
g_BAR0_APERTURE : integer := 20; -- BAR0 aperture, defined in GN4124 PCI_BAR_CONFIG register (0x80C)
-- => number of bits to address periph on the board
g_WB_SLAVES_NB : integer := 2
);
port
(
---------------------------------------------------------
......@@ -86,15 +80,16 @@ entity wbmaster32 is
---------------------------------------------------------
-- CSR wishbone interface
wb_clk_i : in std_logic; -- Wishbone bus clock
wb_adr_o : out std_logic_vector(g_BAR0_APERTURE-log2_ceil(g_WB_SLAVES_NB)-1 downto 0); -- Address
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic; -- Strobe
wb_we_o : out std_logic; -- Write
wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle
wb_dat_i : in std_logic_vector((32*g_WB_SLAVES_NB)-1 downto 0); -- Data in
wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Acknowledge
wb_clk_i : in std_logic; -- Wishbone bus clock
wb_adr_o : out std_logic_vector(30 downto 0); -- Address
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic; -- Strobe
wb_we_o : out std_logic; -- Write
wb_cyc_o : out std_logic; -- Cycle
wb_dat_i : in std_logic_vector(31 downto 0); -- Data in
wb_ack_i : in std_logic; -- Acknowledge
wb_stall_i : in std_logic -- Stall
);
end wbmaster32;
......@@ -136,22 +131,15 @@ architecture behaviour of wbmaster32 is
type wishbone_state_type is (WB_IDLE, WB_READ_FIFO, WB_CYCLE, WB_WAIT_ACK);
signal wishbone_current_state : wishbone_state_type;
--signal s_wb_we : std_logic;
signal s_wb_periph_addr : std_logic_vector(log2_ceil(g_WB_SLAVES_NB)-1 downto 0);
signal wb_periph_addr : std_logic_vector(log2_ceil(g_WB_SLAVES_NB)-1 downto 0);
signal s_wb_periph_select : std_logic_vector((2**s_wb_periph_addr'length)-1 downto 0);
signal s_wb_ack_muxed : std_logic;
signal wb_ack_t : std_logic;
signal s_wb_dat_i_muxed : std_logic_vector(31 downto 0);
signal wb_dat_i_t : std_logic_vector(31 downto 0);
signal wb_cyc_t : std_logic;
signal s_wb_cyc_demuxed : std_logic_vector(g_WB_SLAVES_NB-1 downto 0);
signal wb_dat_o_t : std_logic_vector(31 downto 0);
signal wb_stb_t : std_logic;
signal wb_adr_t : std_logic_vector(30 downto 0);
signal wb_we_t : std_logic;
signal wb_sel_t : std_logic_vector(3 downto 0);
signal wb_ack_t : std_logic;
signal wb_dat_i_t : std_logic_vector(31 downto 0);
signal wb_cyc_t : std_logic;
signal wb_dat_o_t : std_logic_vector(31 downto 0);
signal wb_stb_t : std_logic;
signal wb_adr_t : std_logic_vector(30 downto 0);
signal wb_we_t : std_logic;
signal wb_sel_t : std_logic_vector(3 downto 0);
signal wb_stall_t : std_logic;
-- L2P packet generator
type l2p_read_cpl_state_type is (L2P_IDLE, L2P_HEADER, L2P_DATA);
......@@ -460,81 +448,15 @@ begin
end if;
end process p_wb_fsm;
------------------------------------------------------------------------------
-- Wishbone master address decoding
------------------------------------------------------------------------------
-- Take the first N bits of the address to select the active wb peripheral
-- g_BAR0_APERTURE represents byte address window, has to be shifted right by 2 to match wishbone 32-bit word addresses
s_wb_periph_addr <= wb_adr_t(g_BAR0_APERTURE-3 downto g_BAR0_APERTURE-log2_ceil(g_WB_SLAVES_NB)-2);
-----------------------------------------------------------------------------
-- One-hot decode function, s_wb_periph_select <= onehot_decode(s_wb_periph_addr);
-----------------------------------------------------------------------------
onehot_decode : process(s_wb_periph_addr)
variable v_onehot : std_logic_vector((2**s_wb_periph_addr'length)-1 downto 0);
variable v_index : integer range 0 to (2**s_wb_periph_addr'length)-1;
begin
v_onehot := (others => '0');
v_index := 0;
for i in s_wb_periph_addr'range loop
if (s_wb_periph_addr(i) = '1') then
v_index := 2*v_index+1;
else
v_index := 2*v_index;
end if;
end loop;
v_onehot(v_index) := '1';
s_wb_periph_select <= v_onehot;
end process onehot_decode;
-- Register multiplexed ack and data + periph address
p_wb_in_regs : process (wb_clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
wb_periph_addr <= (others => '0');
wb_dat_i_t <= (others => '0');
wb_ack_t <= '0';
elsif rising_edge(wb_clk_i) then
wb_periph_addr <= s_wb_periph_addr;
wb_dat_i_t <= s_wb_dat_i_muxed;
wb_ack_t <= s_wb_ack_muxed;
end if;
end process p_wb_in_regs;
-- Select ack line of the active peripheral
p_ack_mux : process (wb_ack_i, wb_periph_addr)
begin
if (to_integer(unsigned(wb_periph_addr)) < g_WB_SLAVES_NB) then
s_wb_ack_muxed <= wb_ack_i(to_integer(unsigned(wb_periph_addr)));
else
s_wb_ack_muxed <= '0';
end if;
end process p_ack_mux;
-- Select input data of the active peripheral
p_din_mux : process (wb_dat_i, wb_periph_addr)
begin
if (to_integer(unsigned(wb_periph_addr)) < g_WB_SLAVES_NB) then
s_wb_dat_i_muxed <=
wb_dat_i(31+(32*to_integer(unsigned(wb_periph_addr))) downto 32*to_integer(unsigned(wb_periph_addr)));
else
s_wb_dat_i_muxed <= (others => 'X');
end if;
end process p_din_mux;
-- Assert the cyc line of the selected peripheral
gen_cyc_demux : for i in 0 to g_WB_SLAVES_NB-1 generate
s_wb_cyc_demuxed(i) <= wb_cyc_t and s_wb_periph_select(i) and not(wb_ack_t);
end generate gen_cyc_demux;
-- Wishbone bus outputs
wb_dat_o <= wb_dat_o_t;
wb_stb_o <= wb_stb_t;
wb_we_o <= wb_we_t;
wb_adr_o <= wb_adr_t(g_BAR0_APERTURE-log2_ceil(g_WB_SLAVES_NB)-1 downto 0);
wb_sel_o <= wb_sel_t;
wb_cyc_o <= s_wb_cyc_demuxed;
wb_adr_o <= wb_adr_t;
wb_cyc_o <= wb_cyc_t;
wb_stb_o <= wb_stb_t;
wb_we_o <= wb_we_t;
wb_sel_o <= wb_sel_t;
wb_dat_i_t <= wb_dat_i;
wb_dat_o <= wb_dat_o_t;
wb_ack_t <= wb_ack_i;
wb_stall_t <= wb_stall_i;
end behaviour;
hdl/spec/rtl/Manifest.py
View file @ c90f1f36
files = ["spec_gn4124_test.vhd",]
files = ["spec_gn4124_test.vhd",
"wb_addr_decoder.vhd"]
modules = {"local" : ["../../common/rtl",
"../../gn4124core/rtl",
......
hdl/spec/rtl/spec_gn4124_test.vhd
View file @ c90f1f36
This diff is collapsed.
hdl/spec/rtl/wb_addr_decoder.vhd 0 → 100644
View file @ c90f1f36
--------------------------------------------------------------------------------
-- --
-- CERN BE-CO-HT GN4124 core for PCIe FMC carrier --
-- http://www.ohwr.org/projects/gn4124-core --
--------------------------------------------------------------------------------
--
-- unit name: wishbone address decoder
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 02-08-2011
--
-- version: 0.1
--
-- description: Provides a simple wishbone address decoder.
-- Splits the memory windows into equal parts.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- last changes:
--------------------------------------------------------------------------------
-- TODO:
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
entity wb_addr_decoder is
generic
(
g_WINDOW_SIZE : integer := 18; -- Number of bits to address periph on the board (32-bit word address)
g_WB_SLAVES_NB : integer := 2
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- wishbone master interface
wbm_adr_i : in std_logic_vector(31 downto 0); -- Address
wbm_dat_i : in std_logic_vector(31 downto 0); -- Data out
wbm_sel_i : in std_logic_vector(3 downto 0); -- Byte select
wbm_stb_i : in std_logic; -- Strobe
wbm_we_i : in std_logic; -- Write
wbm_cyc_i : in std_logic; -- Cycle
wbm_dat_o : out std_logic_vector(31 downto 0); -- Data in
wbm_ack_o : out std_logic; -- Acknowledge
wbm_stall_o : out std_logic; -- Stall
---------------------------------------------------------
-- wishbone slaves interface
wb_adr_o : out std_logic_vector(31 downto 0); -- Address
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic; -- Strobe
wb_we_o : out std_logic; -- Write
wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle
wb_dat_i : in std_logic_vector((32*g_WB_SLAVES_NB)-1 downto 0); -- Data in
wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Acknowledge
wb_stall_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Stall
);
end wb_addr_decoder;
architecture behaviour of wb_addr_decoder is
-----------------------------------------------------------------------------
-- Constants declaration
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Signals declaration
-----------------------------------------------------------------------------
-- Wishbone
signal s_wb_periph_addr : std_logic_vector(log2_ceil(g_WB_SLAVES_NB)-1 downto 0);
signal wb_periph_addr : std_logic_vector(log2_ceil(g_WB_SLAVES_NB)-1 downto 0);
signal s_wb_periph_select : std_logic_vector((2**s_wb_periph_addr'length)-1 downto 0);
signal s_wb_ack_muxed : std_logic;
signal wb_ack_t : std_logic;
signal s_wb_dat_i_muxed : std_logic_vector(31 downto 0);
signal s_wb_cyc_demuxed : std_logic_vector(g_WB_SLAVES_NB-1 downto 0);
signal wb_adr_t : std_logic_vector(g_WINDOW_SIZE-log2_ceil(g_WB_SLAVES_NB)-1 downto 0);
begin
------------------------------------------------------------------------------
-- Wishbone master address decoding
------------------------------------------------------------------------------
-- Take the first N bits of the address to select the active wb peripheral
-- g_WINDOW_SIZE represents 32-bit word address window
s_wb_periph_addr <= wbm_adr_i(g_WINDOW_SIZE-1 downto g_WINDOW_SIZE-log2_ceil(g_WB_SLAVES_NB));
-----------------------------------------------------------------------------
-- One-hot decode function, s_wb_periph_select <= onehot_decode(s_wb_periph_addr);
-----------------------------------------------------------------------------
onehot_decode : process(s_wb_periph_addr)
variable v_onehot : std_logic_vector((2**s_wb_periph_addr'length)-1 downto 0);
variable v_index : integer range 0 to (2**s_wb_periph_addr'length)-1;
begin
v_onehot := (others => '0');
v_index := 0;
for i in s_wb_periph_addr'range loop
if (s_wb_periph_addr(i) = '1') then
v_index := 2*v_index+1;
else
v_index := 2*v_index;
end if;
end loop;
v_onehot(v_index) := '1';
s_wb_periph_select <= v_onehot;
end process onehot_decode;
-- Register multiplexed ack and data + periph address
p_wb_in_regs : process (clk_i, rst_n_i)
begin
if (rst_n_i = c_RST_ACTIVE) then
wb_periph_addr <= (others => '0');
wbm_dat_o <= (others => '0');
wb_ack_t <= '0';
elsif rising_edge(clk_i) then
wb_periph_addr <= s_wb_periph_addr;
wbm_dat_o <= s_wb_dat_i_muxed;
wb_ack_t <= s_wb_ack_muxed;
end if;
end process p_wb_in_regs;
wbm_ack_o <= wb_ack_t;
-- Select ack line of the active peripheral
p_ack_mux : process (wb_ack_i, wb_periph_addr)
begin
if (to_integer(unsigned(wb_periph_addr)) < g_WB_SLAVES_NB) then
s_wb_ack_muxed <= wb_ack_i(to_integer(unsigned(wb_periph_addr)));
else
s_wb_ack_muxed <= '0';
end if;
end process p_ack_mux;
-- Select stall line of the active peripheral
p_stall_mux : process (wb_stall_i, wb_periph_addr)
begin
if (to_integer(unsigned(wb_periph_addr)) < g_WB_SLAVES_NB) then
wbm_stall_o <= wb_stall_i(to_integer(unsigned(wb_periph_addr)));
else
wbm_stall_o <= '0';
end if;
end process p_stall_mux;
-- Select input data of the active peripheral
p_din_mux : process (wb_dat_i, wb_periph_addr)
begin
if (to_integer(unsigned(wb_periph_addr)) < g_WB_SLAVES_NB) then
s_wb_dat_i_muxed <=
wb_dat_i(31+(32*to_integer(unsigned(wb_periph_addr))) downto 32*to_integer(unsigned(wb_periph_addr)));
else
s_wb_dat_i_muxed <= (others => 'X');
end if;
end process p_din_mux;
-- Assert the cyc line of the selected peripheral
gen_cyc_demux : for i in 0 to g_WB_SLAVES_NB-1 generate
s_wb_cyc_demuxed(i) <= wbm_cyc_i and s_wb_periph_select(i) and not(wb_ack_t);
end generate gen_cyc_demux;
-- Slaves wishbone bus outputs
wb_dat_o <= wbm_dat_i;
wb_stb_o <= wbm_stb_i;
wb_we_o <= wbm_we_i;
wb_sel_o <= wbm_sel_i;
wb_cyc_o <= s_wb_cyc_demuxed;
-- extend address bus to 32-bit
wb_adr_t <= wbm_adr_i(g_WINDOW_SIZE-log2_ceil(g_WB_SLAVES_NB)-1 downto 0);
wb_adr_o(wb_adr_t'left downto 0) <= wb_adr_t;
wb_adr_o(31 downto wb_adr_t'left+1) <= (others => '0');
end behaviour;
hdl/spec/syn/Makefile
View file @ c90f1f36
......@@ -12,6 +12,7 @@ local:
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
......@@ -32,6 +33,7 @@ CWD := $(shell pwd)
FILES := ../spec_gn4124_test.ucf \
../rtl/spec_gn4124_test.vhd \
../rtl/wb_addr_decoder.vhd \
../../common/rtl/dummy_ctrl_regs.vhd \
../../common/rtl/dummy_stat_regs.vhd \
../../gn4124core/rtl/dma_controller.vhd \
......@@ -209,7 +211,7 @@ __send:
rsync -Rav $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
__do_synthesis:
ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && /opt/Xilinx/12.2/ISE_DS/ISE/bin/lin64/xtclsh run.tcl'
ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && xtclsh run.tcl'
__send_back:
cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)$(CWD) . && cd $(CWD)
......
hdl/spec/syn/spec_gn4124_test.xise
View file @ c90f1f36
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