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Gennum GN4124 core
Commits
6269b8f0
Commit
6269b8f0
authored
Jul 29, 2011
by
Matthieu Cattin
Browse files
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Test with IODDR2 and BUFIO2.
parent
9d321167
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10 changed files
with
479 additions
and
235 deletions
+479
-235
Manifest.py
hdl/gn4124core/rtl/Manifest.py
+1
-1
Manifest.py
hdl/gn4124core/rtl/spartan3/Manifest.py
+1
-1
gn4124_core.vhd
hdl/gn4124core/rtl/spartan3/gn4124_core.vhd
+168
-69
gn4124_core_pkg.vhd
hdl/gn4124core/rtl/spartan3/gn4124_core_pkg.vhd
+13
-7
l2p_ser.vhd
hdl/gn4124core/rtl/spartan3/l2p_ser.vhd
+93
-40
p2l_des.vhd
hdl/gn4124core/rtl/spartan3/p2l_des.vhd
+77
-12
gn4124_core.vhd
hdl/gn4124core/rtl/spartan6/gn4124_core.vhd
+1
-0
spec_gn4124_test.vhd
hdl/spec/rtl/spec_gn4124_test.vhd
+44
-15
Makefile
hdl/spec/syn/Makefile
+4
-8
spec_gn4124_test.xise
hdl/spec/syn/spec_gn4124_test.xise
+77
-82
No files found.
hdl/gn4124core/rtl/Manifest.py
View file @
6269b8f0
...
...
@@ -6,7 +6,7 @@ files = ["dma_controller.vhd",
"p2l_dma_master.vhd"
,
"wbmaster32.vhd"
]
modules
=
{
"local"
:
"spartan
6
"
,
modules
=
{
"local"
:
"spartan
3
"
,
"git"
:
"git://ohwr.org/hdl-core-lib/general-cores.git"
}
fetchto
=
"../ip_cores"
...
...
hdl/gn4124core/rtl/spartan3/Manifest.py
View file @
6269b8f0
files
=
[
"gn4124_core.vhd"
,
"gn4124_core_p
rivate_p
kg.vhd"
,
"gn4124_core_pkg.vhd"
,
"l2p_ser.vhd"
,
"p2l_des.vhd"
]
hdl/gn4124core/rtl/spartan3/gn4124_core.vhd
View file @
6269b8f0
This diff is collapsed.
Click to expand it.
hdl/gn4124core/rtl/spartan3/gn4124_core_pkg.vhd
View file @
6269b8f0
...
...
@@ -60,9 +60,11 @@ package gn4124_core_pkg is
(
---------------------------------------------------------
-- Reset and clock
rst_n_i
:
in
std_logic
;
clk_p_i
:
in
std_logic
;
clk_n_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
clk_sys_n_i
:
in
std_logic
;
clk_p_i
:
in
std_logic
;
clk_n_i
:
in
std_logic
;
---------------------------------------------------------
-- P2L Clock Domain
...
...
@@ -133,9 +135,11 @@ package gn4124_core_pkg is
(
---------------------------------------------------------
-- ICLK Clock Domain Inputs
clk_p_i
:
in
std_logic
;
clk_n_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
clk_sys_n_i
:
in
std_logic
;
clk_p_i
:
in
std_logic
;
clk_n_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
l2p_valid_i
:
in
std_logic
;
l2p_dframe_i
:
in
std_logic
;
...
...
@@ -317,7 +321,8 @@ package gn4124_core_pkg is
l2p_dma_stb_o
:
out
std_logic
;
-- Read or write strobe
l2p_dma_we_o
:
out
std_logic
;
-- Write
l2p_dma_ack_i
:
in
std_logic
;
-- Acknowledge
l2p_dma_stall_i
:
in
std_logic
-- for pipelined Wishbone
l2p_dma_stall_i
:
in
std_logic
;
-- for pipelined Wishbone
p2l_dma_cyc_i
:
in
std_logic
-- P2L dma wb cycle (for bus arbitration)
);
end
component
;
-- l2p_dma_master
...
...
@@ -388,6 +393,7 @@ package gn4124_core_pkg is
p2l_dma_we_o
:
out
std_logic
;
-- Write
p2l_dma_ack_i
:
in
std_logic
;
-- Acknowledge
p2l_dma_stall_i
:
in
std_logic
;
-- for pipelined Wishbone
l2p_dma_cyc_i
:
in
std_logic
;
-- L2P dma wb cycle (for bus arbitration)
---------------------------------------------------------
-- From P2L DMA MASTER
...
...
hdl/gn4124core/rtl/spartan3/l2p_ser.vhd
View file @
6269b8f0
...
...
@@ -40,9 +40,11 @@ entity l2p_ser is
(
---------------------------------------------------------
-- Reset and clock
clk_p_i
:
in
std_logic
;
clk_n_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
clk_sys_n_i
:
in
std_logic
;
clk_p_i
:
in
std_logic
;
clk_n_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
---------------------------------------------------------
-- Serializer inputs
...
...
@@ -72,10 +74,13 @@ architecture rtl of l2p_ser is
signal
ff_rst
:
std_logic
;
-- SDR to DDR signals
signal
dframe_d
:
std_logic
;
signal
valid_d
:
std_logic
;
signal
data_d
:
std_logic_vector
(
l2p_data_i
'range
);
signal
l2p_clk_sdr
:
std_logic
;
signal
dframe_d
:
std_logic
;
signal
valid_d
:
std_logic
;
signal
data_d
:
std_logic_vector
(
l2p_data_i
'range
);
signal
l2p_dframe_buf
:
std_logic
;
signal
l2p_valid_buf
:
std_logic
;
signal
l2p_data_buf
:
std_logic_vector
(
l2p_data_i
'range
);
signal
l2p_clk_sdr
:
std_logic
;
begin
...
...
@@ -95,13 +100,13 @@ begin
-----------------------------------------------------------------------------
-- Re-allign data tightly for the positive clock edge
-----------------------------------------------------------------------------
process
(
clk_
p
_i
,
rst_n_i
)
process
(
clk_
sys
_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
c_RST_ACTIVE
)
then
dframe_d
<=
'0'
;
valid_d
<=
'0'
;
data_d
<=
(
others
=>
'0'
);
elsif
rising_edge
(
clk_
p
_i
)
then
elsif
rising_edge
(
clk_
sys
_i
)
then
dframe_d
<=
l2p_dframe_i
;
valid_d
<=
l2p_valid_i
;
data_d
<=
l2p_data_i
;
...
...
@@ -111,26 +116,69 @@ begin
------------------------------------------------------------------------------
-- Align control signals to the negative clock edge
------------------------------------------------------------------------------
process
(
clk_n_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
c_RST_ACTIVE
)
then
l2p_valid_o
<=
'0'
;
l2p_dframe_o
<=
'0'
;
elsif
rising_edge
(
clk_n_i
)
then
l2p_valid_o
<=
valid_d
;
l2p_dframe_o
<=
dframe_d
;
end
if
;
end
process
;
-- Spartan3 control signal generation
gen_ctl_s3
:
if
g_IS_SPARTAN6
=
false
generate
process
(
clk_n_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
c_RST_ACTIVE
)
then
l2p_valid_o
<=
'0'
;
l2p_dframe_o
<=
'0'
;
elsif
rising_edge
(
clk_n_i
)
then
l2p_valid_o
<=
valid_d
;
l2p_dframe_o
<=
dframe_d
;
end
if
;
end
process
;
end
generate
gen_ctl_s3
;
-- Spartan6 control signal generation
gen_ctl_s6
:
if
g_IS_SPARTAN6
=
true
generate
cmp_ddr_ff_valid
:
ODDR2
port
map
(
Q
=>
l2p_valid_buf
,
C0
=>
clk_p_i
,
C1
=>
clk_n_i
,
CE
=>
'1'
,
D0
=>
valid_d
,
D1
=>
valid_d
,
R
=>
ff_rst
,
S
=>
'0'
);
cmp_buf_valid
:
OBUF
port
map
(
O
=>
l2p_valid_o
,
I
=>
l2p_valid_buf
);
cmp_ddr_ff_dframe
:
ODDR2
port
map
(
Q
=>
l2p_dframe_buf
,
C0
=>
clk_p_i
,
C1
=>
clk_n_i
,
CE
=>
'1'
,
D0
=>
dframe_d
,
D1
=>
dframe_d
,
R
=>
ff_rst
,
S
=>
'0'
);
cmp_buf_dframe
:
OBUF
port
map
(
O
=>
l2p_dframe_o
,
I
=>
l2p_dframe_buf
);
end
generate
gen_ctl_s6
;
------------------------------------------------------------------------------
-- DDR FF instanciation for data
------------------------------------------------------------------------------
-- Spartan3 primitives instanciation
gen_
out_ddr_ff
:
if
g_IS_SPARTAN6
=
false
generate
gen_
data_s3
:
if
g_IS_SPARTAN6
=
false
generate
-- Data
DDROUT
:
for
i
in
0
to
15
generate
U
:
OFDDRRSE
gen_bits
:
for
i
in
0
to
15
generate
cmp_ddr_ff
:
OFDDRRSE
port
map
(
Q
=>
l2p_data_o
(
i
),
...
...
@@ -142,27 +190,32 @@ begin
R
=>
ff_rst
,
S
=>
'0'
);
end
generate
;
end
generate
gen_
out_ddr_ff
;
end
generate
gen_bits
;
end
generate
gen_
data_s3
;
-- Spartan6 primitives instanciation
gen_
out_ddr_ff
_s6
:
if
g_IS_SPARTAN6
=
true
generate
gen_
data
_s6
:
if
g_IS_SPARTAN6
=
true
generate
-- Data
DDROUT
:
for
i
in
0
to
15
generate
U
:
ODDR2
gen_bits
:
for
i
in
0
to
15
generate
cmp_ddr_ff
:
ODDR2
port
map
(
Q
=>
l2p_data_
o
(
i
),
C0
=>
clk_
n
_i
,
C1
=>
clk_
p
_i
,
Q
=>
l2p_data_
buf
(
i
),
C0
=>
clk_
p
_i
,
C1
=>
clk_
n
_i
,
CE
=>
'1'
,
D0
=>
data_d
(
i
),
D1
=>
data_d
(
i
+
16
),
R
=>
ff_rst
,
S
=>
'0'
);
end
generate
;
end
generate
gen_out_ddr_ff_s6
;
cmp_buf
:
OBUF
port
map
(
O
=>
l2p_data_o
(
i
),
I
=>
l2p_data_buf
(
i
)
);
end
generate
gen_bits
;
end
generate
gen_data_s6
;
------------------------------------------------------------------------------
-- DDR source synchronous clock generation
...
...
@@ -174,9 +227,9 @@ begin
I
=>
l2p_clk_sdr
);
-- Spartan3 primitives instanciation
gen_
l2p_clk_ddr_ff
:
if
g_IS_SPARTAN6
=
false
generate
gen_
clk_s3
:
if
g_IS_SPARTAN6
=
false
generate
-- L2P clock
L2P_CLK_int
:
FDDRRSE
cmp_ddr_ff
:
FDDRRSE
port
map
(
Q
=>
l2p_clk_sdr
,
C0
=>
clk_n_i
,
...
...
@@ -186,22 +239,22 @@ begin
D1
=>
'0'
,
R
=>
'0'
,
S
=>
'0'
);
end
generate
gen_
l2p_clk_ddr_ff
;
end
generate
gen_
clk_s3
;
-- Spartan6 primitives instanciation
gen_
l2p_clk_ddr_ff
_s6
:
if
g_IS_SPARTAN6
=
true
generate
gen_
clk
_s6
:
if
g_IS_SPARTAN6
=
true
generate
-- L2P clock
L2P_CLK_int
:
ODDR2
cmp_ddr_ff
:
ODDR2
port
map
(
Q
=>
l2p_clk_sdr
,
C0
=>
clk_
n
_i
,
C1
=>
clk_
p
_i
,
C0
=>
clk_
sys
_i
,
C1
=>
clk_
sys_n
_i
,
CE
=>
'1'
,
D0
=>
'1'
,
D1
=>
'0'
,
R
=>
'0'
,
S
=>
'0'
);
end
generate
gen_
l2p_clk_ddr_ff
_s6
;
end
generate
gen_
clk
_s6
;
end
rtl
;
...
...
hdl/gn4124core/rtl/spartan3/p2l_des.vhd
View file @
6269b8f0
...
...
@@ -39,9 +39,11 @@ entity p2l_des is
(
---------------------------------------------------------
-- Reset and clock
rst_n_i
:
in
std_logic
;
clk_p_i
:
in
std_logic
;
clk_n_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
clk_sys_n_i
:
in
std_logic
;
clk_p_i
:
in
std_logic
;
clk_n_i
:
in
std_logic
;
---------------------------------------------------------
-- P2L clock domain (DDR)
...
...
@@ -76,10 +78,13 @@ architecture rtl of p2l_des is
-- SDR signals
signal
p2l_valid_p
:
std_logic
;
signal
p2l_valid_n
:
std_logic
;
signal
p2l_valid_buf
:
std_logic
;
signal
p2l_dframe_p
:
std_logic
;
signal
p2l_dframe_n
:
std_logic
;
signal
p2l_dframe_buf
:
std_logic
;
signal
p2l_data_p
:
std_logic_vector
(
p2l_data_i
'range
);
signal
p2l_data_n
:
std_logic_vector
(
p2l_data_i
'range
);
signal
p2l_data_buf
:
std_logic_vector
(
p2l_data_i
'range
);
signal
p2l_data_sdr_l
:
std_logic_vector
(
p2l_data_i
'range
);
signal
p2l_data_sdr
:
std_logic_vector
(
p2l_data_i
'length
*
2-1
downto
0
);
...
...
@@ -104,7 +109,7 @@ begin
------------------------------------------------------------------------------
-- Spartan3 primitives instanciation
gen_in_
ddr_ff
:
if
g_IS_SPARTAN6
=
false
generate
gen_in_
s3
:
if
g_IS_SPARTAN6
=
false
generate
-- Data
DDRFF_D
:
for
i
in
p2l_data_i
'range
generate
U
:
IFDDRRSE
...
...
@@ -148,22 +153,82 @@ begin
R
=>
ff_rst
,
S
=>
'0'
);
end
generate
gen_in_
ddr_ff
;
end
generate
gen_in_
s3
;
-- Spartan6 primitives instanciation
gen_in_ddr_ff_s6
:
if
g_IS_SPARTAN6
=
true
generate
end
generate
gen_in_ddr_ff_s6
;
gen_in_s6
:
if
g_IS_SPARTAN6
=
true
generate
-- Data
gen_data
:
for
i
in
p2l_data_i
'range
generate
cmp_buf
:
IBUF
port
map
(
O
=>
p2l_data_buf
(
i
),
I
=>
p2l_data_i
(
i
)
);
cmp_ddr_ff
:
IDDR2
port
map
(
Q0
=>
p2l_data_n
(
i
),
Q1
=>
p2l_data_p
(
i
),
C0
=>
clk_n_i
,
C1
=>
clk_p_i
,
CE
=>
'1'
,
D
=>
p2l_data_buf
(
i
),
R
=>
ff_rst
,
S
=>
'0'
);
end
generate
gen_data
;
-- dframe
cmp_buf_dframe
:
IBUF
port
map
(
O
=>
p2l_dframe_buf
,
I
=>
p2l_dframe_i
);
cmp_ddr_ff_dframe
:
IDDR2
port
map
(
Q0
=>
p2l_dframe_n
,
Q1
=>
p2l_dframe_p
,
C0
=>
clk_n_i
,
C1
=>
clk_p_i
,
CE
=>
'1'
,
D
=>
p2l_dframe_buf
,
R
=>
ff_rst
,
S
=>
'0'
);
-- valid
cmp_buf_valid
:
IBUF
port
map
(
O
=>
p2l_valid_buf
,
I
=>
p2l_valid_i
);
cmp_ddr_ff_valid
:
IDDR2
port
map
(
Q0
=>
p2l_valid_n
,
Q1
=>
p2l_valid_p
,
C0
=>
clk_n_i
,
C1
=>
clk_p_i
,
CE
=>
'1'
,
D
=>
p2l_valid_buf
,
R
=>
ff_rst
,
S
=>
'0'
);
end
generate
gen_in_s6
;
-----------------------------------------------------------------------------
-- Align positive edge data to negative edge clock
-----------------------------------------------------------------------------
process
(
clk_n_i
,
rst_n_i
)
process
(
clk_
sys_
n_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
c_RST_ACTIVE
)
then
p2l_data_sdr_l
<=
(
others
=>
'0'
);
elsif
rising_edge
(
clk_n_i
)
then
elsif
rising_edge
(
clk_
sys_
n_i
)
then
p2l_data_sdr_l
<=
p2l_data_p
;
end
if
;
end
process
;
...
...
@@ -175,13 +240,13 @@ begin
-----------------------------------------------------------------------------
-- Final positive edge clock alignment
-----------------------------------------------------------------------------
process
(
clk_
p
_i
,
rst_n_i
)
process
(
clk_
sys
_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
c_RST_ACTIVE
)
then
p2l_valid_o
<=
'0'
;
p2l_dframe_o
<=
'0'
;
p2l_data_o
<=
(
others
=>
'0'
);
elsif
rising_edge
(
clk_
p
_i
)
then
elsif
rising_edge
(
clk_
sys
_i
)
then
p2l_valid_o
<=
p2l_valid_p
;
p2l_dframe_o
<=
p2l_dframe_p
;
p2l_data_o
<=
p2l_data_sdr
;
...
...
hdl/gn4124core/rtl/spartan6/gn4124_core.vhd
View file @
6269b8f0
...
...
@@ -40,6 +40,7 @@ use UNISIM.vcomponents.all;
--==============================================================================
entity
gn4124_core
is
generic
(
g_IS_SPARTAN6
:
boolean
:
=
false
;
-- This generic is used to instanciate spartan6 specific primitives
g_BAR0_APERTURE
:
integer
:
=
20
;
-- BAR0 aperture, defined in GN4124 PCI_BAR_CONFIG register (0x80C)
-- => number of bits to address periph on the board
g_CSR_WB_SLAVES_NB
:
integer
:
=
1
;
-- Number of CSR wishbone slaves
...
...
hdl/spec/rtl/spec_gn4124_test.vhd
View file @
6269b8f0
...
...
@@ -100,12 +100,12 @@ architecture rtl of spec_gn4124_test is
component
gn4124_core
generic
(
--
g_IS_SPARTAN6 : boolean := false; -- This generic is used to instanciate spartan6 specific primitives
g_BAR0_APERTURE
:
integer
:
=
20
;
-- BAR0 aperture, defined in GN4124 PCI_BAR_CONFIG register (0x80C)
-- => number of bits to address periph on the board
g_CSR_WB_SLAVES_NB
:
integer
:
=
1
;
-- Number of CSR wishbone slaves
g_DMA_WB_SLAVES_NB
:
integer
:
=
1
;
-- Number of DMA wishbone slaves
g_DMA_WB_ADDR_WIDTH
:
integer
:
=
26
-- DMA wishbone address bus width
g_IS_SPARTAN6
:
boolean
:
=
false
;
-- This generic is used to instanciate spartan6 specific primitives
g_BAR0_APERTURE
:
integer
:
=
20
;
-- BAR0 aperture, defined in GN4124 PCI_BAR_CONFIG register (0x80C)
-- => number of bits to address periph on the board
g_CSR_WB_SLAVES_NB
:
integer
:
=
1
;
-- Number of CSR wishbone slaves
g_DMA_WB_SLAVES_NB
:
integer
:
=
1
;
-- Number of DMA wishbone slaves
g_DMA_WB_ADDR_WIDTH
:
integer
:
=
26
-- DMA wishbone address bus width
);
port
(
...
...
@@ -287,8 +287,11 @@ architecture rtl of spec_gn4124_test is
signal
clk_div
:
std_logic
;
-- LED
signal
led_cnt
:
unsigned
(
24
downto
0
);
signal
led_en
:
std_logic
;
signal
led_cnt
:
unsigned
(
24
downto
0
);
signal
led_en
:
std_logic
;
signal
led_k2000
:
unsigned
(
2
downto
0
);
signal
led_pps
:
std_logic
;
signal
leds
:
std_logic_vector
(
3
downto
0
);
begin
...
...
@@ -313,7 +316,7 @@ begin
------------------------------------------------------------------------------
cmp_gn4124_core
:
gn4124_core
generic
map
(
--
g_IS_SPARTAN6 => true,
g_IS_SPARTAN6
=>
true
,
g_BAR0_APERTURE
=>
c_BAR0_APERTURE
,
g_CSR_WB_SLAVES_NB
=>
c_CSR_WB_SLAVES_NB
,
g_DMA_WB_SLAVES_NB
=>
c_DMA_WB_SLAVES_NB
,
...
...
@@ -513,17 +516,43 @@ begin
begin
if
L_RST_N
=
'0'
then
led_cnt
<=
(
others
=>
'1'
);
led_en
<=
'1'
;
led_en
<=
'1'
;
elsif
rising_edge
(
l_clk
)
then
led_cnt
<=
led_cnt
-
1
;
led_en
<=
led_cnt
(
24
);
led_en
<=
led_cnt
(
23
);
end
if
;
end
process
p_led_cnt
;
AUX_LEDS_O
(
0
)
<=
led_en
;
AUX_LEDS_O
(
1
)
<=
not
(
led_en
);
AUX_LEDS_O
(
2
)
<=
'1'
;
AUX_LEDS_O
(
3
)
<=
'0'
;
led_pps
<=
led_cnt
(
23
)
and
not
(
led_en
);
p_led_k2000
:
process
(
l_clk
,
L_RST_N
)
begin
if
L_RST_N
=
'0'
then
led_k2000
<=
(
others
=>
'0'
);
leds
<=
"0001"
;
elsif
rising_edge
(
l_clk
)
then
if
led_pps
=
'1'
then
if
led_k2000
(
2
)
=
'0'
then
if
leds
/=
"1000"
then
leds
<=
leds
(
2
downto
0
)
&
'0'
;
end
if
;
else
if
leds
/=
"0001"
then
leds
<=
'0'
&
leds
(
3
downto
1
);
end
if
;
end
if
;
led_k2000
<=
led_k2000
+
1
;
end
if
;
end
if
;
end
process
p_led_k2000
;
AUX_LEDS_O
<=
not
(
leds
);
--AUX_LEDS_O(0) <= led_en;
--AUX_LEDS_O(1) <= not(led_en);
--AUX_LEDS_O(2) <= '1';
--AUX_LEDS_O(3) <= '0';
end
rtl
;
...
...
hdl/spec/syn/Makefile
View file @
6269b8f0
...
...
@@ -41,14 +41,10 @@ FILES := ../spec_gn4124_test.ucf \
../../gn4124core/rtl/p2l_decode32.vhd
\
../../gn4124core/rtl/p2l_dma_master.vhd
\
../../gn4124core/rtl/wbmaster32.vhd
\
../../gn4124core/rtl/spartan6/gn4124_core.vhd
\
../../gn4124core/rtl/spartan6/gn4124_core_pkg.vhd
\
../../gn4124core/rtl/spartan6/l2p_ser.vhd
\
../../gn4124core/rtl/spartan6/p2l_des.vhd
\
../../gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd
\
../../gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd
\
../../gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd
\
../../gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd
\
../../gn4124core/rtl/spartan3/gn4124_core.vhd
\
../../gn4124core/rtl/spartan3/gn4124_core_pkg.vhd
\
../../gn4124core/rtl/spartan3/l2p_ser.vhd
\
../../gn4124core/rtl/spartan3/p2l_des.vhd
\
../../gn4124core/ip_cores/general-cores/modules/common/gencores_pkg.vhd
\
../../gn4124core/ip_cores/general-cores/modules/common/gc_crc_gen.vhd
\
../../gn4124core/ip_cores/general-cores/modules/common/gc_moving_average.vhd
\
...
...
hdl/spec/syn/spec_gn4124_test.xise
View file @
6269b8f0
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