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Gennum GN4124 core
Commit 9d321167 authored by Matthieu Cattin's avatar Matthieu Cattin
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Bug fix in P2L DMA master, for 1 word length read request last BE was set and it shouldn't

parent 9a3b4cd8
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Showing with 43 additions and 16 deletions
hdl/gn4124core/rtl/p2l_dma_master.vhd
View file @ 9d321167
......@@ -148,6 +148,7 @@ architecture behaviour of p2l_dma_master is
signal l2p_64b_address : std_logic;
signal s_l2p_header : std_logic_vector(31 downto 0);
signal l2p_last_packet : std_logic;
signal l2p_lbe_header : std_logic_vector(3 downto 0);
-- Target address counter
signal target_addr_cnt : unsigned(29 downto 0);
......@@ -255,10 +256,13 @@ begin
end if;
end process p_read_req;
-- Last Byte Enable must be "0000" when length = 1
l2p_lbe_header <= "0000" when l2p_len_header = 1 else "1111";
s_l2p_header <= "000" --> Traffic Class
& '0' --> Snoop
& "000" & l2p_64b_address --> Packet type = read request (32 or 64 bits)
& "1111" --> LBE (Last Byte Enable)
& l2p_lbe_header --> LBE (Last Byte Enable)
& "1111" --> FBE (First Byte Enable)
& "000" --> Reserved
& '0' --> VC (Virtual Channel)
......
hdl/spec/rtl/spec_gn4124_test.vhd
View file @ 9d321167
......@@ -81,6 +81,10 @@ entity spec_gn4124_test is
led_red_o : out std_logic;
led_green_o : out std_logic;
-- Auxiliary pins
AUX_LEDS_O : out std_logic_vector(3 downto 0);
AUX_BUTTONS_I : in std_logic_vector(1 downto 0);
-- PCB version
pcb_ver_i : in std_logic_vector(3 downto 0)
);
......@@ -96,7 +100,7 @@ architecture rtl of spec_gn4124_test is
component gn4124_core
generic(
g_IS_SPARTAN6 : boolean := false; -- This generic is used to instanciate spartan6 specific primitives
--g_IS_SPARTAN6 : boolean := false; -- This generic is used to instanciate spartan6 specific primitives
g_BAR0_APERTURE : integer := 20; -- BAR0 aperture, defined in GN4124 PCI_BAR_CONFIG register (0x80C)
-- => number of bits to address periph on the board
g_CSR_WB_SLAVES_NB : integer := 1; -- Number of CSR wishbone slaves
......@@ -282,6 +286,10 @@ architecture rtl of spec_gn4124_test is
signal clk_div_cnt : unsigned(3 downto 0);
signal clk_div : std_logic;
-- LED
signal led_cnt : unsigned(24 downto 0);
signal led_en : std_logic;
begin
......@@ -305,7 +313,7 @@ begin
------------------------------------------------------------------------------
cmp_gn4124_core : gn4124_core
generic map (
g_IS_SPARTAN6 => true,
--g_IS_SPARTAN6 => true,
g_BAR0_APERTURE => c_BAR0_APERTURE,
g_CSR_WB_SLAVES_NB => c_CSR_WB_SLAVES_NB,
g_DMA_WB_SLAVES_NB => c_DMA_WB_SLAVES_NB,
......@@ -501,6 +509,22 @@ begin
end process p_div_clk;
p_led_cnt : process (L_RST_N, l_clk)
begin
if L_RST_N = '0' then
led_cnt <= (others => '1');
led_en <= '1';
elsif rising_edge(l_clk) then
led_cnt <= led_cnt - 1;
led_en <= led_cnt(24);
end if;
end process p_led_cnt;
AUX_LEDS_O(0) <= led_en;
AUX_LEDS_O(1) <= not(led_en);
AUX_LEDS_O(2) <= '1';
AUX_LEDS_O(3) <= '0';
end rtl;
hdl/spec/spec_gn4124_test.ucf
View file @ 9d321167
......@@ -527,19 +527,18 @@ NET "pcb_ver_i[3]" IOSTANDARD = "LVCMOS15";
#----------------------------------------
# Buttons and LEDs
#----------------------------------------
#NET "AUX_PINS[0]" LOC = C22; # Button PB1
#NET "AUX_PINS[0]" IOSTANDARD = "LVCMOS18";
#NET "AUX_PINS[1]" LOC = D21; # Button PB2
#NET "AUX_PINS[1]" IOSTANDARD = "LVCMOS18";
#NET "AUX_PINS[2]" LOC = G19; # LED LD2
#NET "AUX_PINS[2]" IOSTANDARD = "LVCMOS18";
#NET "AUX_PINS[3]" LOC = F20; # LED LD3
#NET "AUX_PINS[3]" IOSTANDARD = "LVCMOS18";
#NET "AUX_PINS[4]" LOC = F18; # LED LD4
#NET "AUX_PINS[4]" IOSTANDARD = "LVCMOS18";
#NET "AUX_PINS[5]" LOC = C20; # LED LD5
#NET "AUX_PINS[5]" IOSTANDARD = "LVCMOS18";
NET "AUX_BUTTONS_I[0]" LOC = C22;
NET "AUX_BUTTONS_I[0]" IOSTANDARD = "LVCMOS18";
NET "AUX_BUTTONS_I[1]" LOC = D21;
NET "AUX_BUTTONS_I[1]" IOSTANDARD = "LVCMOS18";
NET "AUX_LEDS_O[0]" LOC = G19;
NET "AUX_LEDS_O[0]" IOSTANDARD = "LVCMOS18";
NET "AUX_LEDS_O[1]" LOC = F20;
NET "AUX_LEDS_O[1]" IOSTANDARD = "LVCMOS18";
NET "AUX_LEDS_O[2]" LOC = F18;
NET "AUX_LEDS_O[2]" IOSTANDARD = "LVCMOS18";
NET "AUX_LEDS_O[3]" LOC = C20;
NET "AUX_LEDS_O[3]" IOSTANDARD = "LVCMOS18";
#===============================================================================
......
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