example_tb: add a simpler multi access DMA transfer.

542aa7ea · Tristan Gingold · c211ed08 · 542aa7ea
Commit 542aa7ea authored Aug 30, 2019 by Tristan Gingold
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Showing with 53 additions and 23 deletions

main.sv hdl/sim/example_tb/main.sv +53 -23

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--- a/hdl/sim/example_tb/main.sv
+++ b/hdl/sim/example_tb/main.sv
@@ -136,10 +136,24 @@ module main;
      val_check("Memory read-back", addr, val, expected);
   endtask // reg_check
+   task check_irq_status;
+      //  Check irq status
+      reg_check('h04, 'h04);
+      if (dma_irq != 1'b1)
+        $fatal(1, "dma irq should be 1");
+   endtask
+   task clear_irq;
+      acc.write('h04, 'h04);
+      reg_check('h04, 'h00);
+      if (dma_irq != 1'b0)
+        $fatal(1, "dma irq should be 0");
+   endtask
   initial begin
      automatic int ntest = 1;
-      const     int tests = 6;
+      const     int tests = 7;
      uint32_t addr, val, expected;
@@ -226,10 +240,7 @@ module main;
      @(posedge dma_irq);
-      //  Check irq status
+      check_irq_status;
-      reg_check('h04, 'h04);
-      if (dma_irq != 1'b1)
-        $fatal(1, "dma irq should be 1");
      for (addr = 'h00; addr < 'h20; addr += 1)
        begin
@@ -238,23 +249,48 @@ module main;
           mem_check('h100 + 4 * addr, expected);
        end
-      // clear irq
+      clear_irq;
-      acc.write('h04, 'h04);
-      reg_check('h04, 'h00);
+      repeat(4) @(posedge clk_125m);
-      if (dma_irq != 1'b0)
-        $fatal(1, "dma irq should be 0");
+      $write("PASS\n");
+      // ---------------------------------
+      $write("Test %0d/%0d: 128 reads over DMA: ",
+             ntest++, tests);
+      // Setup DMA
+      acc.write('h14, 'h100); // count
+      acc.write('h20, 'h00); // attrib
+      acc.write('h0c, 'h20000000); // hstartL
+      acc.write('h10, 'h00000000); // hstartH
+      acc.write('h00, 'h01); // start
+      @(posedge dma_irq);
+      check_irq_status;
+      for (addr = 'h00; addr < 'h40; addr += 1)
+        begin
+           expected = 32'h80000000 + 'h20 - addr - 1;
+           mem_check(4 * addr, expected);
+        end
+      clear_irq;
      repeat(4) @(posedge clk_125m);
      $write("PASS\n");
      // Check all four byte swap settings
+      // ---------------------------------
      for (int i = 0; i < 4; i++) begin
-         $write("Test %0d/%0d: 32 reads over DMA (byte swap = %0d): ",
+         $write("Test %0d/%0d: 16KB reads over DMA (byte swap = %0d): ",
                ntest++, tests, i);
         // Restart
-         acc.write('h14, 'h1000); // count
+         acc.write('h14, 'h4000); // count
         acc.write('h20, 'h00); // attrib
         acc.write('h0c, 'h20000000 + i * 'h1000); // hstartL
         acc.write('h10, 'h00000000); // hstartH
@@ -262,32 +298,26 @@ module main;
         @(posedge dma_irq);
-         //  Check irq status
+         check_irq_status;
-         reg_check('h04, 'h04);
-         if (dma_irq != 1'b1)
-           $fatal(1, "dma irq should be 1");
-         for (addr = 'h00; addr < 'h400; addr += 1)
+         for (addr = 'h00; addr < 'h1000; addr += 1)
           begin
              expected = 32'h80000000 + 'h20 - (addr % 'h20) - 1;
+              $write("ex: %x", expected);
              if (i == 1)
                expected = {<<8{expected}};
              else if (i == 2)
                expected = {<<16{expected}};
              else if (i == 3)
                expected = {<<16{{<<8{expected}}}};
+              $display("ex: %x", expected);
              mem_check((i * 'h1000) + 4 * addr, expected);
           end
-         // clear irq
+         clear_irq;
-         acc.write('h04, 'h04);
-         reg_check('h04, 'h00);
-         if (dma_irq != 1'b0)
-           $fatal(1, "dma irq should be 0");
         repeat(4) @(posedge clk_125m);
         $write("PASS\n");
         #1us;