One function operates with the default_word input
as a std_logic_vector, while the other operates with
default_word as an std_ulogic_vector.

This change prevents compilation issues when targeting STD 08.

See wr-cores#101 for more info

There are three functions with the same name.
This commit writes a different name for each function.

If the address input of the function is std_logic_vector the function name is not renamed.

If the address input of the function is std_ulogic_vector the function name is renamed to:
address_trans_u

If the address input of the function is bit_vector the function name is renamed to:
address_trans_b

See wr-cores#101 for more info

This is because since the VHDL 2008 standard the word “default” is a reserved word.

See wr-cores#101 for more info

Also fix some typos.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>