Commits · d34e800c01c8a638d68097b3dfa3a870f187792f · Projects / Gennum GN4124 core · GitLab

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Nov 04, 2020
- gn412x_bfm: work arounds for issues in questa sim. · d34e800c
  Tristan Gingold authored 4 years ago
```
Also fix some typos.
```
  d34e800c
- gn412x_bfm: remove unused signals/variables. · c5520d7a
  Tristan Gingold authored 4 years ago
  
  c5520d7a
Jul 24, 2020
- hdl: fix bug in BFM not accepting 4096B writes · f1e9a982
  Dimitris Lampridis authored 4 years ago
```
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
```
  f1e9a982
- hdl: fix bug in BFM not respecting P2L_RDY during DMA writes · 4f56571d
  Dimitris Lampridis authored 4 years ago
```
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
```
  4f56571d
Aug 29, 2019
- [sim] update BFM and testbench to be able to do proper DMA reads/writes · d601caf2
  Dimitris Lampridis authored 5 years ago and Tristan Gingold committed 5 years ago
  
  d601caf2
Aug 06, 2019
- [hdl] sanitise folder structure · 352c0db5
  Dimitris Lampridis authored 5 years ago
  
  352c0db5
Mar 14, 2019
- sim: add flow control to the write buffer of the BFM to prevent overflows during 'wr' commands · f5b49ca3
  Dimitris Lampridis authored 6 years ago
  
  f5b49ca3
Oct 26, 2018
- sim: Fix Modelsim warnings · 5066970c
  Dimitris Lampridis authored 6 years ago
  
  5066970c
Dec 14, 2017
- sim: VHDL BFM do not wait on RD_BUFFER (temporary workaround, to be confirmed) · 9b9625bb
  Dimitris Lampridis authored 7 years ago
  
  btrain-v2.5
  
  9b9625bb
Apr 27, 2017
- sim: VHDL BFM do not wait on RD_BUFFER (temporary workaround, to be confirmed) · 2710742b
  Dimitris Lampridis authored 7 years ago
  
  2710742b
May 19, 2015
- sim: added SystemVerilog BFM · ffea5479
  Tomasz Wlostowski authored 9 years ago
  
  ffea5479