[hdl] cleanup L2P DMA WB master logic

hdl/rtl/l2p_dma_master.vhd

@@ -89,6 +89,10 @@ architecture behavioral of l2p_dma_master is
     constant c_L2P_MAX_PAYLOAD : integer := 32;
     constant c_TIMEOUT         : integer := 2000;
 
+    -- how many pending WB requests to allow without ACK
+    constant c_L2P_WB_THROTTLE_THRESHOLD : integer :=
+      g_DATA_FIFO_FULL_SIZE - g_DATA_FIFO_FULL_THRES;
+
     ---------------------
     -- Signals
     ---------------------
@@ -98,11 +102,9 @@ architecture behavioral of l2p_dma_master is
 
     -- Data FIFO
     signal data_fifo_rd    : std_logic;
-    signal data_fifo_wr    : std_logic;
     signal data_fifo_empty : std_logic;
     signal data_fifo_full  : std_logic;
     signal data_fifo_dout  : std_logic_vector(31 downto 0);
-    signal data_fifo_din   : std_logic_vector(31 downto 0) := x"DEADBABE";
 
     -- Addr FIFO
     signal addr_fifo_rd    : std_logic;
@@ -138,10 +140,9 @@ architecture behavioral of l2p_dma_master is
     signal l2p_timeout_cnt : unsigned(12 downto 0)         := (others => '0');
 
     -- Wishbone
-    signal l2p_dma_cyc_t : std_logic;
     signal l2p_dma_stb_t : std_logic;
-    signal l2p_dma_adr_t : std_logic_vector(31 downto 0) := (others => '0');
-    signal wb_read_cnt   : unsigned(12 downto 0);
+    signal l2p_throttle  : std_logic;
+    signal wb_read_cnt   : unsigned(log2_ceil(c_L2P_WB_THROTTLE_THRESHOLD)-1 downto 0);
 
 begin
     ------------------------------
@@ -407,67 +408,42 @@ begin
     -- Wishbone Master
     ---------------------
     -- Tie offs
-    l2p_dma_cyc_o <= l2p_dma_cyc_t;
+    l2p_dma_cyc_o <= '1';
     l2p_dma_stb_o <= l2p_dma_stb_t;
     l2p_dma_sel_o <= (others => '1');
-    l2p_dma_adr_o <= l2p_dma_adr_t;
+    l2p_dma_adr_o <= addr_fifo_dout;
     l2p_dma_dat_o <= (others => '0');
     l2p_dma_we_o  <= '0';
 
-    addr_fifo_valid <= not(addr_fifo_empty or l2p_dma_stall_i or data_fifo_full);
-    l2p_dma_adr_t   <= addr_fifo_dout;
-    l2p_dma_stb_t   <= addr_fifo_rd and not addr_fifo_empty;
+    -- fetch new data when:
+    -- a) there is a new request in addr_fifo
+    -- b) there is enough space to store it in data_fifo
+    -- c) there aren't too many pending WB transactions to flood the data_fifo
+    l2p_dma_stb_t <= not(addr_fifo_empty or data_fifo_full or l2p_throttle);
+
+    addr_fifo_rd  <= l2p_dma_stb_t and not l2p_dma_stall_i;
 
     p_wb_master : process (l2p_dma_clk_i)
     begin
       if rising_edge(l2p_dma_clk_i) then
         if wb_fifo_rst_n = '0' then
-          l2p_dma_cyc_t <= '0';
-          addr_fifo_rd  <= '0';
-          wb_read_cnt   <= (others => '0');
-
+          wb_read_cnt  <= (others => '0');
+          l2p_throttle <= '0';
         else
-          l2p_dma_adr_t <= addr_fifo_dout;
-
-          if (addr_fifo_valid = '1') then
-            addr_fifo_rd <= '1';
-          else
-            addr_fifo_rd <= '0';
-          end if;
-
           if (l2p_dma_stb_t = '1' and l2p_dma_ack_i = '0') then
             wb_read_cnt <= wb_read_cnt + 1;
           elsif (l2p_dma_stb_t = '0' and l2p_dma_ack_i = '1') then
             wb_read_cnt <= wb_read_cnt - 1;
           end if;
 
-          if (addr_fifo_valid = '1') then
-            l2p_dma_cyc_t <= '1';
-          elsif (wb_read_cnt = 0) then
-            l2p_dma_cyc_t <= '0';
-          end if;
-
-        end if;
-      end if;
-    end process p_wb_master;
-
-    -- Receive data
-    data_rec_proc : process(l2p_dma_clk_i)
-    begin
-      if rising_edge(l2p_dma_clk_i) then
-        if wb_fifo_rst_n = '0' then
-          data_fifo_wr  <= '0';
-        else
-          if (l2p_dma_cyc_t = '1') then
-            data_fifo_din <= l2p_dma_dat_i;
-            data_fifo_wr  <= l2p_dma_ack_i;
+          if wb_read_cnt > c_L2P_WB_THROTTLE_THRESHOLD then
+            l2p_throttle <= '1';
           else
-            data_fifo_din <= x"BABEDEAD";
-            data_fifo_wr  <= '0';
+            l2p_throttle <= '0';
           end if;
         end if;
       end if;
-    end process data_rec_proc;
+    end process p_wb_master;
 
     ---------------------
     -- FIFOs
@@ -506,8 +482,8 @@ begin
       port map (
         rst_wr_n_i        => wb_fifo_rst_n,
         clk_wr_i          => l2p_dma_clk_i,
-        d_i               => data_fifo_din,
-        we_i              => data_fifo_wr,
+        d_i               => l2p_dma_dat_i,
+        we_i              => l2p_dma_ack_i,
         wr_almost_full_o  => data_fifo_full,
         rst_rd_n_i        => fifo_rst_n,
         clk_rd_i          => clk_i,