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Created with Raphaël 2.2.014Feb29Jan2Oct123Sep7Dec20Nov1527Oct24Jul29Jun3Nov28May29Apr13Nov954329Oct12929Sep27Jul244Sep330Aug2928238765117Jul1620May630Apr261214Mar13Feb30Jan29282329Nov26Oct17Sep30Aug13Jun826Mar201914Dec22Aug27Apr1231May18Mar16Sep1Jul30Jun2319May16Mar5Sep10Jun3Apr20Mar31Jan1Mar19Nov5Oct6Feb6Jan6Dec522Nov12Aug93229Jul2625118729Jun13Apr24Mar24Feb3231Jan281110Dec829Nov2619171211854329Oct2725212019765130Sep29272423212087632131Aug26131229Jul2720137628Jun2132128May2721429AprDefine two separate functions for SRAM_InitializemastermasterReneame the address_trans functionsRewrite the word default to default_valUpdate .ohwr.yamlUpdate .ohwr.yamlUpdate .ohwr.yamladd a component to insert a axi pipeline stage under control of a generic.ltgt_add_axi4_s…ltgt_add_axi4_slaveMerge branch '5-release-v3-1-2' into 'master'update changelogv3.1.2v3.1.2Merge branch '4-simplify-l2p_dma_master-fifo-reset-logic' into 'master'hdl: simplify l2p_dma_master fifo reset logicMerge branch '3-timing-issues-related-to-l2p_arbiter-outputs' into 'master'hdl: relax timing for l2p_arbiter outputsMerge branch 'release-v311' into 'master'Fix component, create releasev3.1.1v3.1.1Add AXI4 slave RTL and testbenchbugfix WB_DMA wr->RD wishbone bus turnarrounf bug.ltgt_wb_dma_wr_…ltgt_wb_dma_wr_turnarround_bugfixAdd testcase for DMA R2W anw W2R bus turnarrounds.Relax timing pressure on dma_ctrl_directionAdd missing CHANGELOG pointv3.1.0v3.1.0Add CHANGELOG entry for 3.1.0sim: modify testbench to test long p2l dma transfers.p2l_dma_master: allow transfer longer than 4096 bytes.p2l_dma_master: more refactoringp2l_dma_master: refactoringgn412x_bfm: add labels to processes.gn412x_bfm: remove unused code.gn412x_bfm: work arounds for issues in questa sim.gn412x_bfm: remove unused signals/variables.l2p_dma_master: add a commentl2p_dma_master.vhd: do not cross 4KB page boundaryl2p_dma_master: simplify the FSMAdd a commentl2p_dma_master: minor simplification.dma_controller.vhd: remove one state, clarify the codep2l_dma_master: refactoring.p2l_dma_master: fix incorrect handling of stall signal.Merge tag 'v3.0.1' into proposed_masterMerge branch 'release/3.0.1'v3.0.1v3.0.1bld: update changelog