[hdl] fix bug in new dma_controller where the DMA status was not properly...

[hdl] fix bug in new dma_controller where the DMA status was not properly exposed through the WB registers

hdl/rtl/dma_controller.vhd

@@ -81,10 +81,10 @@ end dma_controller;
 architecture behaviour of dma_controller is
 
   --  Values for the STAT register
-  constant c_IDLE  : std_logic_vector(1 downto 0) := "00";
-  constant c_BUSY  : std_logic_vector(1 downto 0) := "01";
-  constant c_ERROR : std_logic_vector(1 downto 0) := "10";
-  constant c_ABORT : std_logic_vector(1 downto 0) := "11";
+  constant c_DMA_STAT_IDLE  : std_logic_vector(1 downto 0) := "00";
+  constant c_DMA_STAT_BUSY  : std_logic_vector(1 downto 0) := "01";
+  constant c_DMA_STAT_ERROR : std_logic_vector(1 downto 0) := "10";
+  constant c_DMA_STAT_ABORT : std_logic_vector(1 downto 0) := "11";
 
   -- DMA controller registers
   signal dma_ctrl_start_wb : std_logic;
@@ -105,7 +105,6 @@ architecture behaviour of dma_controller is
   signal dma_attrib_chain  : std_logic;
   signal dma_attrib_dir    : std_logic;
 
-  signal dma_stat_reg    : std_logic_vector(1 downto 0);
   signal dma_stat_irq_i_wb    : std_logic;
   signal dma_stat_irq_o_wb    : std_logic;
   signal dma_stat_status_wb   : std_logic_vector(1 downto 0);
@@ -131,8 +130,8 @@ architecture behaviour of dma_controller is
   signal dma_ctrl_current_state : dma_ctrl_state_type;
 
   -- status signals
-  signal dma_status    : std_logic_vector(1 downto 0);
-  signal dma_irq_reg   : std_logic;
+  signal dma_stat_reg : std_logic_vector(1 downto 0);
+  signal dma_irq_reg  : std_logic;
 
   attribute keep: string;
   attribute keep of dma_cstart, dma_hstartl, dma_hstarth, dma_len,
@@ -249,11 +248,10 @@ begin
         dma_ctrl_start_l2p_o    <= '0';
         dma_ctrl_start_p2l_o    <= '0';
         dma_ctrl_start_next_o   <= '0';
-        dma_status              <= c_IDLE;
-        dma_irq_reg             <= '0';
         dma_ctrl_abort_o        <= '0';
 
-        dma_stat_reg     <= (others => '0');
+        dma_stat_reg     <= c_DMA_STAT_IDLE;
+        dma_irq_reg      <= '0';
         dma_cstart_reg   <= (others => '0');
         dma_hstartl_reg  <= (others => '0');
         dma_hstarth_reg  <= (others => '0');
@@ -295,7 +293,7 @@ begin
             if (unsigned(dma_len_reg(31 downto 2)) = 0) then
               -- Requesting a DMA of 0 word length gives a error
               dma_irq_reg      <= '1';
-              dma_status       <= c_ERROR;
+              dma_stat_reg     <= c_DMA_STAT_ERROR;
               dma_ctrl_current_state <= DMA_IDLE;
             else
               -- Start the DMA if the length is not 0
@@ -307,7 +305,7 @@ begin
                 dma_ctrl_start_p2l_o <= '1';
               end if;
               dma_ctrl_current_state <= DMA_TRANSFER;
-              dma_status             <= c_BUSY;
+              dma_stat_reg           <= c_DMA_STAT_BUSY;
             end if;
 
           when DMA_TRANSFER =>
@@ -317,13 +315,13 @@ begin
 
             if (dma_ctrl_abort and dma_ctrl_wr) = '1' then
               -- Transfer aborted
-              dma_status       <= c_ABORT;
+              dma_stat_reg     <= c_DMA_STAT_ABORT;
               dma_ctrl_abort_o <= '1';
               dma_ctrl_current_state <= DMA_IDLE;
             elsif dma_ctrl_error_i = '1' then
               -- An error occurs !
               dma_irq_reg      <= '1';
-              dma_status       <= c_ERROR;
+              dma_stat_reg     <= c_DMA_STAT_ERROR;
               dma_ctrl_current_state <= DMA_IDLE;
             elsif dma_ctrl_done_i = '1' then
               -- End of DMA transfer
@@ -332,7 +330,7 @@ begin
                 dma_ctrl_current_state <= DMA_START_CHAIN;
               else
                 -- Was the last transfer
-                dma_status             <= c_IDLE;
+                dma_stat_reg           <= c_DMA_STAT_IDLE;
                 dma_irq_reg            <= '1';
                 dma_ctrl_current_state <= DMA_IDLE;
               end if;
@@ -352,13 +350,13 @@ begin
 
             if (dma_ctrl_abort and dma_ctrl_wr) = '1' then
               -- Transfer aborted
-              dma_status       <= c_ABORT;
+              dma_stat_reg     <= c_DMA_STAT_ABORT;
               dma_ctrl_abort_o <= '1';
               dma_ctrl_current_state <= DMA_IDLE;
             elsif dma_ctrl_error_i = '1' then
               -- An error occurs !
               dma_irq_reg      <= '1';
-              dma_status       <= c_ERROR;
+              dma_stat_reg     <= c_DMA_STAT_ERROR;
               dma_ctrl_current_state <= DMA_IDLE;
             elsif next_item_valid_i = '1' then
               --  Capture parameters