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Commit 726ed8f8 authored by Matthieu Cattin's avatar Matthieu Cattin
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Modify CSR wishbone master to make it more generic (number of slaves, BAR0 apreture). 

Add 2 wishbone slave on CSR bus;
Dummy_stat_regs with fixed values and the DEBUG switch state.
Dummy_ctrl_regs with r/w regs and LEDs control.
parent 36078cbb
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hdl/gn4124core/design/rtl/gn4124_core.vhd
+ 9
− 9
View file @ 726ed8f8
......@@ -19,12 +19,11 @@
-- dependencies:
--
--------------------------------------------------------------------------------
-- last changes: 23-09-2010 (mcattin)
-- last changes: see svn log
--------------------------------------------------------------------------------
-- TODO: - DMA wishbone bus address map
-- - reset and clock signals
-- - wishbone timeout generic
-- - rename component instance -> cmp_xxx
-- - wishbone timeout generic ??
--------------------------------------------------------------------------------
library IEEE;
......@@ -41,8 +40,9 @@ use UNISIM.vcomponents.all;
--==============================================================================
entity gn4124_core is
generic(
g_BAR0_APERTURE : integer := 20; -- BAR0 aperture, defined in GN4124 PCI_BAR_CONFIG register (0x80C)
-- => number of bits to address periph on the board
g_CSR_WB_SLAVES_NB : integer := 1; -- Number of CSR wishbone slaves
g_CSR_WB_ADDR_WIDTH : integer := 27; -- CSR wishbone address bus width
g_DMA_WB_SLAVES_NB : integer := 1; -- Number of DMA wishbone slaves
g_DMA_WB_ADDR_WIDTH : integer := 26 -- DMA wishbone address bus width
);
......@@ -66,7 +66,7 @@ entity gn4124_core is
p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
rx_error_o : out std_logic; -- Receive Error
vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready
vc_rdy_i : in std_logic_vector(1 downto 0); -- Virtual channel ready
---------------------------------------------------------
-- L2P Direction
......@@ -93,7 +93,7 @@ entity gn4124_core is
---------------------------------------------------------
-- Target interface (CSR wishbone master)
wb_clk_i : in std_logic;
wb_adr_o : out std_logic_vector(g_CSR_WB_ADDR_WIDTH-1 downto 0);
wb_adr_o : out std_logic_vector(g_BAR0_APERTURE-log2_ceil(g_CSR_WB_SLAVES_NB+1)-1 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic;
......@@ -242,7 +242,7 @@ architecture rtl of gn4124_core is
------------------------------------------------------------------------------
-- CSR wishbone bus
------------------------------------------------------------------------------
signal wb_adr : std_logic_vector(g_CSR_WB_ADDR_WIDTH-1 downto 0);
signal wb_adr : std_logic_vector(g_BAR0_APERTURE-log2_ceil(g_CSR_WB_SLAVES_NB+1)-1 downto 0);
signal wb_dat_s2m : std_logic_vector((32*(g_CSR_WB_SLAVES_NB+1))-1 downto 0);
signal wb_dat_m2s : std_logic_vector(31 downto 0);
signal wb_sel : std_logic_vector(3 downto 0);
......@@ -424,8 +424,8 @@ begin
cmp_wbmaster32 : wbmaster32
generic map
(
g_WB_SLAVES_NB => (g_CSR_WB_SLAVES_NB + 1), -- +1 for the DMA controller (wb slave always present)
g_WB_ADDR_WIDTH => g_CSR_WB_ADDR_WIDTH
g_BAR0_APERTURE => g_BAR0_APERTURE,
g_WB_SLAVES_NB => (g_CSR_WB_SLAVES_NB + 1) -- +1 for the DMA controller (wb slave always present)
)
port map
(
......
hdl/gn4124core/design/rtl/gn4124_core_pkg.vhd
+ 25
− 11
View file @ 726ed8f8
......@@ -45,6 +45,7 @@ package gn4124_core_pkg is
signal byte_swap : std_logic_vector(1 downto 0))
return std_logic_vector;
function log2_ceil(N : natural) return positive;
--==============================================================================
--! Components declaration
......@@ -153,8 +154,9 @@ package gn4124_core_pkg is
-----------------------------------------------------------------------------
generic
(
g_WB_SLAVES_NB : integer := 2;
g_WB_ADDR_WIDTH : integer := 27
g_BAR0_APERTURE : integer := 20; -- BAR0 aperture, defined in GN4124 PCI_BAR_CONFIG register (0x80C)
-- => number of bits to address periph on the board
g_WB_SLAVES_NB : integer := 2
);
port
(
......@@ -199,15 +201,15 @@ package gn4124_core_pkg is
---------------------------------------------------------
-- CSR wishbone interface
wb_clk_i : in std_logic; -- Wishbone bus clock
wb_adr_o : out std_logic_vector(g_WB_ADDR_WIDTH-1 downto 0); -- Address
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic; -- Strobe
wb_we_o : out std_logic; -- Write
wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle
wb_dat_i : in std_logic_vector((32*g_WB_SLAVES_NB)-1 downto 0); -- Data in
wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Acknowledge
wb_clk_i : in std_logic; -- Wishbone bus clock
wb_adr_o : out std_logic_vector(g_BAR0_APERTURE-log2_ceil(g_WB_SLAVES_NB)-1 downto 0); -- Address
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic; -- Strobe
wb_we_o : out std_logic; -- Write
wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle
wb_dat_i : in std_logic_vector((32*g_WB_SLAVES_NB)-1 downto 0); -- Data in
wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Acknowledge
);
end component; -- wbmaster32
......@@ -528,4 +530,16 @@ package body gn4124_core_pkg is
return dout;
end function f_byte_swap;
-----------------------------------------------------------------------------
-- Returns log of 2 of a natural number
-----------------------------------------------------------------------------
function log2_ceil(N : natural) return positive is
begin
if N < 2 then
return 1;
else
return 1 + log2_ceil(N/2);
end if;
end;
end gn4124_core_pkg;
hdl/gn4124core/design/rtl/gullwing_wrapper.vhd
+ 109
− 23
View file @ 726ed8f8
......@@ -27,6 +27,7 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
......@@ -160,8 +161,9 @@ architecture rtl of gw_wrapper is
component gn4124_core
generic(
g_BAR0_APERTURE : integer := 20; -- BAR0 aperture, defined in GN4124 PCI_BAR_CONFIG register (0x80C)
-- => number of bits to address periph on the board
g_CSR_WB_SLAVES_NB : integer := 1; -- Number of CSR wishbone slaves
g_CSR_WB_ADDR_WIDTH : integer := 27; -- CSR wishbone address bus width
g_DMA_WB_SLAVES_NB : integer := 1; -- Number of DMA wishbone slaves
g_DMA_WB_ADDR_WIDTH : integer := 26 -- DMA wishbone address bus width
);
......@@ -212,7 +214,7 @@ architecture rtl of gw_wrapper is
---------------------------------------------------------
-- Target interface (CSR wishbone master)
wb_clk_i : in std_logic;
wb_adr_o : out std_logic_vector(g_CSR_WB_ADDR_WIDTH-1 downto 0);
wb_adr_o : out std_logic_vector(g_BAR0_APERTURE-log2_ceil(g_CSR_WB_SLAVES_NB+1)-1 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic;
......@@ -236,6 +238,43 @@ architecture rtl of gw_wrapper is
);
end component; -- gn4124_core
component dummy_stat_regs_wb_slave
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
dummy_stat_reg_1_i : in std_logic_vector(31 downto 0);
dummy_stat_reg_2_i : in std_logic_vector(31 downto 0);
dummy_stat_reg_3_i : in std_logic_vector(31 downto 0);
dummy_stat_reg_switch_i : in std_logic_vector(31 downto 0)
);
end component;
component dummy_ctrl_regs_wb_slave
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
dummy_reg_1_o : out std_logic_vector(31 downto 0);
dummy_reg_2_o : out std_logic_vector(31 downto 0);
dummy_reg_3_o : out std_logic_vector(31 downto 0);
dummy_reg_led_o : out std_logic_vector(31 downto 0)
);
end component;
component ram_2048x32
port (
......@@ -250,8 +289,8 @@ architecture rtl of gw_wrapper is
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_CSR_WB_SLAVES_NB : integer := 1;
constant c_CSR_WB_ADDR_WIDTH : integer := 27;
constant c_BAR0_APERTURE : integer := 20;
constant c_CSR_WB_SLAVES_NB : integer := 2;
constant c_DMA_WB_SLAVES_NB : integer := 1;
constant c_DMA_WB_ADDR_WIDTH : integer := 26;
......@@ -263,14 +302,14 @@ architecture rtl of gw_wrapper is
signal l_clk : std_logic;
-- CSR wishbone bus
signal wb_adr_o : std_logic_vector(c_CSR_WB_ADDR_WIDTH-1 downto 0);
signal wb_adr : std_logic_vector(c_BAR0_APERTURE-log2_ceil(c_CSR_WB_SLAVES_NB+1)-1 downto 0);
signal wb_dat_i : std_logic_vector((32*c_CSR_WB_SLAVES_NB)-1 downto 0);
signal wb_dat_o : std_logic_vector(31 downto 0);
signal wb_sel_o : std_logic_vector(3 downto 0);
signal wb_cyc_o : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
signal wb_stb_o : std_logic;
signal wb_we_o : std_logic;
signal wb_ack_i : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
signal wb_sel : std_logic_vector(3 downto 0);
signal wb_cyc : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
signal wb_stb : std_logic;
signal wb_we : std_logic;
signal wb_ack : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
-- DMA wishbone bus
signal dma_adr_o : std_logic_vector(31 downto 0);
......@@ -282,12 +321,22 @@ architecture rtl of gw_wrapper is
signal dma_we_o : std_logic;
signal dma_ack_i : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
signal dma_stall_i : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
signal ram_we : std_logic_vector(0 downto 0);
signal ram_we : std_logic_vector(0 downto 0);
-- Interrupts stuff
signal irq_sources : std_logic_vector(1 downto 0);
signal irq_to_gn4124 : std_logic;
-- CSR whisbone slaves for test
signal dummy_stat_reg_1 : std_logic_vector(31 downto 0);
signal dummy_stat_reg_2 : std_logic_vector(31 downto 0);
signal dummy_stat_reg_3 : std_logic_vector(31 downto 0);
signal dummy_stat_reg_switch : std_logic_vector(31 downto 0);
signal dummy_ctrl_reg_1 : std_logic_vector(31 downto 0);
signal dummy_ctrl_reg_2 : std_logic_vector(31 downto 0);
signal dummy_ctrl_reg_3 : std_logic_vector(31 downto 0);
signal dummy_ctrl_reg_led : std_logic_vector(31 downto 0);
begin
......@@ -320,16 +369,14 @@ begin
SER_DVB_ASI <= '0';
GS4911_HOST_B <= '0';
SER_SMPTE_BYPASS <= '0';
LED <= (others => '1');
------------------------------------------------------------------------------
-- GN4124 interface
------------------------------------------------------------------------------
cmp_gn4124_core : gn4124_core
generic map (
g_BAR0_APERTURE => c_BAR0_APERTURE,
g_CSR_WB_SLAVES_NB => c_CSR_WB_SLAVES_NB,
g_CSR_WB_ADDR_WIDTH => c_CSR_WB_ADDR_WIDTH,
g_DMA_WB_SLAVES_NB => c_DMA_WB_SLAVES_NB,
g_DMA_WB_ADDR_WIDTH => c_DMA_WB_ADDR_WIDTH
)
......@@ -382,14 +429,14 @@ begin
---------------------------------------------------------
-- Target Interface (Wishbone master)
wb_clk_i => l_clk,
wb_adr_o => wb_adr_o,
wb_adr_o => wb_adr,
wb_dat_o => wb_dat_o,
wb_sel_o => wb_sel_o,
wb_stb_o => wb_stb_o,
wb_we_o => wb_we_o,
wb_cyc_o => wb_cyc_o,
wb_sel_o => wb_sel,
wb_stb_o => wb_stb,
wb_we_o => wb_we,
wb_cyc_o => wb_cyc,
wb_dat_i => wb_dat_i,
wb_ack_i => wb_ack_i,
wb_ack_i => wb_ack,
---------------------------------------------------------
-- L2P DMA Interface (Pipelined Wishbone master)
......@@ -407,11 +454,50 @@ begin
------------------------------------------------------------------------------
-- UNUSED CSR wishbone bus
-- CSR wishbone bus slaves
------------------------------------------------------------------------------
wb_ack_i <= (others => '0');
wb_dat_i <= (others => '0');
cmp_dummy_stat_regs : dummy_stat_regs_wb_slave
port map(
rst_n_i => L_RST_N,
wb_clk_i => l_clk,
wb_addr_i => wb_adr(1 downto 0),
wb_data_i => wb_dat_o,
wb_data_o => wb_dat_i(31 downto 0),
wb_cyc_i => wb_cyc(0),
wb_sel_i => wb_sel,
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_ack_o => wb_ack(0),
dummy_stat_reg_1_i => dummy_stat_reg_1,
dummy_stat_reg_2_i => dummy_stat_reg_2,
dummy_stat_reg_3_i => dummy_stat_reg_3,
dummy_stat_reg_switch_i => dummy_stat_reg_switch
);
dummy_stat_reg_1 <= X"DEADBABE";
dummy_stat_reg_2 <= X"BEEFFACE";
dummy_stat_reg_3 <= X"12345678";
dummy_stat_reg_switch <= X"000000" & DEBUG;
cmp_dummy_ctrl_regs : dummy_ctrl_regs_wb_slave
port map(
rst_n_i => L_RST_N,
wb_clk_i => l_clk,
wb_addr_i => wb_adr(1 downto 0),
wb_data_i => wb_dat_o,
wb_data_o => wb_dat_i(63 downto 32),
wb_cyc_i => wb_cyc(1),
wb_sel_i => wb_sel,
wb_stb_i => wb_stb,
wb_we_i => wb_we,
wb_ack_o => wb_ack(1),
dummy_reg_1_o => dummy_ctrl_reg_1,
dummy_reg_2_o => dummy_ctrl_reg_2,
dummy_reg_3_o => dummy_ctrl_reg_3,
dummy_reg_led_o => dummy_ctrl_reg_led
);
LED <= dummy_ctrl_reg_led(7 downto 0);
------------------------------------------------------------------------------
-- DMA wishbone bus connected to a DPRAM
......
hdl/gn4124core/design/rtl/wbmaster32.vhd
+ 19
− 17
View file @ 726ed8f8
......@@ -35,8 +35,9 @@ use work.gn4124_core_pkg.all;
entity wbmaster32 is
generic
(
g_WB_SLAVES_NB : integer := 2;
g_WB_ADDR_WIDTH : integer := 27
g_BAR0_APERTURE : integer := 20; -- BAR0 aperture, defined in GN4124 PCI_BAR_CONFIG register (0x80C)
-- => number of bits to address periph on the board
g_WB_SLAVES_NB : integer := 2
);
port
(
......@@ -82,15 +83,15 @@ entity wbmaster32 is
---------------------------------------------------------
-- CSR wishbone interface
wb_clk_i : in std_logic; -- Wishbone bus clock
wb_adr_o : out std_logic_vector(g_WB_ADDR_WIDTH-1 downto 0); -- Address
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic; -- Strobe
wb_we_o : out std_logic; -- Write
wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle
wb_dat_i : in std_logic_vector((32*g_WB_SLAVES_NB)-1 downto 0); -- Data in
wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Acknowledge
wb_clk_i : in std_logic; -- Wishbone bus clock
wb_adr_o : out std_logic_vector(g_BAR0_APERTURE-log2_ceil(g_WB_SLAVES_NB)-1 downto 0); -- Address
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic; -- Strobe
wb_we_o : out std_logic; -- Write
wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle
wb_dat_i : in std_logic_vector((32*g_WB_SLAVES_NB)-1 downto 0); -- Data in
wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Acknowledge
);
end wbmaster32;
......@@ -134,8 +135,8 @@ architecture behaviour of wbmaster32 is
--signal s_wb_we : std_logic;
signal s_wb_periph_addr : std_logic_vector(30-g_WB_ADDR_WIDTH downto 0);
signal wb_periph_addr : std_logic_vector(30-g_WB_ADDR_WIDTH downto 0);
signal s_wb_periph_addr : std_logic_vector(log2_ceil(g_WB_SLAVES_NB)-1 downto 0);
signal wb_periph_addr : std_logic_vector(log2_ceil(g_WB_SLAVES_NB)-1 downto 0);
signal s_wb_periph_select : std_logic_vector((2**s_wb_periph_addr'length)-1 downto 0);
signal s_wb_ack_muxed : std_logic;
signal wb_ack_t : std_logic;
......@@ -421,7 +422,8 @@ begin
------------------------------------------------------------------------------
-- Take the first N bits of the address to select the active wb peripheral
s_wb_periph_addr <= wb_adr_t(30 downto g_WB_ADDR_WIDTH);
-- g_BAR0_APERTURE represents byte address window, has to be shifted right by 2 to match wishbone 32-bit word addresses
s_wb_periph_addr <= wb_adr_t(g_BAR0_APERTURE-3 downto g_BAR0_APERTURE-log2_ceil(g_WB_SLAVES_NB)-2);
-----------------------------------------------------------------------------
-- One-hot decode function, s_wb_periph_select <= onehot_decode(s_wb_periph_addr);
......@@ -450,11 +452,11 @@ begin
wb_periph_addr <= (others => '0');
wb_dat_i_t <= (others => '0');
wb_ack_t <= '0';
elsif rising_edge(wb_clk_i) then
elsif rising_edge(wb_clk_i) then
wb_periph_addr <= s_wb_periph_addr;
wb_dat_i_t <= s_wb_dat_i_muxed;
wb_ack_t <= s_wb_ack_muxed;
end if;
end if;
end process p_wb_in_regs;
-- Select ack line of the active peripheral
......@@ -487,7 +489,7 @@ begin
wb_dat_o <= wb_dat_o_t;
wb_stb_o <= wb_stb_t;
wb_we_o <= wb_we_t;
wb_adr_o <= wb_adr_t(g_WB_ADDR_WIDTH-1 downto 0);
wb_adr_o <= wb_adr_t(g_BAR0_APERTURE-log2_ceil(g_WB_SLAVES_NB)-1 downto 0);
wb_sel_o <= wb_sel_t;
wb_cyc_o <= s_wb_cyc_demuxed;
......
hdl/gn4124core/gn4124core.xise
+ 8
− 0
View file @ 726ed8f8
......@@ -81,6 +81,14 @@
<file xil_pn:name="design/chipscope/cs_core.cdc" xil_pn:type="FILE_CDC">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="design/rtl/dummy_ctrl_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="design/rtl/dummy_stat_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="design/ipcore_dir/fifo_32x512.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation"/>
</file>
......
hdl/gn4124core/gw_wrapper.bit
+ 0
− 0
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hdl/gn4124core/gw_wrapper.par
+ 92
− 100
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hdl/gn4124core/gw_wrapper.syr
+ 328
− 225
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hdl/gn4124core/gw_wrapper.twr
+ 1128
− 1103
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