diff --git a/hdl/gn4124core/design/rtl/gn4124_core.vhd b/hdl/gn4124core/design/rtl/gn4124_core.vhd
index 6fd6af9340a04ec119521ea4a6937db931b0419d..47d851c0e731c7ad073d096606740f61e64a28a5 100644
--- a/hdl/gn4124core/design/rtl/gn4124_core.vhd
+++ b/hdl/gn4124core/design/rtl/gn4124_core.vhd
@@ -19,12 +19,11 @@
-- dependencies:
--
--------------------------------------------------------------------------------
--- last changes: 23-09-2010 (mcattin)
+-- last changes: see svn log
--------------------------------------------------------------------------------
-- TODO: - DMA wishbone bus address map
-- - reset and clock signals
--- - wishbone timeout generic
--- - rename component instance -> cmp_xxx
+-- - wishbone timeout generic ??
--------------------------------------------------------------------------------
library IEEE;
@@ -41,8 +40,9 @@ use UNISIM.vcomponents.all;
--==============================================================================
entity gn4124_core is
generic(
+ g_BAR0_APERTURE : integer := 20; -- BAR0 aperture, defined in GN4124 PCI_BAR_CONFIG register (0x80C)
+ -- => number of bits to address periph on the board
g_CSR_WB_SLAVES_NB : integer := 1; -- Number of CSR wishbone slaves
- g_CSR_WB_ADDR_WIDTH : integer := 27; -- CSR wishbone address bus width
g_DMA_WB_SLAVES_NB : integer := 1; -- Number of DMA wishbone slaves
g_DMA_WB_ADDR_WIDTH : integer := 26 -- DMA wishbone address bus width
);
@@ -66,7 +66,7 @@ entity gn4124_core is
p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
rx_error_o : out std_logic; -- Receive Error
- vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready
+ vc_rdy_i : in std_logic_vector(1 downto 0); -- Virtual channel ready
---------------------------------------------------------
-- L2P Direction
@@ -93,7 +93,7 @@ entity gn4124_core is
---------------------------------------------------------
-- Target interface (CSR wishbone master)
wb_clk_i : in std_logic;
- wb_adr_o : out std_logic_vector(g_CSR_WB_ADDR_WIDTH-1 downto 0);
+ wb_adr_o : out std_logic_vector(g_BAR0_APERTURE-log2_ceil(g_CSR_WB_SLAVES_NB+1)-1 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic;
@@ -242,7 +242,7 @@ architecture rtl of gn4124_core is
------------------------------------------------------------------------------
-- CSR wishbone bus
------------------------------------------------------------------------------
- signal wb_adr : std_logic_vector(g_CSR_WB_ADDR_WIDTH-1 downto 0);
+ signal wb_adr : std_logic_vector(g_BAR0_APERTURE-log2_ceil(g_CSR_WB_SLAVES_NB+1)-1 downto 0);
signal wb_dat_s2m : std_logic_vector((32*(g_CSR_WB_SLAVES_NB+1))-1 downto 0);
signal wb_dat_m2s : std_logic_vector(31 downto 0);
signal wb_sel : std_logic_vector(3 downto 0);
@@ -424,8 +424,8 @@ begin
cmp_wbmaster32 : wbmaster32
generic map
(
- g_WB_SLAVES_NB => (g_CSR_WB_SLAVES_NB + 1), -- +1 for the DMA controller (wb slave always present)
- g_WB_ADDR_WIDTH => g_CSR_WB_ADDR_WIDTH
+ g_BAR0_APERTURE => g_BAR0_APERTURE,
+ g_WB_SLAVES_NB => (g_CSR_WB_SLAVES_NB + 1) -- +1 for the DMA controller (wb slave always present)
)
port map
(
diff --git a/hdl/gn4124core/design/rtl/gn4124_core_pkg.vhd b/hdl/gn4124core/design/rtl/gn4124_core_pkg.vhd
index 9bd5ae7856e94db5ada14c81ea2bcb0c527f0aca..f395296591fb42984af2076d3ed0fd1ab3d7809c 100644
--- a/hdl/gn4124core/design/rtl/gn4124_core_pkg.vhd
+++ b/hdl/gn4124core/design/rtl/gn4124_core_pkg.vhd
@@ -45,6 +45,7 @@ package gn4124_core_pkg is
signal byte_swap : std_logic_vector(1 downto 0))
return std_logic_vector;
+ function log2_ceil(N : natural) return positive;
--==============================================================================
--! Components declaration
@@ -153,8 +154,9 @@ package gn4124_core_pkg is
-----------------------------------------------------------------------------
generic
(
- g_WB_SLAVES_NB : integer := 2;
- g_WB_ADDR_WIDTH : integer := 27
+ g_BAR0_APERTURE : integer := 20; -- BAR0 aperture, defined in GN4124 PCI_BAR_CONFIG register (0x80C)
+ -- => number of bits to address periph on the board
+ g_WB_SLAVES_NB : integer := 2
);
port
(
@@ -199,15 +201,15 @@ package gn4124_core_pkg is
---------------------------------------------------------
-- CSR wishbone interface
- wb_clk_i : in std_logic; -- Wishbone bus clock
- wb_adr_o : out std_logic_vector(g_WB_ADDR_WIDTH-1 downto 0); -- Address
- wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
- wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
- wb_stb_o : out std_logic; -- Strobe
- wb_we_o : out std_logic; -- Write
- wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle
- wb_dat_i : in std_logic_vector((32*g_WB_SLAVES_NB)-1 downto 0); -- Data in
- wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Acknowledge
+ wb_clk_i : in std_logic; -- Wishbone bus clock
+ wb_adr_o : out std_logic_vector(g_BAR0_APERTURE-log2_ceil(g_WB_SLAVES_NB)-1 downto 0); -- Address
+ wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
+ wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
+ wb_stb_o : out std_logic; -- Strobe
+ wb_we_o : out std_logic; -- Write
+ wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle
+ wb_dat_i : in std_logic_vector((32*g_WB_SLAVES_NB)-1 downto 0); -- Data in
+ wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Acknowledge
);
end component; -- wbmaster32
@@ -528,4 +530,16 @@ package body gn4124_core_pkg is
return dout;
end function f_byte_swap;
+ -----------------------------------------------------------------------------
+ -- Returns log of 2 of a natural number
+ -----------------------------------------------------------------------------
+ function log2_ceil(N : natural) return positive is
+ begin
+ if N < 2 then
+ return 1;
+ else
+ return 1 + log2_ceil(N/2);
+ end if;
+ end;
+
end gn4124_core_pkg;
diff --git a/hdl/gn4124core/design/rtl/gullwing_wrapper.vhd b/hdl/gn4124core/design/rtl/gullwing_wrapper.vhd
index 3a71b67c2cfca2c2bb2d87cf3e997e64d7b401b8..502905e18218621e4e58cd52ddeb50bfcaeb4b50 100644
--- a/hdl/gn4124core/design/rtl/gullwing_wrapper.vhd
+++ b/hdl/gn4124core/design/rtl/gullwing_wrapper.vhd
@@ -27,6 +27,7 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
+use work.gn4124_core_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
@@ -160,8 +161,9 @@ architecture rtl of gw_wrapper is
component gn4124_core
generic(
+ g_BAR0_APERTURE : integer := 20; -- BAR0 aperture, defined in GN4124 PCI_BAR_CONFIG register (0x80C)
+ -- => number of bits to address periph on the board
g_CSR_WB_SLAVES_NB : integer := 1; -- Number of CSR wishbone slaves
- g_CSR_WB_ADDR_WIDTH : integer := 27; -- CSR wishbone address bus width
g_DMA_WB_SLAVES_NB : integer := 1; -- Number of DMA wishbone slaves
g_DMA_WB_ADDR_WIDTH : integer := 26 -- DMA wishbone address bus width
);
@@ -212,7 +214,7 @@ architecture rtl of gw_wrapper is
---------------------------------------------------------
-- Target interface (CSR wishbone master)
wb_clk_i : in std_logic;
- wb_adr_o : out std_logic_vector(g_CSR_WB_ADDR_WIDTH-1 downto 0);
+ wb_adr_o : out std_logic_vector(g_BAR0_APERTURE-log2_ceil(g_CSR_WB_SLAVES_NB+1)-1 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic;
@@ -236,6 +238,43 @@ architecture rtl of gw_wrapper is
);
end component; -- gn4124_core
+ component dummy_stat_regs_wb_slave
+ port (
+ rst_n_i : in std_logic;
+ wb_clk_i : in std_logic;
+ wb_addr_i : in std_logic_vector(1 downto 0);
+ wb_data_i : in std_logic_vector(31 downto 0);
+ wb_data_o : out std_logic_vector(31 downto 0);
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(3 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_ack_o : out std_logic;
+ dummy_stat_reg_1_i : in std_logic_vector(31 downto 0);
+ dummy_stat_reg_2_i : in std_logic_vector(31 downto 0);
+ dummy_stat_reg_3_i : in std_logic_vector(31 downto 0);
+ dummy_stat_reg_switch_i : in std_logic_vector(31 downto 0)
+ );
+ end component;
+
+ component dummy_ctrl_regs_wb_slave
+ port (
+ rst_n_i : in std_logic;
+ wb_clk_i : in std_logic;
+ wb_addr_i : in std_logic_vector(1 downto 0);
+ wb_data_i : in std_logic_vector(31 downto 0);
+ wb_data_o : out std_logic_vector(31 downto 0);
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(3 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_ack_o : out std_logic;
+ dummy_reg_1_o : out std_logic_vector(31 downto 0);
+ dummy_reg_2_o : out std_logic_vector(31 downto 0);
+ dummy_reg_3_o : out std_logic_vector(31 downto 0);
+ dummy_reg_led_o : out std_logic_vector(31 downto 0)
+ );
+ end component;
component ram_2048x32
port (
@@ -250,8 +289,8 @@ architecture rtl of gw_wrapper is
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
- constant c_CSR_WB_SLAVES_NB : integer := 1;
- constant c_CSR_WB_ADDR_WIDTH : integer := 27;
+ constant c_BAR0_APERTURE : integer := 20;
+ constant c_CSR_WB_SLAVES_NB : integer := 2;
constant c_DMA_WB_SLAVES_NB : integer := 1;
constant c_DMA_WB_ADDR_WIDTH : integer := 26;
@@ -263,14 +302,14 @@ architecture rtl of gw_wrapper is
signal l_clk : std_logic;
-- CSR wishbone bus
- signal wb_adr_o : std_logic_vector(c_CSR_WB_ADDR_WIDTH-1 downto 0);
+ signal wb_adr : std_logic_vector(c_BAR0_APERTURE-log2_ceil(c_CSR_WB_SLAVES_NB+1)-1 downto 0);
signal wb_dat_i : std_logic_vector((32*c_CSR_WB_SLAVES_NB)-1 downto 0);
signal wb_dat_o : std_logic_vector(31 downto 0);
- signal wb_sel_o : std_logic_vector(3 downto 0);
- signal wb_cyc_o : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
- signal wb_stb_o : std_logic;
- signal wb_we_o : std_logic;
- signal wb_ack_i : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
+ signal wb_sel : std_logic_vector(3 downto 0);
+ signal wb_cyc : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
+ signal wb_stb : std_logic;
+ signal wb_we : std_logic;
+ signal wb_ack : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
-- DMA wishbone bus
signal dma_adr_o : std_logic_vector(31 downto 0);
@@ -282,12 +321,22 @@ architecture rtl of gw_wrapper is
signal dma_we_o : std_logic;
signal dma_ack_i : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
signal dma_stall_i : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
- signal ram_we : std_logic_vector(0 downto 0);
+ signal ram_we : std_logic_vector(0 downto 0);
-- Interrupts stuff
signal irq_sources : std_logic_vector(1 downto 0);
signal irq_to_gn4124 : std_logic;
+ -- CSR whisbone slaves for test
+ signal dummy_stat_reg_1 : std_logic_vector(31 downto 0);
+ signal dummy_stat_reg_2 : std_logic_vector(31 downto 0);
+ signal dummy_stat_reg_3 : std_logic_vector(31 downto 0);
+ signal dummy_stat_reg_switch : std_logic_vector(31 downto 0);
+
+ signal dummy_ctrl_reg_1 : std_logic_vector(31 downto 0);
+ signal dummy_ctrl_reg_2 : std_logic_vector(31 downto 0);
+ signal dummy_ctrl_reg_3 : std_logic_vector(31 downto 0);
+ signal dummy_ctrl_reg_led : std_logic_vector(31 downto 0);
begin
@@ -320,16 +369,14 @@ begin
SER_DVB_ASI <= '0';
GS4911_HOST_B <= '0';
SER_SMPTE_BYPASS <= '0';
- LED <= (others => '1');
-
------------------------------------------------------------------------------
-- GN4124 interface
------------------------------------------------------------------------------
cmp_gn4124_core : gn4124_core
generic map (
+ g_BAR0_APERTURE => c_BAR0_APERTURE,
g_CSR_WB_SLAVES_NB => c_CSR_WB_SLAVES_NB,
- g_CSR_WB_ADDR_WIDTH => c_CSR_WB_ADDR_WIDTH,
g_DMA_WB_SLAVES_NB => c_DMA_WB_SLAVES_NB,
g_DMA_WB_ADDR_WIDTH => c_DMA_WB_ADDR_WIDTH
)
@@ -382,14 +429,14 @@ begin
---------------------------------------------------------
-- Target Interface (Wishbone master)
wb_clk_i => l_clk,
- wb_adr_o => wb_adr_o,
+ wb_adr_o => wb_adr,
wb_dat_o => wb_dat_o,
- wb_sel_o => wb_sel_o,
- wb_stb_o => wb_stb_o,
- wb_we_o => wb_we_o,
- wb_cyc_o => wb_cyc_o,
+ wb_sel_o => wb_sel,
+ wb_stb_o => wb_stb,
+ wb_we_o => wb_we,
+ wb_cyc_o => wb_cyc,
wb_dat_i => wb_dat_i,
- wb_ack_i => wb_ack_i,
+ wb_ack_i => wb_ack,
---------------------------------------------------------
-- L2P DMA Interface (Pipelined Wishbone master)
@@ -407,11 +454,50 @@ begin
------------------------------------------------------------------------------
- -- UNUSED CSR wishbone bus
+ -- CSR wishbone bus slaves
------------------------------------------------------------------------------
- wb_ack_i <= (others => '0');
- wb_dat_i <= (others => '0');
+ cmp_dummy_stat_regs : dummy_stat_regs_wb_slave
+ port map(
+ rst_n_i => L_RST_N,
+ wb_clk_i => l_clk,
+ wb_addr_i => wb_adr(1 downto 0),
+ wb_data_i => wb_dat_o,
+ wb_data_o => wb_dat_i(31 downto 0),
+ wb_cyc_i => wb_cyc(0),
+ wb_sel_i => wb_sel,
+ wb_stb_i => wb_stb,
+ wb_we_i => wb_we,
+ wb_ack_o => wb_ack(0),
+ dummy_stat_reg_1_i => dummy_stat_reg_1,
+ dummy_stat_reg_2_i => dummy_stat_reg_2,
+ dummy_stat_reg_3_i => dummy_stat_reg_3,
+ dummy_stat_reg_switch_i => dummy_stat_reg_switch
+ );
+
+ dummy_stat_reg_1 <= X"DEADBABE";
+ dummy_stat_reg_2 <= X"BEEFFACE";
+ dummy_stat_reg_3 <= X"12345678";
+ dummy_stat_reg_switch <= X"000000" & DEBUG;
+
+ cmp_dummy_ctrl_regs : dummy_ctrl_regs_wb_slave
+ port map(
+ rst_n_i => L_RST_N,
+ wb_clk_i => l_clk,
+ wb_addr_i => wb_adr(1 downto 0),
+ wb_data_i => wb_dat_o,
+ wb_data_o => wb_dat_i(63 downto 32),
+ wb_cyc_i => wb_cyc(1),
+ wb_sel_i => wb_sel,
+ wb_stb_i => wb_stb,
+ wb_we_i => wb_we,
+ wb_ack_o => wb_ack(1),
+ dummy_reg_1_o => dummy_ctrl_reg_1,
+ dummy_reg_2_o => dummy_ctrl_reg_2,
+ dummy_reg_3_o => dummy_ctrl_reg_3,
+ dummy_reg_led_o => dummy_ctrl_reg_led
+ );
+ LED <= dummy_ctrl_reg_led(7 downto 0);
------------------------------------------------------------------------------
-- DMA wishbone bus connected to a DPRAM
diff --git a/hdl/gn4124core/design/rtl/wbmaster32.vhd b/hdl/gn4124core/design/rtl/wbmaster32.vhd
index 5e037d96fea5e3a1c9fbad06cf3b33d7bae38d05..97403efde4b8a97fce094ac01c312aa3f99073cb 100644
--- a/hdl/gn4124core/design/rtl/wbmaster32.vhd
+++ b/hdl/gn4124core/design/rtl/wbmaster32.vhd
@@ -35,8 +35,9 @@ use work.gn4124_core_pkg.all;
entity wbmaster32 is
generic
(
- g_WB_SLAVES_NB : integer := 2;
- g_WB_ADDR_WIDTH : integer := 27
+ g_BAR0_APERTURE : integer := 20; -- BAR0 aperture, defined in GN4124 PCI_BAR_CONFIG register (0x80C)
+ -- => number of bits to address periph on the board
+ g_WB_SLAVES_NB : integer := 2
);
port
(
@@ -82,15 +83,15 @@ entity wbmaster32 is
---------------------------------------------------------
-- CSR wishbone interface
- wb_clk_i : in std_logic; -- Wishbone bus clock
- wb_adr_o : out std_logic_vector(g_WB_ADDR_WIDTH-1 downto 0); -- Address
- wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
- wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
- wb_stb_o : out std_logic; -- Strobe
- wb_we_o : out std_logic; -- Write
- wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle
- wb_dat_i : in std_logic_vector((32*g_WB_SLAVES_NB)-1 downto 0); -- Data in
- wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Acknowledge
+ wb_clk_i : in std_logic; -- Wishbone bus clock
+ wb_adr_o : out std_logic_vector(g_BAR0_APERTURE-log2_ceil(g_WB_SLAVES_NB)-1 downto 0); -- Address
+ wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
+ wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
+ wb_stb_o : out std_logic; -- Strobe
+ wb_we_o : out std_logic; -- Write
+ wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle
+ wb_dat_i : in std_logic_vector((32*g_WB_SLAVES_NB)-1 downto 0); -- Data in
+ wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Acknowledge
);
end wbmaster32;
@@ -134,8 +135,8 @@ architecture behaviour of wbmaster32 is
--signal s_wb_we : std_logic;
- signal s_wb_periph_addr : std_logic_vector(30-g_WB_ADDR_WIDTH downto 0);
- signal wb_periph_addr : std_logic_vector(30-g_WB_ADDR_WIDTH downto 0);
+ signal s_wb_periph_addr : std_logic_vector(log2_ceil(g_WB_SLAVES_NB)-1 downto 0);
+ signal wb_periph_addr : std_logic_vector(log2_ceil(g_WB_SLAVES_NB)-1 downto 0);
signal s_wb_periph_select : std_logic_vector((2**s_wb_periph_addr'length)-1 downto 0);
signal s_wb_ack_muxed : std_logic;
signal wb_ack_t : std_logic;
@@ -421,7 +422,8 @@ begin
------------------------------------------------------------------------------
-- Take the first N bits of the address to select the active wb peripheral
- s_wb_periph_addr <= wb_adr_t(30 downto g_WB_ADDR_WIDTH);
+ -- g_BAR0_APERTURE represents byte address window, has to be shifted right by 2 to match wishbone 32-bit word addresses
+ s_wb_periph_addr <= wb_adr_t(g_BAR0_APERTURE-3 downto g_BAR0_APERTURE-log2_ceil(g_WB_SLAVES_NB)-2);
-----------------------------------------------------------------------------
-- One-hot decode function, s_wb_periph_select <= onehot_decode(s_wb_periph_addr);
@@ -450,11 +452,11 @@ begin
wb_periph_addr <= (others => '0');
wb_dat_i_t <= (others => '0');
wb_ack_t <= '0';
- elsif rising_edge(wb_clk_i) then
+ elsif rising_edge(wb_clk_i) then
wb_periph_addr <= s_wb_periph_addr;
wb_dat_i_t <= s_wb_dat_i_muxed;
wb_ack_t <= s_wb_ack_muxed;
- end if;
+ end if;
end process p_wb_in_regs;
-- Select ack line of the active peripheral
@@ -487,7 +489,7 @@ begin
wb_dat_o <= wb_dat_o_t;
wb_stb_o <= wb_stb_t;
wb_we_o <= wb_we_t;
- wb_adr_o <= wb_adr_t(g_WB_ADDR_WIDTH-1 downto 0);
+ wb_adr_o <= wb_adr_t(g_BAR0_APERTURE-log2_ceil(g_WB_SLAVES_NB)-1 downto 0);
wb_sel_o <= wb_sel_t;
wb_cyc_o <= s_wb_cyc_demuxed;
diff --git a/hdl/gn4124core/gn4124core.xise b/hdl/gn4124core/gn4124core.xise
index 65f67bd95efab0795fced084fffd86f3dd5f19ab..3d008e78f4b4e28439f4b87b7ed46b4c9bbb966d 100644
--- a/hdl/gn4124core/gn4124core.xise
+++ b/hdl/gn4124core/gn4124core.xise
@@ -81,6 +81,14 @@
<file xil_pn:name="design/chipscope/cs_core.cdc" xil_pn:type="FILE_CDC">
<association xil_pn:name="Implementation"/>
</file>
+ <file xil_pn:name="design/rtl/dummy_ctrl_regs.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation"/>
+ <association xil_pn:name="Implementation"/>
+ </file>
+ <file xil_pn:name="design/rtl/dummy_stat_regs.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation"/>
+ <association xil_pn:name="Implementation"/>
+ </file>
<file xil_pn:name="design/ipcore_dir/fifo_32x512.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation"/>
</file>
diff --git a/hdl/gn4124core/gw_wrapper.bit b/hdl/gn4124core/gw_wrapper.bit
index c793a6bfc49f4f65facab7cb44b7a81ac7eb8ba2..f0dab7569a9775de7c4a1bccfd27e659c06ebdf4 100644
Binary files a/hdl/gn4124core/gw_wrapper.bit and b/hdl/gn4124core/gw_wrapper.bit differ
diff --git a/hdl/gn4124core/gw_wrapper.par b/hdl/gn4124core/gw_wrapper.par
index b7a6e9445f7d0fc2ee026d0898c238c80818637d..84cdfc74724678187924745f7649178968955d94 100644
--- a/hdl/gn4124core/gw_wrapper.par
+++ b/hdl/gn4124core/gw_wrapper.par
@@ -1,7 +1,7 @@
Release 12.2 par M.63c (lin)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
-ABPC10853:: Fri Nov 05 15:11:05 2010
+ABPC10853:: Wed Nov 10 20:02:41 2010
par -w -intstyle ise -pl high -rl high -xe n -t 1 gw_wrapper_map.ncd
gw_wrapper.ncd gw_wrapper.pcf
@@ -10,19 +10,19 @@ gw_wrapper.ncd gw_wrapper.pcf
Constraints file: gw_wrapper.pcf.
Loading device for application Rf_Device from file '3s1400a.nph' in environment /opt/Xilinx/12.2/ISE_DS/ISE/.
"gw_wrapper" is an NCD, version 3.2, device xc3s1400a, package fg484, speed -5
-WARNING:ConstraintSystem:64 - Constraint <NET "L_WR_RDY<1>/L_WR_RDY_1_IBUF" MAXDELAY = 2 ns;> [gw_wrapper.pcf(17914)]
- overrides constraint <NET "L_WR_RDY<1>/L_WR_RDY_1_IBUF" MAXDELAY = 2 ns;> [gw_wrapper.pcf(17913)] on the design
+WARNING:ConstraintSystem:64 - Constraint <NET "L_WR_RDY<1>/L_WR_RDY_1_IBUF" MAXDELAY = 2 ns;> [gw_wrapper.pcf(17905)]
+ overrides constraint <NET "L_WR_RDY<1>/L_WR_RDY_1_IBUF" MAXDELAY = 2 ns;> [gw_wrapper.pcf(17904)] on the design
object 'L_WR_RDY<1>/L_WR_RDY_1_IBUF'.
-WARNING:ConstraintSystem:64 - Constraint <NET "L_WR_RDY<0>/L_WR_RDY_0_IBUF" MAXDELAY = 2 ns;> [gw_wrapper.pcf(17916)]
- overrides constraint <NET "L_WR_RDY<0>/L_WR_RDY_0_IBUF" MAXDELAY = 2 ns;> [gw_wrapper.pcf(17915)] on the design
+WARNING:ConstraintSystem:64 - Constraint <NET "L_WR_RDY<0>/L_WR_RDY_0_IBUF" MAXDELAY = 2 ns;> [gw_wrapper.pcf(17907)]
+ overrides constraint <NET "L_WR_RDY<0>/L_WR_RDY_0_IBUF" MAXDELAY = 2 ns;> [gw_wrapper.pcf(17906)] on the design
object 'L_WR_RDY<0>/L_WR_RDY_0_IBUF'.
-WARNING:ConstraintSystem:64 - Constraint <NET "VC_RDY<1>_IBUF" MAXDELAY = 2 ns;> [gw_wrapper.pcf(17921)] overrides
- constraint <NET "VC_RDY<1>_IBUF" MAXDELAY = 2 ns;> [gw_wrapper.pcf(17920)] on the design object 'VC_RDY<1>_IBUF'.
+WARNING:ConstraintSystem:64 - Constraint <NET "VC_RDY<1>_IBUF" MAXDELAY = 2 ns;> [gw_wrapper.pcf(17912)] overrides
+ constraint <NET "VC_RDY<1>_IBUF" MAXDELAY = 2 ns;> [gw_wrapper.pcf(17911)] on the design object 'VC_RDY<1>_IBUF'.
-WARNING:ConstraintSystem:64 - Constraint <NET "VC_RDY<0>_IBUF" MAXDELAY = 2 ns;> [gw_wrapper.pcf(17923)] overrides
- constraint <NET "VC_RDY<0>_IBUF" MAXDELAY = 2 ns;> [gw_wrapper.pcf(17922)] on the design object 'VC_RDY<0>_IBUF'.
+WARNING:ConstraintSystem:64 - Constraint <NET "VC_RDY<0>_IBUF" MAXDELAY = 2 ns;> [gw_wrapper.pcf(17914)] overrides
+ constraint <NET "VC_RDY<0>_IBUF" MAXDELAY = 2 ns;> [gw_wrapper.pcf(17913)] on the design object 'VC_RDY<0>_IBUF'.
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
@@ -63,8 +63,8 @@ Design Summary Report:
Number of LOCed BUFGMUXs 2 out of 5 40%
Number of RAMB16BWEs 28 out of 32 87%
- Number of Slices 3624 out of 11264 32%
- Number of SLICEMs 307 out of 5632 5%
+ Number of Slices 4019 out of 11264 35%
+ Number of SLICEMs 305 out of 5632 5%
@@ -73,9 +73,55 @@ Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please
consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.
-Starting initial Timing Analysis. REAL time: 44 secs
+Starting initial Timing Analysis. REAL time: 43 secs
Finished initial Timing Analysis. REAL time: 44 secs
+WARNING:Par:288 - The signal MIC_DATA<20>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal MIC_DATA<12>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal MIC_DATA<21>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal MIC_DATA<13>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal MIC_DATA<30>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal MIC_DATA<22>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal MIC_DATA<14>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal MIC_DATA<31>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal MIC_DATA<23>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal MIC_DATA<15>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal MIC_DATA<24>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal MIC_DATA<16>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal MIC_DATA<25>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal MIC_DATA<17>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal MIC_DATA<26>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal MIC_DATA<18>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal MIC_DATA<27>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal MIC_DATA<19>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal MIC_DATA<28>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal MIC_DATA<29>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal DES_PCLK_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal GPIO<10>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal GPIO<11>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal GPIO<12>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal GPIO<13>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal GPIO<14>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal GPIO<15>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal DES<10>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal DES<11>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal DES<12>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal DES<13>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal DES<14>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal DES<15>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal DES<16>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal DES<17>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal DES<18>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal DES<19>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal GPIO<0>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal GPIO<1>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal GPIO<2>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal GPIO<3>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal GPIO<4>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal GPIO<5>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal GPIO<6>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal GPIO<7>_IBUF has no load. PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal GPIO<9>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/gl0.rd/grhf.rhf/ram_valid_d1_mux0001 has no load. PAR
will not attempt to route this signal.
@@ -127,97 +173,43 @@ WARNING:Par:288 - The signal SYNCSEPERATOR_V_TIMING_IBUF has no load. PAR will
WARNING:Par:288 - The signal DES_SMPTE_BYPASS_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal GS4911_SDOUT_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DES_SDHDN_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DEBUG<0>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DEBUG<1>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DEBUG<2>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DEBUG<3>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DEBUG<4>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DEBUG<5>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DEBUG<6>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DEBUG<7>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal PCLK_4911_1531_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal DES_DVB_ASI_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal MIC_DATA<10>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal MIC_DATA<11>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<20>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<12>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<21>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<13>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<30>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<22>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<14>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<31>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<23>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<15>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<24>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<16>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<25>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<17>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<26>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<18>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<27>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<19>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<28>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal MIC_DATA<29>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES_PCLK_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<10>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<11>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<12>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<13>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<14>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<15>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES<10>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES<11>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES<12>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES<13>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES<14>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES<15>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES<16>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES<17>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES<18>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal DES<19>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<0>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<1>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<2>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<3>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<4>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<5>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<6>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<7>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal GPIO<9>_IBUF has no load. PAR will not attempt to route this signal.
Starting Router
-Phase 1 : 23588 unrouted; REAL time: 1 mins 9 secs
+Phase 1 : 25214 unrouted; REAL time: 1 mins 9 secs
-Phase 2 : 18410 unrouted; REAL time: 1 mins 11 secs
+Phase 2 : 19756 unrouted; REAL time: 1 mins 10 secs
-Phase 3 : 5259 unrouted; REAL time: 1 mins 22 secs
+Phase 3 : 5151 unrouted; REAL time: 1 mins 22 secs
-Phase 4 : 5683 unrouted; (Setup:20580, Hold:0, Component Switching Limit:0) REAL time: 1 mins 58 secs
+Phase 4 : 5717 unrouted; (Setup:18855, Hold:0, Component Switching Limit:0) REAL time: 2 mins 15 secs
-Phase 5 : 0 unrouted; (Setup:33675, Hold:0, Component Switching Limit:0) REAL time: 2 mins 44 secs
+Phase 5 : 0 unrouted; (Setup:44177, Hold:0, Component Switching Limit:0) REAL time: 3 mins 5 secs
Updating file: gw_wrapper.ncd with current fully routed design.
-Phase 6 : 0 unrouted; (Setup:33675, Hold:0, Component Switching Limit:0) REAL time: 2 mins 49 secs
+Phase 6 : 0 unrouted; (Setup:44177, Hold:0, Component Switching Limit:0) REAL time: 3 mins 10 secs
-Phase 7 : 0 unrouted; (Setup:33675, Hold:0, Component Switching Limit:0) REAL time: 3 mins 36 secs
+Phase 7 : 0 unrouted; (Setup:44177, Hold:0, Component Switching Limit:0) REAL time: 4 mins 56 secs
-Phase 8 : 0 unrouted; (Setup:26917, Hold:0, Component Switching Limit:0) REAL time: 5 mins 15 secs
+Phase 8 : 0 unrouted; (Setup:31118, Hold:0, Component Switching Limit:0) REAL time: 5 mins 51 secs
Updating file: gw_wrapper.ncd with current fully routed design.
-Phase 9 : 0 unrouted; (Setup:26917, Hold:0, Component Switching Limit:0) REAL time: 7 mins 4 secs
+Phase 9 : 0 unrouted; (Setup:31118, Hold:0, Component Switching Limit:0) REAL time: 9 mins 31 secs
-Phase 10 : 0 unrouted; (Setup:26917, Hold:0, Component Switching Limit:0) REAL time: 7 mins 4 secs
+Phase 10 : 0 unrouted; (Setup:31118, Hold:0, Component Switching Limit:0) REAL time: 9 mins 32 secs
-Phase 11 : 0 unrouted; (Setup:22013, Hold:0, Component Switching Limit:0) REAL time: 7 mins 8 secs
+Phase 11 : 0 unrouted; (Setup:22331, Hold:0, Component Switching Limit:0) REAL time: 9 mins 36 secs
WARNING:Route:455 - CLK Net:icon_control0<13> may have excessive skew because
1 CLK pins and 4 NON_CLK pins failed to route using a CLK template.
-Total REAL time to Router completion: 7 mins 8 secs
-Total CPU time to Router completion: 7 mins 6 secs
+Total REAL time to Router completion: 9 mins 36 secs
+Total CPU time to Router completion: 9 mins 33 secs
Partition Implementation Status
-------------------------------
@@ -236,27 +228,27 @@ Generating Clock Report
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/clk_ | | | | | |
-| p | BUFGMUX_X2Y10|Yes | 2540 | 0.313 | 1.197 |
+| p | BUFGMUX_X2Y10|Yes | 2661 | 0.292 | 1.177 |
+---------------------+--------------+------+------+------------+-------------+
-| l_clk | BUFGMUX_X2Y1| No | 729 | 0.179 | 1.069 |
-+---------------------+--------------+------+------+------------+-------------+
-| icon_control0<0> | BUFGMUX_X1Y0| No | 182 | 0.160 | 1.045 |
+| icon_control0<0> | BUFGMUX_X1Y0| No | 181 | 0.140 | 1.030 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/clk_ | | | | | |
-| n | BUFGMUX_X2Y11|Yes | 51 | 0.107 | 1.041 |
+| n | BUFGMUX_X2Y11|Yes | 51 | 0.117 | 1.041 |
+---------------------+--------------+------+------+------------+-------------+
-| icon_control0<13> | Local| | 5 | 0.000 | 0.390 |
+| l_clk | BUFGMUX_X2Y1| No | 905 | 0.227 | 1.112 |
+---------------------+--------------+------+------+------------+-------------+
|U_icon_pro/U0/iUPDAT | | | | | |
| E_OUT | Local| | 1 | 0.000 | 1.699 |
+---------------------+--------------+------+------+------------+-------------+
+| icon_control0<13> | Local| | 5 | 0.000 | 0.758 |
++---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
-Timing Score: 22013 (Setup: 22013, Hold: 0, Component Switching Limit: 0)
+Timing Score: 22331 (Setup: 22331, Hold: 0, Component Switching Limit: 0)
WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in
your design.
@@ -286,8 +278,8 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
-* TS_p2l_clkn = PERIOD TIMEGRP "p2l_clkn_gr | SETUP | -0.673ns| 5.673ns| 65| 22013
- p" 5 ns HIGH 50% | HOLD | 0.274ns| | 0| 0
+* TS_p2l_clkn = PERIOD TIMEGRP "p2l_clkn_gr | SETUP | -0.647ns| 5.647ns| 98| 22331
+ p" 5 ns HIGH 50% | HOLD | 0.428ns| | 0| 0
----------------------------------------------------------------------------------------------------------
NET "cmp_gn4124_core/clk_p_buf" MAXDELAY | MAXDELAY | 0.078ns| 0.022ns| 0| 0
= 0.1 ns | | | | |
@@ -544,18 +536,18 @@ Asterisk (*) preceding a constraint indicates it was not met.
----------------------------------------------------------------------------------------------------------
NET "VC_RDY<1>_IBUF" MAXDELAY = 2 ns | MAXDELAY | 2.000ns| 0.000ns| 0| 0
----------------------------------------------------------------------------------------------------------
- TS_U_TO_J = MAXDELAY FROM TIMEGRP "U_CLK" | SETUP | 10.345ns| 4.655ns| 0| 0
- TO TIMEGRP "J_CLK" 15 ns | HOLD | 1.965ns| | 0| 0
+ TS_U_TO_J = MAXDELAY FROM TIMEGRP "U_CLK" | SETUP | 9.463ns| 5.537ns| 0| 0
+ TO TIMEGRP "J_CLK" 15 ns | HOLD | 2.000ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_U_TO_U = MAXDELAY FROM TIMEGRP "U_CLK" | SETUP | 13.697ns| 1.303ns| 0| 0
TO TIMEGRP "U_CLK" 15 ns | HOLD | 0.955ns| | 0| 0
----------------------------------------------------------------------------------------------------------
- TS_J_CLK = PERIOD TIMEGRP "J_CLK" 30 ns H | SETUP | 17.070ns| 12.930ns| 0| 0
- IGH 50% | HOLD | 0.798ns| | 0| 0
+ TS_J_CLK = PERIOD TIMEGRP "J_CLK" 30 ns H | SETUP | 14.697ns| 15.303ns| 0| 0
+ IGH 50% | HOLD | 0.645ns| | 0| 0
----------------------------------------------------------------------------------------------------------
- PATH "TS_D_TO_J_path" TIG | SETUP | N/A| 4.647ns| N/A| 0
+ PATH "TS_D_TO_J_path" TIG | SETUP | N/A| 5.642ns| N/A| 0
----------------------------------------------------------------------------------------------------------
- PATH "TS_J_TO_D_path" TIG | SETUP | N/A| 6.239ns| N/A| 0
+ PATH "TS_J_TO_D_path" TIG | SETUP | N/A| 6.615ns| N/A| 0
----------------------------------------------------------------------------------------------------------
NET "VC_RDY<0>_IBUF" MAXDELAY = 2 ns | N/A | N/A| N/A| N/A| N/A
----------------------------------------------------------------------------------------------------------
@@ -596,19 +588,19 @@ Generating Pad Report.
All signals are completely routed.
-WARNING:Par:283 - There are 107 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
+WARNING:Par:283 - There are 99 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
-Total REAL time to PAR completion: 7 mins 13 secs
-Total CPU time to PAR completion: 7 mins 11 secs
+Total REAL time to PAR completion: 9 mins 41 secs
+Total CPU time to PAR completion: 9 mins 38 secs
-Peak Memory Usage: 247 MB
+Peak Memory Usage: 250 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
-Timing: Completed - 65 errors found.
+Timing: Completed - 98 errors found.
Number of error messages: 0
-Number of warning messages: 115
+Number of warning messages: 107
Number of info messages: 1
Writing design to file gw_wrapper.ncd
diff --git a/hdl/gn4124core/gw_wrapper.syr b/hdl/gn4124core/gw_wrapper.syr
index abc9e2c0bd97354cba2da940ddb93f919f02a220..e6dcc3f1986fc5e2ff6c38b7d9623d9efb822d11 100644
--- a/hdl/gn4124core/gw_wrapper.syr
+++ b/hdl/gn4124core/gw_wrapper.syr
@@ -4,15 +4,15 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Parameter TMPDIR set to xst/projnav.tmp
-Total REAL time to Xst completion: 1.00 secs
-Total CPU time to Xst completion: 0.11 secs
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.14 secs
-->
Parameter xsthdpdir set to xst
-Total REAL time to Xst completion: 1.00 secs
-Total CPU time to Xst completion: 0.11 secs
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.14 secs
-->
Reading design: gw_wrapper.prj
@@ -128,20 +128,21 @@ Architecture rtl of Entity p2l_decode32 is up to date.
Compiling vhdl file "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/wbmaster32.vhd" in Library work.
Architecture behaviour of Entity wbmaster32 is up to date.
Compiling vhdl file "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/dma_controller.vhd" in Library work.
-Entity <dma_controller> compiled.
-Entity <dma_controller> (Architecture <behaviour>) compiled.
+Architecture behaviour of Entity dma_controller is up to date.
Compiling vhdl file "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/l2p_dma_master.vhd" in Library work.
-Entity <l2p_dma_master> compiled.
-Entity <l2p_dma_master> (Architecture <behaviour>) compiled.
+Architecture behaviour of Entity l2p_dma_master is up to date.
Compiling vhdl file "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/p2l_dma_master.vhd" in Library work.
-Entity <p2l_dma_master> compiled.
-Entity <p2l_dma_master> (Architecture <behaviour>) compiled.
+Architecture behaviour of Entity p2l_dma_master is up to date.
Compiling vhdl file "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/l2p_arbiter.vhd" in Library work.
Architecture rtl of Entity l2p_arbiter is up to date.
Compiling vhdl file "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/l2p_ser.vhd" in Library work.
Architecture rtl of Entity l2p_ser is up to date.
Compiling vhdl file "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/gn4124_core.vhd" in Library work.
Architecture rtl of Entity gn4124_core is up to date.
+Compiling vhdl file "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/dummy_stat_regs.vhd" in Library work.
+Architecture syn of Entity dummy_stat_regs_wb_slave is up to date.
+Compiling vhdl file "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/dummy_ctrl_regs.vhd" in Library work.
+Architecture syn of Entity dummy_ctrl_regs_wb_slave is up to date.
Compiling vhdl file "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/ipcore_dir/ram_2048x32.vhd" in Library work.
Architecture ram_2048x32_a of Entity ram_2048x32 is up to date.
Compiling vhdl file "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/gullwing_wrapper.vhd" in Library work.
@@ -154,18 +155,22 @@ Analyzing hierarchy for entity <gw_wrapper> in library <work> (architecture <rtl
TAR_ADDR_WDTH = 13
Analyzing hierarchy for entity <gn4124_core> in library <work> (architecture <rtl>) with generics.
- g_CSR_WB_ADDR_WIDTH = 27
- g_CSR_WB_SLAVES_NB = 1
+ g_BAR0_APERTURE = 20
+ g_CSR_WB_SLAVES_NB = 2
g_DMA_WB_ADDR_WIDTH = 26
g_DMA_WB_SLAVES_NB = 1
+Analyzing hierarchy for entity <dummy_stat_regs_wb_slave> in library <work> (architecture <syn>).
+
+Analyzing hierarchy for entity <dummy_ctrl_regs_wb_slave> in library <work> (architecture <syn>).
+
Analyzing hierarchy for entity <p2l_des> in library <work> (architecture <rtl>).
Analyzing hierarchy for entity <p2l_decode32> in library <work> (architecture <rtl>).
Analyzing hierarchy for entity <wbmaster32> in library <work> (architecture <behaviour>) with generics.
- g_WB_ADDR_WIDTH = 27
- g_WB_SLAVES_NB = 2
+ g_BAR0_APERTURE = 20
+ g_WB_SLAVES_NB = 3
Analyzing hierarchy for entity <dma_controller> in library <work> (architecture <behaviour>).
@@ -193,12 +198,12 @@ Analyzing generic Entity <gw_wrapper> in library <work> (Architecture <rtl>).
Set user-defined property "IBUF_LOW_PWR = TRUE" for instance <cmp_sysclk_buf> in unit <gw_wrapper>.
Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance <cmp_sysclk_buf> in unit <gw_wrapper>.
Set user-defined property "IOSTANDARD = DEFAULT" for instance <cmp_sysclk_buf> in unit <gw_wrapper>.
-WARNING:Xst:2211 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/gullwing_wrapper.vhd" line 436: Instantiating black box module <ram_2048x32>.
+WARNING:Xst:2211 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/gullwing_wrapper.vhd" line 522: Instantiating black box module <ram_2048x32>.
Entity <gw_wrapper> analyzed. Unit <gw_wrapper> generated.
Analyzing generic Entity <gn4124_core> in library <work> (Architecture <rtl>).
- g_CSR_WB_ADDR_WIDTH = 27
- g_CSR_WB_SLAVES_NB = 1
+ g_BAR0_APERTURE = 20
+ g_CSR_WB_SLAVES_NB = 2
g_DMA_WB_ADDR_WIDTH = 26
g_DMA_WB_SLAVES_NB = 1
Set user-defined property "CAPACITANCE = DONT_CARE" for instance <CLK_ibuf> in unit <gn4124_core>.
@@ -220,15 +225,15 @@ Analyzing Entity <p2l_decode32> in library <work> (Architecture <rtl>).
Entity <p2l_decode32> analyzed. Unit <p2l_decode32> generated.
Analyzing generic Entity <wbmaster32> in library <work> (Architecture <behaviour>).
- g_WB_ADDR_WIDTH = 27
- g_WB_SLAVES_NB = 2
-WARNING:Xst:753 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/wbmaster32.vhd" line 301: Unconnected output port 'full' of component 'fifo_64x512'.
-WARNING:Xst:753 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/wbmaster32.vhd" line 301: Unconnected output port 'valid' of component 'fifo_64x512'.
-WARNING:Xst:2211 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/wbmaster32.vhd" line 301: Instantiating black box module <fifo_64x512>.
-WARNING:Xst:753 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/wbmaster32.vhd" line 322: Unconnected output port 'full' of component 'fifo_32x512'.
-WARNING:Xst:753 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/wbmaster32.vhd" line 322: Unconnected output port 'valid' of component 'fifo_32x512'.
-WARNING:Xst:2211 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/wbmaster32.vhd" line 322: Instantiating black box module <fifo_32x512>.
-WARNING:Xst:790 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/wbmaster32.vhd" line 464: Index value(s) does not match array range, simulation mismatch.
+ g_BAR0_APERTURE = 20
+ g_WB_SLAVES_NB = 3
+WARNING:Xst:753 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/wbmaster32.vhd" line 302: Unconnected output port 'full' of component 'fifo_64x512'.
+WARNING:Xst:753 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/wbmaster32.vhd" line 302: Unconnected output port 'valid' of component 'fifo_64x512'.
+WARNING:Xst:2211 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/wbmaster32.vhd" line 302: Instantiating black box module <fifo_64x512>.
+WARNING:Xst:753 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/wbmaster32.vhd" line 323: Unconnected output port 'full' of component 'fifo_32x512'.
+WARNING:Xst:753 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/wbmaster32.vhd" line 323: Unconnected output port 'valid' of component 'fifo_32x512'.
+WARNING:Xst:2211 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/wbmaster32.vhd" line 323: Instantiating black box module <fifo_32x512>.
+WARNING:Xst:790 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/wbmaster32.vhd" line 466: Index value(s) does not match array range, simulation mismatch.
Entity <wbmaster32> analyzed. Unit <wbmaster32> generated.
Analyzing Entity <dma_controller> in library <work> (Architecture <behaviour>).
@@ -295,6 +300,16 @@ Analyzing Entity <l2p_ser> in library <work> (Architecture <rtl>).
Set user-defined property "INIT = 0" for instance <L2P_CLK_int> in unit <l2p_ser>.
Entity <l2p_ser> analyzed. Unit <l2p_ser> generated.
+Analyzing Entity <dummy_stat_regs_wb_slave> in library <work> (Architecture <syn>).
+INFO:Xst:1561 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/dummy_stat_regs.vhd" line 110: Mux is complete : default of case is discarded
+INFO:Xst:2679 - Register <ack_sreg<9>> in unit <dummy_stat_regs_wb_slave> has a constant value of 0 during circuit operation. The register is replaced by logic.
+Entity <dummy_stat_regs_wb_slave> analyzed. Unit <dummy_stat_regs_wb_slave> generated.
+
+Analyzing Entity <dummy_ctrl_regs_wb_slave> in library <work> (Architecture <syn>).
+INFO:Xst:1561 - "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/dummy_ctrl_regs.vhd" line 122: Mux is complete : default of case is discarded
+INFO:Xst:2679 - Register <ack_sreg<9>> in unit <dummy_ctrl_regs_wb_slave> has a constant value of 0 during circuit operation. The register is replaced by logic.
+Entity <dummy_ctrl_regs_wb_slave> analyzed. Unit <dummy_ctrl_regs_wb_slave> generated.
+
=========================================================================
* HDL Synthesis *
@@ -302,6 +317,47 @@ Entity <l2p_ser> analyzed. Unit <l2p_ser> generated.
Performing bidirectional port resolution...
INFO:Xst:2679 - Register <ack_sreg<8>> in unit <dma_controller_wb_slave> has a constant value of 0 during circuit operation. The register is replaced by logic.
+INFO:Xst:2679 - Register <ack_sreg<8>> in unit <dummy_stat_regs_wb_slave> has a constant value of 0 during circuit operation. The register is replaced by logic.
+INFO:Xst:2679 - Register <ack_sreg<8>> in unit <dummy_ctrl_regs_wb_slave> has a constant value of 0 during circuit operation. The register is replaced by logic.
+
+Synthesizing Unit <dummy_stat_regs_wb_slave>.
+ Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/dummy_stat_regs.vhd".
+WARNING:Xst:646 - Signal <wrdata_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <wr_int> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <rd_int> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <bwsel_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <allzeros> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <allones> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+ Found 1-bit register for signal <ack_in_progress>.
+ Found 8-bit register for signal <ack_sreg<7:0>>.
+ Found 32-bit register for signal <rddata_reg>.
+ Found 32-bit 4-to-1 multiplexer for signal <rddata_reg$mux0000> created at line 82.
+ Summary:
+ inferred 41 D-type flip-flop(s).
+ inferred 32 Multiplexer(s).
+Unit <dummy_stat_regs_wb_slave> synthesized.
+
+
+Synthesizing Unit <dummy_ctrl_regs_wb_slave>.
+ Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/dummy_ctrl_regs.vhd".
+WARNING:Xst:646 - Signal <wr_int> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <rd_int> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <bwsel_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <allzeros> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <allones> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+ Found 1-bit register for signal <ack_in_progress>.
+ Found 8-bit register for signal <ack_sreg<7:0>>.
+ Found 32-bit register for signal <dummy_reg_1_int>.
+ Found 32-bit register for signal <dummy_reg_2_int>.
+ Found 32-bit register for signal <dummy_reg_3_int>.
+ Found 32-bit register for signal <dummy_reg_led_int>.
+ Found 32-bit register for signal <rddata_reg>.
+ Found 32-bit 4-to-1 multiplexer for signal <rddata_reg$mux0000> created at line 90.
+ Summary:
+ inferred 169 D-type flip-flop(s).
+ inferred 32 Multiplexer(s).
+Unit <dummy_ctrl_regs_wb_slave> synthesized.
+
Synthesizing Unit <p2l_decode32>.
Related source file is "/home/mcattin/projects/GN4124_core/hdl/gn4124core/design/rtl/p2l_decode32.vhd".
@@ -482,7 +538,8 @@ WARNING:Xst:647 - Input <pd_wbm_addr_i<1>> is never used. This port will be pres
WARNING:Xst:647 - Input <pd_wbm_hdr_length_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pd_wbm_data_last_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <pd_wbm_be_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:646 - Signal <s_wb_periph_select<15:2>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <wb_adr_t<30:18>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <s_wb_periph_select<3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <from_wb_fifo_full> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Found finite state machine <FSM_0> for signal <wishbone_current_state>.
-----------------------------------------------------------------------
@@ -520,29 +577,25 @@ WARNING:Xst:646 - Signal <from_wb_fifo_full> is assigned but never used. This un
Found 1-bit register for signal <from_wb_fifo_rd>.
Found 1-bit register for signal <from_wb_fifo_wr>.
Found 2-bit register for signal <p2l_cid>.
- Found 32-bit 4-to-1 multiplexer for signal <s_wb_dat_i_muxed>.
- Found 4-bit comparator less for signal <s_wb_dat_i_muxed$cmp_lt0000> created at line 473.
+ Found 2-bit comparator less for signal <s_wb_dat_i_muxed$cmp_lt0000> created at line 475.
Found 64-bit register for signal <to_wb_fifo_din>.
Found 1-bit register for signal <to_wb_fifo_rd>.
Found 1-bit register for signal <to_wb_fifo_wr>.
- Found 4-bit adder for signal <v_index$addsub0000> created at line 437.
- Found 4-bit adder for signal <v_index$addsub0001> created at line 437.
- Found 4-bit adder for signal <v_index$addsub0002> created at line 437.
+ Found 2-bit adder for signal <v_index$addsub0000> created at line 439.
Found 1-bit register for signal <wb_ack_t>.
Found 31-bit register for signal <wb_adr_t>.
Found 1-bit register for signal <wb_cyc_t>.
Found 32-bit register for signal <wb_dat_i_t>.
Found 32-bit register for signal <wb_dat_o_t>.
- Found 4-bit register for signal <wb_periph_addr>.
+ Found 2-bit register for signal <wb_periph_addr>.
Found 4-bit register for signal <wb_sel_t>.
Found 1-bit register for signal <wb_stb_t>.
Found 1-bit register for signal <wb_we_t>.
Summary:
inferred 2 Finite State Machine(s).
- inferred 244 D-type flip-flop(s).
- inferred 3 Adder/Subtractor(s).
+ inferred 242 D-type flip-flop(s).
+ inferred 1 Adder/Subtractor(s).
inferred 1 Comparator(s).
- inferred 32 Multiplexer(s).
Unit <wbmaster32> synthesized.
@@ -768,7 +821,6 @@ WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<17>> is never assigned.
WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<22>> is never assigned.
WARNING:Xst:2565 - Inout <MIC_DATA<3>> is never assigned.
WARNING:Xst:2565 - Inout <DES_DVB_ASI> is never assigned.
-WARNING:Xst:647 - Input <DEBUG> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1306 - Output <MIC_CLKA> is never assigned.
WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<18>> is never assigned.
WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<23>> is never assigned.
@@ -892,12 +944,11 @@ WARNING:Xst:647 - Input <SYS_CLK> is never used. This port will be preserved and
WARNING:Xst:2565 - Inout <MIC_DATA<2>> is never assigned.
WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<16>> is never assigned.
WARNING:Xst:2565 - Inout <CNTRL0_DDR2_DQ<21>> is never assigned.
-WARNING:Xst:646 - Signal <wb_we_o> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <wb_stb_o> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <wb_sel_o> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <wb_dat_o> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <wb_cyc_o<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <wb_adr_o> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <wb_adr<17:2>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <dummy_ctrl_reg_led<31:8>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <dummy_ctrl_reg_3> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <dummy_ctrl_reg_2> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <dummy_ctrl_reg_1> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dma_sel_o> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dma_adr_o<31:11>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Found 1-bit register for signal <dma_ack_i>.
@@ -910,36 +961,36 @@ Unit <gw_wrapper> synthesized.
HDL Synthesis Report
Macro Statistics
-# Adders/Subtractors : 10
+# Adders/Subtractors : 8
11-bit subtractor : 1
+ 2-bit adder : 1
30-bit adder : 1
30-bit subtractor : 2
32-bit adder : 1
- 4-bit adder : 3
7-bit subtractor : 2
# Counters : 8
11-bit down counter : 1
30-bit down counter : 1
30-bit up counter : 2
7-bit up counter : 4
-# Registers : 432
- 1-bit register : 345
+# Registers : 456
+ 1-bit register : 363
10-bit register : 3
11-bit register : 1
16-bit register : 1
- 2-bit register : 7
+ 2-bit register : 8
3-bit register : 1
30-bit register : 2
31-bit register : 1
- 32-bit register : 64
- 4-bit register : 7
+ 32-bit register : 70
+ 4-bit register : 6
# Comparators : 9
11-bit comparator lessequal : 3
+ 2-bit comparator less : 1
30-bit comparator greater : 3
- 4-bit comparator less : 1
7-bit comparator equal : 2
-# Multiplexers : 3
- 32-bit 4-to-1 multiplexer : 3
+# Multiplexers : 4
+ 32-bit 4-to-1 multiplexer : 4
=========================================================================
@@ -1015,22 +1066,23 @@ Loading core <fifo_32x512> for timing and area information for instance <cmp_dat
Loading core <fifo_64x512> for timing and area information for instance <cmp_to_wb_fifo>.
INFO:Xst:2261 - The FF/Latch <addr_fifo_din_30> in Unit <cmp_l2p_dma_master> is equivalent to the following FF/Latch, which will be removed : <addr_fifo_din_31>
INFO:Xst:2261 - The FF/Latch <p2l_dma_adr_o_30> in Unit <cmp_p2l_dma_master> is equivalent to the following FF/Latch, which will be removed : <p2l_dma_adr_o_31>
-WARNING:Xst:1710 - FF/Latch <p2l_dma_adr_o_30> (without init value) has a constant value of 0 in block <cmp_p2l_dma_master>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <addr_fifo_din_30> (without init value) has a constant value of 0 in block <cmp_l2p_dma_master>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ack_sreg_7> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_31> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_30> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_29> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_28> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_27> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_26> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_25> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_24> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_23> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_22> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_21> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_20> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_19> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_21> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_22> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_23> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_24> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_25> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_26> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_27> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_28> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_29> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_30> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_31> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <ack_sreg_7> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <addr_fifo_din_30> (without init value) has a constant value of 0 in block <cmp_l2p_dma_master>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <p2l_dma_adr_o_30> (without init value) has a constant value of 0 in block <cmp_p2l_dma_master>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <ack_sreg_7> (without init value) has a constant value of 0 in block <cmp_dummy_stat_regs>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <ack_sreg_7> (without init value) has a constant value of 0 in block <cmp_dummy_ctrl_regs>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_3> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_4> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_5> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
@@ -1047,7 +1099,20 @@ WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_15> (without init value) has a co
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_16> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_17> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_18> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_19> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <cmp_dummy_stat_regs>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <cmp_dummy_ctrl_regs>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_5> (without init value) has a constant value of 0 in block <cmp_dummy_stat_regs>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_5> (without init value) has a constant value of 0 in block <cmp_dummy_ctrl_regs>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_4> (without init value) has a constant value of 0 in block <cmp_dummy_ctrl_regs>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_4> (without init value) has a constant value of 0 in block <cmp_dummy_stat_regs>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_3> (without init value) has a constant value of 0 in block <cmp_dummy_stat_regs>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_3> (without init value) has a constant value of 0 in block <cmp_dummy_ctrl_regs>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_2> (without init value) has a constant value of 0 in block <cmp_dummy_stat_regs>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_2> (without init value) has a constant value of 0 in block <cmp_dummy_ctrl_regs>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_1> (without init value) has a constant value of 0 in block <cmp_dummy_stat_regs>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_1> (without init value) has a constant value of 0 in block <cmp_dummy_ctrl_regs>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <wb_adr_t_4> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_5> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_6> of sequential type is unconnected in block <cmp_wbmaster32>.
@@ -1060,8 +1125,6 @@ WARNING:Xst:2677 - Node <wb_adr_t_12> of sequential type is unconnected in block
WARNING:Xst:2677 - Node <wb_adr_t_13> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_14> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_15> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_16> of sequential type is unconnected in block <cmp_wbmaster32>.
-WARNING:Xst:2677 - Node <wb_adr_t_17> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_18> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_19> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_20> of sequential type is unconnected in block <cmp_wbmaster32>.
@@ -1071,56 +1134,91 @@ WARNING:Xst:2677 - Node <wb_adr_t_23> of sequential type is unconnected in block
WARNING:Xst:2677 - Node <wb_adr_t_24> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_25> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <wb_adr_t_26> of sequential type is unconnected in block <cmp_wbmaster32>.
+WARNING:Xst:2677 - Node <wb_adr_t_27> of sequential type is unconnected in block <cmp_wbmaster32>.
+WARNING:Xst:2677 - Node <wb_adr_t_28> of sequential type is unconnected in block <cmp_wbmaster32>.
+WARNING:Xst:2677 - Node <wb_adr_t_29> of sequential type is unconnected in block <cmp_wbmaster32>.
+WARNING:Xst:2677 - Node <wb_adr_t_30> of sequential type is unconnected in block <cmp_wbmaster32>.
WARNING:Xst:2677 - Node <dma_ctrl_carrier_addr_o_0> of sequential type is unconnected in block <cmp_dma_controller>.
WARNING:Xst:2677 - Node <dma_ctrl_carrier_addr_o_1> of sequential type is unconnected in block <cmp_dma_controller>.
WARNING:Xst:2677 - Node <dma_ctrl_len_o_0> of sequential type is unconnected in block <cmp_dma_controller>.
WARNING:Xst:2677 - Node <dma_ctrl_len_o_1> of sequential type is unconnected in block <cmp_dma_controller>.
WARNING:Xst:2404 - FFs/Latches <addr_fifo_din<31:30>> (without init value) have a constant value of 0 in block <l2p_dma_master>.
WARNING:Xst:2404 - FFs/Latches <p2l_dma_adr_o<31:30>> (without init value) have a constant value of 0 in block <p2l_dma_master>.
+WARNING:Xst:2677 - Node <wb_adr_t_18> of sequential type is unconnected in block <wbmaster32>.
+WARNING:Xst:2677 - Node <wb_adr_t_19> of sequential type is unconnected in block <wbmaster32>.
+WARNING:Xst:2677 - Node <wb_adr_t_20> of sequential type is unconnected in block <wbmaster32>.
+WARNING:Xst:2677 - Node <wb_adr_t_21> of sequential type is unconnected in block <wbmaster32>.
+WARNING:Xst:2677 - Node <wb_adr_t_22> of sequential type is unconnected in block <wbmaster32>.
+WARNING:Xst:2677 - Node <wb_adr_t_23> of sequential type is unconnected in block <wbmaster32>.
+WARNING:Xst:2677 - Node <wb_adr_t_24> of sequential type is unconnected in block <wbmaster32>.
+WARNING:Xst:2677 - Node <wb_adr_t_25> of sequential type is unconnected in block <wbmaster32>.
+WARNING:Xst:2677 - Node <wb_adr_t_26> of sequential type is unconnected in block <wbmaster32>.
+WARNING:Xst:2677 - Node <wb_adr_t_27> of sequential type is unconnected in block <wbmaster32>.
+WARNING:Xst:2677 - Node <wb_adr_t_28> of sequential type is unconnected in block <wbmaster32>.
+WARNING:Xst:2677 - Node <wb_adr_t_29> of sequential type is unconnected in block <wbmaster32>.
+WARNING:Xst:2677 - Node <wb_adr_t_30> of sequential type is unconnected in block <wbmaster32>.
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# FSMs : 5
-# Adders/Subtractors : 10
+# Adders/Subtractors : 8
11-bit subtractor : 1
2-bit adder : 1
- 3-bit adder : 1
30-bit adder : 1
30-bit subtractor : 2
32-bit adder : 1
- 4-bit adder : 1
7-bit subtractor : 2
# Counters : 8
11-bit down counter : 1
30-bit down counter : 1
30-bit up counter : 2
7-bit up counter : 4
-# Registers : 2582
- Flip-Flops : 2582
+# Registers : 2777
+ Flip-Flops : 2777
# Comparators : 9
11-bit comparator lessequal : 3
+ 2-bit comparator less : 1
30-bit comparator greater : 3
- 4-bit comparator less : 1
7-bit comparator equal : 2
-# Multiplexers : 3
- 32-bit 4-to-1 multiplexer : 3
+# Multiplexers : 4
+ 32-bit 4-to-1 multiplexer : 4
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
+WARNING:Xst:1710 - FF/Latch <ack_sreg_7> (without init value) has a constant value of 0 in block <dummy_stat_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <dummy_stat_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_5> (without init value) has a constant value of 0 in block <dummy_stat_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_4> (without init value) has a constant value of 0 in block <dummy_stat_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_3> (without init value) has a constant value of 0 in block <dummy_stat_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_2> (without init value) has a constant value of 0 in block <dummy_stat_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_1> (without init value) has a constant value of 0 in block <dummy_stat_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <ack_sreg_7> (without init value) has a constant value of 0 in block <dummy_ctrl_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <dummy_ctrl_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_5> (without init value) has a constant value of 0 in block <dummy_ctrl_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_4> (without init value) has a constant value of 0 in block <dummy_ctrl_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_3> (without init value) has a constant value of 0 in block <dummy_ctrl_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_2> (without init value) has a constant value of 0 in block <dummy_ctrl_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_1> (without init value) has a constant value of 0 in block <dummy_ctrl_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ack_sreg_7> (without init value) has a constant value of 0 in block <dma_controller_wb_slave>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <dma_controller_wb_slave>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <l2p_dma_sel_o_0> in Unit <l2p_dma_master> is equivalent to the following 4 FFs/Latches, which will be removed : <l2p_dma_sel_o_1> <l2p_dma_sel_o_2> <l2p_dma_sel_o_3> <l2p_dma_stb_o>
INFO:Xst:2261 - The FF/Latch <p2l_dma_sel_o_0> in Unit <p2l_dma_master> is equivalent to the following 4 FFs/Latches, which will be removed : <p2l_dma_sel_o_1> <p2l_dma_sel_o_2> <p2l_dma_sel_o_3> <p2l_dma_stb_o>
INFO:Xst:2261 - The FF/Latch <dma_stat_int_read_3> in Unit <dma_controller_wb_slave> is equivalent to the following 28 FFs/Latches, which will be removed : <dma_stat_int_read_4> <dma_stat_int_read_5> <dma_stat_int_read_6> <dma_stat_int_read_7> <dma_stat_int_read_8> <dma_stat_int_read_9> <dma_stat_int_read_10> <dma_stat_int_read_11> <dma_stat_int_read_12> <dma_stat_int_read_13> <dma_stat_int_read_14> <dma_stat_int_read_15> <dma_stat_int_read_16> <dma_stat_int_read_17> <dma_stat_int_read_18> <dma_stat_int_read_19> <dma_stat_int_read_20> <dma_stat_int_read_21> <dma_stat_int_read_22> <dma_stat_int_read_23> <dma_stat_int_read_24> <dma_stat_int_read_25> <dma_stat_int_read_26> <dma_stat_int_read_27> <dma_stat_int_read_28> <dma_stat_int_read_29> <dma_stat_int_read_30> <dma_stat_int_read_31>
WARNING:Xst:1710 - FF/Latch <dma_stat_int_read_3> (without init value) has a constant value of 0 in block <dma_controller_wb_slave>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <rddata_reg_8> (without init value) has a constant value of 0 in block <dummy_stat_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_24> (without init value) has a constant value of 0 in block <dummy_stat_regs_wb_slave>. This FF/Latch will be trimmed during the optimization process.
Optimizing unit <gw_wrapper> ...
+Optimizing unit <dummy_stat_regs_wb_slave> ...
+
+Optimizing unit <dummy_ctrl_regs_wb_slave> ...
+
Optimizing unit <p2l_decode32> ...
Optimizing unit <l2p_arbiter> ...
@@ -1265,17 +1363,6 @@ WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_12> of sequenti
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_13> of sequential type is unconnected in block <gw_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_14> of sequential type is unconnected in block <gw_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_15> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_16> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_17> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_18> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_19> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_20> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_21> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_22> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_23> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_24> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_25> of sequential type is unconnected in block <gw_wrapper>.
-WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_wbmaster32/wb_adr_t_26> of sequential type is unconnected in block <gw_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_0> of sequential type is unconnected in block <gw_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_1> of sequential type is unconnected in block <gw_wrapper>.
WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_hdr_length_2> of sequential type is unconnected in block <gw_wrapper>.
@@ -1305,7 +1392,7 @@ WARNING:Xst:2677 - Node <cmp_gn4124_core/cmp_p2l_decode32/p2l_addr_1> of sequent
Mapping all equations...
Building and optimizing final netlist ...
-Found area constraint ratio of 100 (+ 5) on block gw_wrapper, actual ratio is 20.
+Found area constraint ratio of 100 (+ 5) on block gw_wrapper, actual ratio is 22.
Forward register balancing over carry chain cmp_gn4124_core/cmp_dma_controller/dma_ctrl_current_state_cmp_eq0000_wg_cy<0>
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/rstblk/wr_rst_reg_1> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/rstblk/wr_rst_reg_0>
INFO:Xst:2260 - The FF/Latch <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i> in Unit <BU2> is equivalent to the following FF/Latch : <U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i>
@@ -1396,38 +1483,8 @@ Processing Unit <gw_wrapper> :
Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_nexth_lw has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_nexth_lw_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_nexth_lw_BRB1.
Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_nextl_lw has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_nextl_lw_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_nextl_lw_BRB1.
Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_lw has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_lw_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_lw_BRB1.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_0 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_0_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_0_BRB2 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_0_BRB3.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_1 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_1_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_1_BRB2 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_1_BRB3.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_10 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_10_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_10_BRB2.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_11 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_11_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_11_BRB2.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_12 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_12_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_12_BRB2.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_13 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_13_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_13_BRB2.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_14 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_14_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_14_BRB2.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_15 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_15_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_15_BRB2.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_16 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_16_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_16_BRB2.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_17 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_17_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_17_BRB2.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_18 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_18_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_18_BRB2.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_19 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_19_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_19_BRB2.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_2 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_2_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_2_BRB2 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_2_BRB3.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_20 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_20_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_20_BRB2.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_21 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_21_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_21_BRB2.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_22 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_22_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_22_BRB2.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_23 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_23_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_23_BRB2.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_24 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_24_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_24_BRB2.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_25 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_25_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_25_BRB2.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_26 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_26_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_26_BRB2.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_27 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_27_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_27_BRB2.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_28 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_28_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_28_BRB2.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_29 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_29_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_29_BRB2.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_3 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_3_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_3_BRB2.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_30 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_30_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_30_BRB2.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_31 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_31_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_31_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_31_BRB2.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_4 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_4_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_4_BRB2.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_5 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_5_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_5_BRB2.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_6 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_6_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_6_BRB2.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_7 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_7_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_7_BRB2.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_8 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_8_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_8_BRB2.
- Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_9 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_9_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_9_BRB2.
+ Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_24 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_24_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_24_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_24_BRB2 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_24_BRB3.
+ Register(s) cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_8 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_8_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_8_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rddata_reg_8_BRB3.
Register(s) cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg_0 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg_0_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg_0_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg_0_BRB2.
Register(s) cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg_1 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg_1_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_cstart_reg_1_BRB2.
Register(s) cmp_gn4124_core/cmp_dma_controller/dma_len_reg_0 has(ve) been backward balanced into : cmp_gn4124_core/cmp_dma_controller/dma_len_reg_0_BRB0 cmp_gn4124_core/cmp_dma_controller/dma_len_reg_0_BRB1 cmp_gn4124_core/cmp_dma_controller/dma_len_reg_0_BRB2.
@@ -1465,7 +1522,7 @@ Processing Unit <gw_wrapper> :
Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_8 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_8_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_8_BRB1 .
Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_9 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_9_BRB0 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_9_BRB1 .
Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_dframe_o has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_dframe_o_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_dframe_o_BRB2 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_dframe_o_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_dframe_o_BRB4 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_dframe_o_BRB5.
- Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_valid_o has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_valid_o_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_valid_o_BRB4 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_valid_o_BRB5.
+ Register(s) cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_valid_o has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_valid_o_BRB1 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_valid_o_BRB3 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_valid_o_BRB5.
Register(s) cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_rd has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_rd_BRB0 cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_rd_BRB1 cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_rd_BRB3 cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_rd_BRB4 cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_rd_BRB5 cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_rd_BRB6.
Register(s) cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_20 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_20_BRB1 cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_20_BRB2.
Register(s) cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_21 has(ve) been backward balanced into : cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_21_BRB1 cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_21_BRB2.
@@ -1518,45 +1575,51 @@ Processing Unit <gw_wrapper> :
Register(s) cmp_gn4124_core/cmp_p2l_dma_master/l2p_len_cnt_27 has(ve) been backward balanced into : cmp_gn4124_core/cmp_p2l_dma_master/l2p_len_cnt_27_BRB0 cmp_gn4124_core/cmp_p2l_dma_master/l2p_len_cnt_27_BRB1 .
Register(s) cmp_gn4124_core/cmp_p2l_dma_master/l2p_len_cnt_28 has(ve) been backward balanced into : cmp_gn4124_core/cmp_p2l_dma_master/l2p_len_cnt_28_BRB0 cmp_gn4124_core/cmp_p2l_dma_master/l2p_len_cnt_28_BRB1 .
Register(s) cmp_gn4124_core/cmp_p2l_dma_master/l2p_len_cnt_29 has(ve) been backward balanced into : cmp_gn4124_core/cmp_p2l_dma_master/l2p_len_cnt_29_BRB0 cmp_gn4124_core/cmp_p2l_dma_master/l2p_len_cnt_29_BRB1 cmp_gn4124_core/cmp_p2l_dma_master/l2p_len_cnt_29_BRB2.
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_0 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_0_BRB0 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_0_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_0_BRB2.
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_1 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_1_BRB1 .
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_10 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_10_BRB1 .
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_11 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_11_BRB1 .
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_12 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_12_BRB1 .
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_13 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_13_BRB1 .
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_14 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_14_BRB1 .
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_15 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_15_BRB1 .
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_16 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_16_BRB1 .
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_17 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_17_BRB1 .
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_18 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_18_BRB1 .
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_19 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_19_BRB1 .
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_2 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_2_BRB1 .
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_20 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_20_BRB1 .
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_21 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_21_BRB1 .
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_22 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_22_BRB1 .
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_23 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_23_BRB1 .
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_24 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_24_BRB1 .
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_25 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_25_BRB1 .
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_26 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_26_BRB1 .
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_27 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_27_BRB1 .
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_28 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_28_BRB1 .
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_29 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_29_BRB1 .
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_3 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_3_BRB1 .
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_30 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_30_BRB1 .
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_31 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_31_BRB1 .
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_4 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_4_BRB1 .
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_5 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_5_BRB1 .
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_6 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_6_BRB1 .
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_7 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_7_BRB1 .
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_8 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_8_BRB1 .
- Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_9 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_9_BRB1 .
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_0 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_0_BRB0 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_0_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_0_BRB2 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_0_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_1 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_1_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_1_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_10 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_10_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_10_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_11 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_11_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_11_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_12 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_12_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_12_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_13 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_13_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_13_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_14 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_14_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_14_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_15 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_15_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_15_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_16 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_16_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_16_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_17 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_17_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_17_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_18 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_18_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_18_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_19 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_19_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_19_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_2 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_2_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_2_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_20 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_20_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_20_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_21 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_21_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_21_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_22 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_22_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_22_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_23 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_23_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_23_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_24 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_24_BRB2 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_24_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_25 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_25_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_25_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_26 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_26_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_26_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_27 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_27_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_27_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_28 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_28_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_28_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_29 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_29_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_29_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_3 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_3_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_3_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_30 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_30_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_30_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_31 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_31_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_31_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_4 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_4_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_4_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_5 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_5_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_5_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_6 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_6_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_6_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_7 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_7_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_7_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_8 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_8_BRB0 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_8_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_8_BRB2 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_8_BRB3.
+ Register(s) cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_9 has(ve) been backward balanced into : cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_9_BRB1 cmp_gn4124_core/cmp_wbmaster32/wb_dat_i_t_9_BRB3.
Unit <gw_wrapper> processed.
Replicating register cmp_gn4124_core/cmp_l2p_dma_master/l2p_edb_o to handle IOB=TRUE attribute
Replicating register cmp_gn4124_core/cmp_p2l_dma_master/rx_error_o to handle IOB=TRUE attribute
+Replicating register cmp_dummy_ctrl_regs/dummy_reg_led_int_7 to handle IOB=TRUE attribute
+Replicating register cmp_dummy_ctrl_regs/dummy_reg_led_int_6 to handle IOB=TRUE attribute
+Replicating register cmp_dummy_ctrl_regs/dummy_reg_led_int_5 to handle IOB=TRUE attribute
+Replicating register cmp_dummy_ctrl_regs/dummy_reg_led_int_4 to handle IOB=TRUE attribute
+Replicating register cmp_dummy_ctrl_regs/dummy_reg_led_int_3 to handle IOB=TRUE attribute
+Replicating register cmp_dummy_ctrl_regs/dummy_reg_led_int_2 to handle IOB=TRUE attribute
+Replicating register cmp_dummy_ctrl_regs/dummy_reg_led_int_1 to handle IOB=TRUE attribute
+Replicating register cmp_dummy_ctrl_regs/dummy_reg_led_int_0 to handle IOB=TRUE attribute
FlipFlop cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_in_progress has been replicated 1 time(s)
-FlipFlop cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_current_state_FSM_FFd2 has been replicated 1 time(s)
-FlipFlop cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_current_state_FSM_FFd3 has been replicated 1 time(s)
Final Macro Processing ...
@@ -1570,8 +1633,8 @@ Unit <gw_wrapper> processed.
Final Register Report
Macro Statistics
-# Registers : 2734
- Flip-Flops : 2734
+# Registers : 2933
+ Flip-Flops : 2933
# Shift Registers : 3
4-bit shift register : 3
@@ -1602,30 +1665,30 @@ Design Statistics
# IOs : 273
Cell Usage :
-# BELS : 3415
+# BELS : 3658
# GND : 7
-# INV : 51
+# INV : 53
# LUT1 : 149
-# LUT2 : 380
-# LUT2_D : 10
+# LUT2 : 388
+# LUT2_D : 8
# LUT2_L : 22
-# LUT3 : 699
+# LUT3 : 822
# LUT3_D : 37
-# LUT3_L : 20
-# LUT4 : 871
-# LUT4_D : 39
-# LUT4_L : 182
+# LUT3_L : 34
+# LUT4 : 946
+# LUT4_D : 35
+# LUT4_L : 168
# MUXCY : 573
-# MUXF5 : 21
+# MUXF5 : 62
# VCC : 7
# XORCY : 347
-# FlipFlops/Latches : 3557
-# FD : 67
+# FlipFlops/Latches : 3756
+# FD : 70
# FDC : 1022
-# FDCE : 2190
+# FDCE : 2390
# FDDRRSE : 1
-# FDE : 126
-# FDP : 67
+# FDE : 93
+# FDP : 96
# FDPE : 50
# IFDDRRSE : 18
# OFDDRRSE : 16
@@ -1635,8 +1698,8 @@ Cell Usage :
# SRL16 : 3
# Clock Buffers : 4
# BUFG : 4
-# IO Buffers : 37
-# IBUF : 6
+# IO Buffers : 45
+# IBUF : 14
# IBUFDS : 1
# IBUFGDS : 2
# OBUF : 27
@@ -1648,14 +1711,14 @@ Device utilization summary:
Selected Device : 3s1400afg484-5
- Number of Slices: 2364 out of 11264 20%
- Number of Slice Flip Flops: 3548 out of 22528 15%
- Number of 4 input LUTs: 2463 out of 22528 10%
- Number used as logic: 2460
+ Number of Slices: 2510 out of 11264 22%
+ Number of Slice Flip Flops: 3739 out of 22528 16%
+ Number of 4 input LUTs: 2665 out of 22528 11%
+ Number used as logic: 2662
Number used as Shift registers: 3
Number of IOs: 273
- Number of bonded IOBs: 71 out of 375 18%
- IOB Flip Flops: 9
+ Number of bonded IOBs: 79 out of 375 21%
+ IOB Flip Flops: 17
Number of BRAMs: 11 out of 32 34%
Number of GCLKs: 4 out of 24 16%
@@ -1680,9 +1743,9 @@ Clock Information:
-----------------------------------+-----------------------------------------------------------------------------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+-----------------------------------------------------------------------------------------------+-------+
-L_CLKp | IBUFDS+BUFG | 977 |
+L_CLKp | IBUFDS+BUFG | 1178 |
cmp_test_ram/BU2/dbiterr | NONE(cmp_test_ram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[3].ram.r/s3a_init.ram/dpram.ram)| 4 |
-P2L_CLKp | IBUFGDS+BUFG | 2583 |
+P2L_CLKp | IBUFGDS+BUFG | 2581 |
P2L_CLKn | IBUFGDS+BUFG | 53 |
-----------------------------------+-----------------------------------------------------------------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
@@ -1692,12 +1755,13 @@ Asynchronous Control Signals Information:
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+-------+
Control Signal | Buffer(FF name) | Load |
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------+-------+
-cmp_gn4124_core/rst_n_inv1_INV_0_1(cmp_gn4124_core/rst_n_inv1_INV_0_1:O) | NONE(cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_attrib_load_o) | 439 |
-cmp_gn4124_core/rst_n_inv1_INV_0_2(cmp_gn4124_core/rst_n_inv1_INV_0_2:O) | NONE(cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_in_progress) | 439 |
-cmp_gn4124_core/rst_n_inv1_INV_0_3(cmp_gn4124_core/rst_n_inv1_INV_0_3:O) | NONE(cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_0) | 439 |
-cmp_gn4124_core/rst_n_inv1_INV_0_5(cmp_gn4124_core/rst_n_inv1_INV_0_5:O) | NONE(cmp_gn4124_core/cmp_p2l_dma_master/completion_error) | 439 |
-cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rst_n_i_inv(cmp_gn4124_core/rst_n_inv1_INV_0:O) | NONE(cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_10_BRB1) | 436 |
-cmp_gn4124_core/rst_n_inv1_INV_0_4(cmp_gn4124_core/rst_n_inv1_INV_0_4:O) | NONE(cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr) | 405 |
+cmp_gn4124_core/rst_n_inv1_INV_0_5(cmp_gn4124_core/rst_n_inv1_INV_0_5:O) | NONE(cmp_gn4124_core/cmp_p2l_dma_master/completion_error) | 444 |
+cmp_gn4124_core/rst_n_inv1_INV_0_1(cmp_gn4124_core/rst_n_inv1_INV_0_1:O) | NONE(cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_attrib_load_o) | 443 |
+cmp_gn4124_core/rst_n_inv1_INV_0_2(cmp_gn4124_core/rst_n_inv1_INV_0_2:O) | NONE(cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_0) | 443 |
+cmp_gn4124_core/rst_n_inv1_INV_0_3(cmp_gn4124_core/rst_n_inv1_INV_0_3:O) | NONE(cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_0) | 443 |
+cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/rst_n_i_inv(cmp_gn4124_core/rst_n_inv1_INV_0:O) | NONE(cmp_gn4124_core/cmp_dma_controller/dma_attrib_reg_10_BRB1) | 441 |
+cmp_gn4124_core/rst_n_inv1_INV_0_4(cmp_gn4124_core/rst_n_inv1_INV_0_4:O) | NONE(cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr) | 410 |
+L_RST_N_inv(cmp_gn4124_core/rst_n_a_i_inv1_INV_0:O) | NONE(cmp_dummy_ctrl_regs/ack_in_progress) | 204 |
cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg<1>(cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_1:Q) | NONE(cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_1) | 45 |
cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg<1>(cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_1:Q) | NONE(cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_1) | 45 |
cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg<1>(cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_1:Q)| NONE(cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/diff_pntr_pad_1)| 45 |
@@ -1728,7 +1792,6 @@ cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/rstblk/rd_rst_comb(c
cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/rstblk/rst_d2(cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/rstblk/rst_d2:Q) | NONE(cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i) | 3 |
cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/rstblk/rd_rst_comb(cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/rstblk/rd_rst_comb1:O) | NONE(cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/rstblk/rd_rst_reg_0) | 3 |
cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/rstblk/rst_d2(cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/rstblk/rst_d2:Q) | NONE(cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/gl0.wr/gwas.gpf.wrpf/prog_full_i) | 3 |
-L_RST_N_inv(cmp_gn4124_core/rst_n_a_i_inv1_INV_0:O) | NONE(cmp_gn4124_core/rst_reg) | 2 |
cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/rstblk/wr_rst_comb(cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/rstblk/wr_rst_comb1:O) | NONE(cmp_gn4124_core/cmp_l2p_dma_master/cmp_addr_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_0) | 2 |
cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/rstblk/wr_rst_comb(cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/rstblk/wr_rst_comb1:O) | NONE(cmp_gn4124_core/cmp_l2p_dma_master/cmp_data_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_0) | 2 |
cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/rstblk/wr_rst_comb(cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/rstblk/wr_rst_comb1:O) | NONE(cmp_gn4124_core/cmp_p2l_dma_master/cmp_to_wb_fifo/BU2/U0/grf.rf/rstblk/wr_rst_reg_0) | 2 |
@@ -1740,8 +1803,8 @@ Timing Summary:
---------------
Speed Grade: -5
- Minimum period: 5.938ns (Maximum Frequency: 168.415MHz)
- Minimum input arrival time before clock: 1.378ns
+ Minimum period: 6.966ns (Maximum Frequency: 143.550MHz)
+ Minimum input arrival time before clock: 2.030ns
Maximum output required time after clock: 6.297ns
Maximum combinational path delay: No path found
@@ -1751,53 +1814,74 @@ All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'L_CLKp'
- Clock period: 5.780ns (frequency: 173.000MHz)
- Total number of paths / destination ports: 9215 / 1800
+ Clock period: 6.966ns (frequency: 143.550MHz)
+ Total number of paths / destination ports: 10717 / 2168
-------------------------------------------------------------------------
-Delay: 5.780ns (Levels of Logic = 4)
- Source: cmp_gn4124_core/cmp_wbmaster32/wb_cyc_t (FF)
+Delay: 6.966ns (Levels of Logic = 5)
+ Source: cmp_gn4124_core/cmp_wbmaster32/wb_ack_t (FF)
Destination: cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_nexth_lw_delay (FF)
Source Clock: L_CLKp rising
Destination Clock: L_CLKp rising
- Data Path: cmp_gn4124_core/cmp_wbmaster32/wb_cyc_t to cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_nexth_lw_delay
+ Data Path: cmp_gn4124_core/cmp_wbmaster32/wb_ack_t to cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_nexth_lw_delay
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
- FDC:C->Q 2 0.495 0.488 cmp_gn4124_core/cmp_wbmaster32/wb_cyc_t (cmp_gn4124_core/cmp_wbmaster32/wb_cyc_t)
- LUT4_D:I0->O 6 0.561 0.677 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_5_mux0003123 (cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_5_mux0003123)
- LUT3:I0->O 11 0.561 0.795 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_cstart_lw_read_in_progress_not000111 (cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/N34)
- LUT4:I3->O 3 0.561 0.474 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_cstart_rwsel_not00011 (cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_cstart_rwsel_not0001)
- LUT3:I2->O 3 0.561 0.451 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_cstart_lw_not00011 (cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_cstart_lw_not0001)
- FDCE:CE 0.156 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_cstart_lw_delay
+ FDC:C->Q 8 0.495 0.666 cmp_gn4124_core/cmp_wbmaster32/wb_ack_t (cmp_gn4124_core/cmp_wbmaster32/wb_ack_t)
+ LUT3:I2->O 1 0.561 0.359 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_5_mux00031_SW0 (N269)
+ LUT4:I3->O 11 0.561 0.859 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/ack_sreg_5_mux00031 (cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/N42)
+ LUT2:I1->O 9 0.562 0.699 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_cstart_lw_read_in_progress_not000111 (cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/N34)
+ LUT4:I3->O 3 0.561 0.474 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_rwsel_not00011 (cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_rwsel_not0001)
+ LUT3:I2->O 3 0.561 0.451 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_lw_delay_not00011 (cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_lw_delay_not0001)
+ FDCE:CE 0.156 cmp_gn4124_core/cmp_dma_controller/dma_controller_wb_slave_0/dma_stat_lw_delay
----------------------------------------
- Total 5.780ns (2.895ns logic, 2.885ns route)
- (50.1% logic, 49.9% route)
+ Total 6.966ns (3.457ns logic, 3.509ns route)
+ (49.6% logic, 50.4% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'P2L_CLKp'
- Clock period: 5.938ns (frequency: 168.415MHz)
- Total number of paths / destination ports: 26478 / 4142
+ Clock period: 5.729ns (frequency: 174.545MHz)
+ Total number of paths / destination ports: 26455 / 4140
-------------------------------------------------------------------------
-Delay: 5.938ns (Levels of Logic = 4)
- Source: cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_current_state_FSM_FFd1 (FF)
- Destination: cmp_gn4124_core/cmp_p2l_dma_master/l2p_len_cnt_15 (FF)
+Delay: 5.729ns (Levels of Logic = 4)
+ Source: cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_2 (FF)
+ Destination: cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_0 (FF)
Source Clock: P2L_CLKp rising
Destination Clock: P2L_CLKp rising
- Data Path: cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_current_state_FSM_FFd1 to cmp_gn4124_core/cmp_p2l_dma_master/l2p_len_cnt_15
+ Data Path: cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_2 to cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
- FDC:C->Q 19 0.495 0.945 cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_current_state_FSM_FFd1 (cmp_gn4124_core/cmp_p2l_dma_master/p2l_dma_current_state_FSM_FFd1)
- LUT3_D:I2->O 6 0.561 0.592 cmp_gn4124_core/cmp_p2l_dma_master/completion_error_mux000011 (cmp_gn4124_core/cmp_p2l_dma_master/N6)
- LUT3:I2->O 69 0.561 1.085 cmp_gn4124_core/cmp_p2l_dma_master/pdm_arb_req_o_mux000021_2 (cmp_gn4124_core/cmp_p2l_dma_master/pdm_arb_req_o_mux000021_1)
- LUT4:I3->O 1 0.561 0.380 cmp_gn4124_core/cmp_p2l_dma_master/l2p_len_cnt_mux0001<17>_SW0 (N174)
- LUT3:I2->O 1 0.561 0.000 cmp_gn4124_core/cmp_p2l_dma_master/l2p_len_cnt_mux0001<17> (cmp_gn4124_core/cmp_p2l_dma_master/l2p_len_cnt_mux0001<17>)
- FDC:D 0.197 cmp_gn4124_core/cmp_p2l_dma_master/l2p_len_cnt_15
+ FDCE:C->Q 2 0.495 0.488 cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_2 (cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_2)
+ LUT4:I0->O 1 0.561 0.423 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and000015 (cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and000015)
+ LUT4:I1->O 2 0.562 0.446 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000130 (cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000130)
+ LUT3:I1->O 2 0.562 0.403 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000198 (cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr_and0000)
+ LUT3:I2->O 30 0.561 1.072 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and00002 (cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000)
+ FDE:CE 0.156 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_0
----------------------------------------
- Total 5.938ns (2.936ns logic, 3.002ns route)
- (49.4% logic, 50.6% route)
+ Total 5.729ns (2.897ns logic, 2.832ns route)
+ (50.6% logic, 49.4% route)
+
+=========================================================================
+Timing constraint: Default OFFSET IN BEFORE for Clock 'L_CLKp'
+ Total number of paths / destination ports: 8 / 8
+-------------------------------------------------------------------------
+Offset: 2.030ns (Levels of Logic = 2)
+ Source: DEBUG<7> (PAD)
+ Destination: cmp_dummy_stat_regs/rddata_reg_7 (FF)
+ Destination Clock: L_CLKp rising
+
+ Data Path: DEBUG<7> to cmp_dummy_stat_regs/rddata_reg_7
+ Gate Net
+ Cell:in->out fanout Delay Delay Logical Name (Net Name)
+ ---------------------------------------- ------------
+ IBUF:I->O 1 0.824 0.357 DEBUG_7_IBUF (DEBUG_7_IBUF)
+ MUXF5:S->O 1 0.652 0.000 cmp_dummy_stat_regs/Mmux_rddata_reg_mux000054_f5 (cmp_dummy_stat_regs/rddata_reg_mux0000<7>)
+ FDCE:D 0.197 cmp_dummy_stat_regs/rddata_reg_7
+ ----------------------------------------
+ Total 2.030ns (1.673ns logic, 0.357ns route)
+ (82.4% logic, 17.6% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'P2L_CLKn'
@@ -1876,17 +1960,36 @@ Offset: 5.248ns (Levels of Logic = 1)
(93.2% logic, 6.8% route)
=========================================================================
+Timing constraint: Default OFFSET OUT AFTER for Clock 'L_CLKp'
+ Total number of paths / destination ports: 8 / 8
+-------------------------------------------------------------------------
+Offset: 5.248ns (Levels of Logic = 1)
+ Source: cmp_dummy_ctrl_regs/dummy_reg_led_int_7 (FF)
+ Destination: LED<7> (PAD)
+ Source Clock: L_CLKp rising
+
+ Data Path: cmp_dummy_ctrl_regs/dummy_reg_led_int_7 to LED<7>
+ Gate Net
+ Cell:in->out fanout Delay Delay Logical Name (Net Name)
+ ---------------------------------------- ------------
+ FDCE:C->Q 1 0.495 0.357 cmp_dummy_ctrl_regs/dummy_reg_led_int_7 (cmp_dummy_ctrl_regs/dummy_reg_led_int_7)
+ OBUF:I->O 4.396 LED_7_OBUF (LED<7>)
+ ----------------------------------------
+ Total 5.248ns (4.891ns logic, 0.357ns route)
+ (93.2% logic, 6.8% route)
+
+=========================================================================
-Total REAL time to Xst completion: 132.00 secs
-Total CPU time to Xst completion: 129.39 secs
+Total REAL time to Xst completion: 144.00 secs
+Total CPU time to Xst completion: 141.58 secs
-->
-Total memory usage is 198868 kilobytes
+Total memory usage is 201616 kilobytes
Number of errors : 0 ( 0 filtered)
-Number of warnings : 418 ( 0 filtered)
-Number of infos : 79 ( 0 filtered)
+Number of warnings : 462 ( 0 filtered)
+Number of infos : 85 ( 0 filtered)
diff --git a/hdl/gn4124core/gw_wrapper.twr b/hdl/gn4124core/gw_wrapper.twr
index e1298f2417373a3206daeb93c0c68b0781bd35a6..6267b4d62941cca1a7802a7030ef8bb7157bd7dd 100644
--- a/hdl/gn4124core/gw_wrapper.twr
+++ b/hdl/gn4124core/gw_wrapper.twr
@@ -157,177 +157,177 @@ Timing constraint: TS_U_TO_J = MAXDELAY FROM TIMEGRP "U_CLK" TO TIMEGRP "J_CLK"
18 paths analyzed, 18 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
- Maximum delay is 4.655ns.
+ Maximum delay is 5.537ns.
--------------------------------------------------------------------------------
-Paths for end point U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[10].I_NE0.U_TARGET (SLICE_X62Y124.CE), 1 path
+Paths for end point U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[9].I_NE0.U_TARGET (SLICE_X70Y75.CE), 1 path
--------------------------------------------------------------------------------
-Slack (setup paths): 10.345ns (requirement - (data path - clock path skew + uncertainty))
+Slack (setup paths): 9.463ns (requirement - (data path - clock path skew + uncertainty))
Source: U_icon_pro/U0/U_ICON/U_iDATA_CMD (FF)
- Destination: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[10].I_NE0.U_TARGET (FF)
+ Destination: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[9].I_NE0.U_TARGET (FF)
Requirement: 15.000ns
- Data Path Delay: 4.655ns (Levels of Logic = 1)
+ Data Path Delay: 5.537ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: U_icon_pro/U0/iUPDATE_OUT rising
Destination Clock: icon_control0<0> rising at 0.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path: U_icon_pro/U0/U_ICON/U_iDATA_CMD to U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[10].I_NE0.U_TARGET
+ Maximum Data Path: U_icon_pro/U0/U_ICON/U_iDATA_CMD to U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[9].I_NE0.U_TARGET
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X78Y143.YQ Tcko 0.596 U_icon_pro/U0/U_ICON/iDATA_CMD
U_icon_pro/U0/U_ICON/U_iDATA_CMD
- SLICE_X73Y130.G1 net (fanout=7) 2.059 U_icon_pro/U0/U_ICON/iDATA_CMD
- SLICE_X73Y130.Y Tilo 0.561 U_icon_pro/U0/U_ICON/U_CMD/iTARGET_CE
+ SLICE_X75Y105.G4 net (fanout=8) 2.361 U_icon_pro/U0/U_ICON/iDATA_CMD
+ SLICE_X75Y105.Y Tilo 0.561 U_icon_pro/U0/U_ICON/U_CMD/iTARGET_CE
U_icon_pro/U0/U_ICON/U_CMD/U_TARGET_CE
- SLICE_X62Y124.CE net (fanout=8) 1.284 U_icon_pro/U0/U_ICON/U_CMD/iTARGET_CE
- SLICE_X62Y124.CLK Tceck 0.155 U_icon_pro/U0/U_ICON/U_CMD/iTARGET<10>
- U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[10].I_NE0.U_TARGET
+ SLICE_X70Y75.CE net (fanout=7) 1.864 U_icon_pro/U0/U_ICON/U_CMD/iTARGET_CE
+ SLICE_X70Y75.CLK Tceck 0.155 U_icon_pro/U0/U_ICON/U_CMD/iTARGET<9>
+ U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[9].I_NE0.U_TARGET
------------------------------------------------- ---------------------------
- Total 4.655ns (1.312ns logic, 3.343ns route)
- (28.2% logic, 71.8% route)
+ Total 5.537ns (1.312ns logic, 4.225ns route)
+ (23.7% logic, 76.3% route)
--------------------------------------------------------------------------------
-Paths for end point U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[9].I_NE0.U_TARGET (SLICE_X62Y125.CE), 1 path
+Paths for end point U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[8].I_NE0.U_TARGET (SLICE_X71Y75.CE), 1 path
--------------------------------------------------------------------------------
-Slack (setup paths): 10.345ns (requirement - (data path - clock path skew + uncertainty))
+Slack (setup paths): 9.782ns (requirement - (data path - clock path skew + uncertainty))
Source: U_icon_pro/U0/U_ICON/U_iDATA_CMD (FF)
- Destination: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[9].I_NE0.U_TARGET (FF)
+ Destination: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[8].I_NE0.U_TARGET (FF)
Requirement: 15.000ns
- Data Path Delay: 4.655ns (Levels of Logic = 1)
+ Data Path Delay: 5.218ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: U_icon_pro/U0/iUPDATE_OUT rising
Destination Clock: icon_control0<0> rising at 0.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path: U_icon_pro/U0/U_ICON/U_iDATA_CMD to U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[9].I_NE0.U_TARGET
+ Maximum Data Path: U_icon_pro/U0/U_ICON/U_iDATA_CMD to U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[8].I_NE0.U_TARGET
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X78Y143.YQ Tcko 0.596 U_icon_pro/U0/U_ICON/iDATA_CMD
U_icon_pro/U0/U_ICON/U_iDATA_CMD
- SLICE_X73Y130.G1 net (fanout=7) 2.059 U_icon_pro/U0/U_ICON/iDATA_CMD
- SLICE_X73Y130.Y Tilo 0.561 U_icon_pro/U0/U_ICON/U_CMD/iTARGET_CE
+ SLICE_X75Y105.G4 net (fanout=8) 2.361 U_icon_pro/U0/U_ICON/iDATA_CMD
+ SLICE_X75Y105.Y Tilo 0.561 U_icon_pro/U0/U_ICON/U_CMD/iTARGET_CE
U_icon_pro/U0/U_ICON/U_CMD/U_TARGET_CE
- SLICE_X62Y125.CE net (fanout=8) 1.284 U_icon_pro/U0/U_ICON/U_CMD/iTARGET_CE
- SLICE_X62Y125.CLK Tceck 0.155 U_icon_pro/U0/U_ICON/U_CMD/iTARGET<9>
- U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[9].I_NE0.U_TARGET
+ SLICE_X71Y75.CE net (fanout=7) 1.545 U_icon_pro/U0/U_ICON/U_CMD/iTARGET_CE
+ SLICE_X71Y75.CLK Tceck 0.155 U_icon_pro/U0/U_ICON/U_CMD/iTARGET<8>
+ U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[8].I_NE0.U_TARGET
------------------------------------------------- ---------------------------
- Total 4.655ns (1.312ns logic, 3.343ns route)
- (28.2% logic, 71.8% route)
+ Total 5.218ns (1.312ns logic, 3.906ns route)
+ (25.1% logic, 74.9% route)
--------------------------------------------------------------------------------
-Paths for end point U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[8].I_NE0.U_TARGET (SLICE_X62Y125.CE), 1 path
+Paths for end point U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[10].I_NE0.U_TARGET (SLICE_X71Y75.CE), 1 path
--------------------------------------------------------------------------------
-Slack (setup paths): 10.345ns (requirement - (data path - clock path skew + uncertainty))
+Slack (setup paths): 9.782ns (requirement - (data path - clock path skew + uncertainty))
Source: U_icon_pro/U0/U_ICON/U_iDATA_CMD (FF)
- Destination: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[8].I_NE0.U_TARGET (FF)
+ Destination: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[10].I_NE0.U_TARGET (FF)
Requirement: 15.000ns
- Data Path Delay: 4.655ns (Levels of Logic = 1)
+ Data Path Delay: 5.218ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: U_icon_pro/U0/iUPDATE_OUT rising
Destination Clock: icon_control0<0> rising at 0.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path: U_icon_pro/U0/U_ICON/U_iDATA_CMD to U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[8].I_NE0.U_TARGET
+ Maximum Data Path: U_icon_pro/U0/U_ICON/U_iDATA_CMD to U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[10].I_NE0.U_TARGET
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X78Y143.YQ Tcko 0.596 U_icon_pro/U0/U_ICON/iDATA_CMD
U_icon_pro/U0/U_ICON/U_iDATA_CMD
- SLICE_X73Y130.G1 net (fanout=7) 2.059 U_icon_pro/U0/U_ICON/iDATA_CMD
- SLICE_X73Y130.Y Tilo 0.561 U_icon_pro/U0/U_ICON/U_CMD/iTARGET_CE
+ SLICE_X75Y105.G4 net (fanout=8) 2.361 U_icon_pro/U0/U_ICON/iDATA_CMD
+ SLICE_X75Y105.Y Tilo 0.561 U_icon_pro/U0/U_ICON/U_CMD/iTARGET_CE
U_icon_pro/U0/U_ICON/U_CMD/U_TARGET_CE
- SLICE_X62Y125.CE net (fanout=8) 1.284 U_icon_pro/U0/U_ICON/U_CMD/iTARGET_CE
- SLICE_X62Y125.CLK Tceck 0.155 U_icon_pro/U0/U_ICON/U_CMD/iTARGET<9>
- U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[8].I_NE0.U_TARGET
+ SLICE_X71Y75.CE net (fanout=7) 1.545 U_icon_pro/U0/U_ICON/U_CMD/iTARGET_CE
+ SLICE_X71Y75.CLK Tceck 0.155 U_icon_pro/U0/U_ICON/U_CMD/iTARGET<8>
+ U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[10].I_NE0.U_TARGET
------------------------------------------------- ---------------------------
- Total 4.655ns (1.312ns logic, 3.343ns route)
- (28.2% logic, 71.8% route)
+ Total 5.218ns (1.312ns logic, 3.906ns route)
+ (25.1% logic, 74.9% route)
--------------------------------------------------------------------------------
Hold Paths: TS_U_TO_J = MAXDELAY FROM TIMEGRP "U_CLK" TO TIMEGRP "J_CLK" 15 ns;
--------------------------------------------------------------------------------
-Paths for end point U_icon_pro/U0/U_ICON/U_SYNC/U_SYNC (SLICE_X75Y135.SR), 1 path
+Paths for end point U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[3].I_NE0.U_FDR (SLICE_X76Y117.SR), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 1.965ns (requirement - (clock path skew + uncertainty - data path))
+Slack (hold path): 2.000ns (requirement - (clock path skew + uncertainty - data path))
Source: U_icon_pro/U0/U_ICON/U_iDATA_CMD (FF)
- Destination: U_icon_pro/U0/U_ICON/U_SYNC/U_SYNC (FF)
+ Destination: U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[3].I_NE0.U_FDR (FF)
Requirement: 0.000ns
- Data Path Delay: 1.965ns (Levels of Logic = 0)
+ Data Path Delay: 2.000ns (Levels of Logic = 0)
Positive Clock Path Skew: 0.000ns
Source Clock: U_icon_pro/U0/iUPDATE_OUT rising
Destination Clock: icon_control0<0> rising at 0.000ns
Clock Uncertainty: 0.000ns
- Minimum Data Path: U_icon_pro/U0/U_ICON/U_iDATA_CMD to U_icon_pro/U0/U_ICON/U_SYNC/U_SYNC
+ Minimum Data Path: U_icon_pro/U0/U_ICON/U_iDATA_CMD to U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[3].I_NE0.U_FDR
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X78Y143.YQ Tcko 0.477 U_icon_pro/U0/U_ICON/iDATA_CMD
U_icon_pro/U0/U_ICON/U_iDATA_CMD
- SLICE_X75Y135.SR net (fanout=7) 1.198 U_icon_pro/U0/U_ICON/iDATA_CMD
- SLICE_X75Y135.CLK Tcksr (-Th) -0.290 U_icon_pro/U0/U_ICON/iSYNC
- U_icon_pro/U0/U_ICON/U_SYNC/U_SYNC
+ SLICE_X76Y117.SR net (fanout=8) 1.233 U_icon_pro/U0/U_ICON/iDATA_CMD
+ SLICE_X76Y117.CLK Tcksr (-Th) -0.290 U_icon_pro/U0/U_ICON/U_SYNC/iSYNC_WORD<3>
+ U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[3].I_NE0.U_FDR
------------------------------------------------- ---------------------------
- Total 1.965ns (0.767ns logic, 1.198ns route)
- (39.0% logic, 61.0% route)
+ Total 2.000ns (0.767ns logic, 1.233ns route)
+ (38.4% logic, 61.6% route)
--------------------------------------------------------------------------------
-Paths for end point U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[1].I_NE0.U_FDR (SLICE_X73Y134.SR), 1 path
+Paths for end point U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[4].I_NE0.U_FDR (SLICE_X76Y114.SR), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 2.032ns (requirement - (clock path skew + uncertainty - data path))
+Slack (hold path): 2.192ns (requirement - (clock path skew + uncertainty - data path))
Source: U_icon_pro/U0/U_ICON/U_iDATA_CMD (FF)
- Destination: U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[1].I_NE0.U_FDR (FF)
+ Destination: U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[4].I_NE0.U_FDR (FF)
Requirement: 0.000ns
- Data Path Delay: 2.032ns (Levels of Logic = 0)
+ Data Path Delay: 2.192ns (Levels of Logic = 0)
Positive Clock Path Skew: 0.000ns
Source Clock: U_icon_pro/U0/iUPDATE_OUT rising
Destination Clock: icon_control0<0> rising at 0.000ns
Clock Uncertainty: 0.000ns
- Minimum Data Path: U_icon_pro/U0/U_ICON/U_iDATA_CMD to U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[1].I_NE0.U_FDR
+ Minimum Data Path: U_icon_pro/U0/U_ICON/U_iDATA_CMD to U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[4].I_NE0.U_FDR
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X78Y143.YQ Tcko 0.477 U_icon_pro/U0/U_ICON/iDATA_CMD
U_icon_pro/U0/U_ICON/U_iDATA_CMD
- SLICE_X73Y134.SR net (fanout=7) 1.265 U_icon_pro/U0/U_ICON/iDATA_CMD
- SLICE_X73Y134.CLK Tcksr (-Th) -0.290 U_icon_pro/U0/U_ICON/U_SYNC/iSYNC_WORD<1>
- U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[1].I_NE0.U_FDR
+ SLICE_X76Y114.SR net (fanout=8) 1.425 U_icon_pro/U0/U_ICON/iDATA_CMD
+ SLICE_X76Y114.CLK Tcksr (-Th) -0.290 U_icon_pro/U0/U_ICON/U_SYNC/iSYNC_WORD<4>
+ U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[4].I_NE0.U_FDR
------------------------------------------------- ---------------------------
- Total 2.032ns (0.767ns logic, 1.265ns route)
- (37.7% logic, 62.3% route)
+ Total 2.192ns (0.767ns logic, 1.425ns route)
+ (35.0% logic, 65.0% route)
--------------------------------------------------------------------------------
-Paths for end point U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[0].I_NE0.U_FDR (SLICE_X73Y134.SR), 1 path
+Paths for end point U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[5].I_NE0.U_FDR (SLICE_X76Y114.SR), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 2.032ns (requirement - (clock path skew + uncertainty - data path))
+Slack (hold path): 2.192ns (requirement - (clock path skew + uncertainty - data path))
Source: U_icon_pro/U0/U_ICON/U_iDATA_CMD (FF)
- Destination: U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[0].I_NE0.U_FDR (FF)
+ Destination: U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[5].I_NE0.U_FDR (FF)
Requirement: 0.000ns
- Data Path Delay: 2.032ns (Levels of Logic = 0)
+ Data Path Delay: 2.192ns (Levels of Logic = 0)
Positive Clock Path Skew: 0.000ns
Source Clock: U_icon_pro/U0/iUPDATE_OUT rising
Destination Clock: icon_control0<0> rising at 0.000ns
Clock Uncertainty: 0.000ns
- Minimum Data Path: U_icon_pro/U0/U_ICON/U_iDATA_CMD to U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[0].I_NE0.U_FDR
+ Minimum Data Path: U_icon_pro/U0/U_ICON/U_iDATA_CMD to U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[5].I_NE0.U_FDR
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X78Y143.YQ Tcko 0.477 U_icon_pro/U0/U_ICON/iDATA_CMD
U_icon_pro/U0/U_ICON/U_iDATA_CMD
- SLICE_X73Y134.SR net (fanout=7) 1.265 U_icon_pro/U0/U_ICON/iDATA_CMD
- SLICE_X73Y134.CLK Tcksr (-Th) -0.290 U_icon_pro/U0/U_ICON/U_SYNC/iSYNC_WORD<1>
- U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[0].I_NE0.U_FDR
+ SLICE_X76Y114.SR net (fanout=8) 1.425 U_icon_pro/U0/U_ICON/iDATA_CMD
+ SLICE_X76Y114.CLK Tcksr (-Th) -0.290 U_icon_pro/U0/U_ICON/U_SYNC/iSYNC_WORD<4>
+ U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[5].I_NE0.U_FDR
------------------------------------------------- ---------------------------
- Total 2.032ns (0.767ns logic, 1.265ns route)
- (37.7% logic, 62.3% route)
+ Total 2.192ns (0.767ns logic, 1.425ns route)
+ (35.0% logic, 65.0% route)
--------------------------------------------------------------------------------
================================================================================
@@ -357,7 +357,7 @@ Slack (setup paths): 13.697ns (requirement - (data path - clock path skew + u
------------------------------------------------- -------------------
SLICE_X78Y143.YQ Tcko 0.596 U_icon_pro/U0/U_ICON/iDATA_CMD
U_icon_pro/U0/U_ICON/U_iDATA_CMD
- SLICE_X78Y143.BY net (fanout=7) 0.427 U_icon_pro/U0/U_ICON/iDATA_CMD
+ SLICE_X78Y143.BY net (fanout=8) 0.427 U_icon_pro/U0/U_ICON/iDATA_CMD
SLICE_X78Y143.CLK Tdick 0.280 U_icon_pro/U0/U_ICON/iDATA_CMD
U_icon_pro/U0/U_ICON/U_iDATA_CMD
------------------------------------------------- ---------------------------
@@ -386,7 +386,7 @@ Slack (hold path): 0.955ns (requirement - (clock path skew + uncertainty -
------------------------------------------------- -------------------
SLICE_X78Y143.YQ Tcko 0.477 U_icon_pro/U0/U_ICON/iDATA_CMD
U_icon_pro/U0/U_ICON/U_iDATA_CMD
- SLICE_X78Y143.BY net (fanout=7) 0.341 U_icon_pro/U0/U_ICON/iDATA_CMD
+ SLICE_X78Y143.BY net (fanout=8) 0.341 U_icon_pro/U0/U_ICON/iDATA_CMD
SLICE_X78Y143.CLK Tckdi (-Th) -0.137 U_icon_pro/U0/U_ICON/iDATA_CMD
U_icon_pro/U0/U_ICON/U_iDATA_CMD
------------------------------------------------- ---------------------------
@@ -401,342 +401,340 @@ Timing constraint: PATH "TS_J_TO_D_path" TIG;
0 timing errors detected. (0 setup errors, 0 hold errors)
--------------------------------------------------------------------------------
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[4].U_FDRE (SLICE_X37Y118.SR), 3 paths
+Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_DOUT (SLICE_X73Y20.BY), 3 paths
--------------------------------------------------------------------------------
-Delay (setup path): 6.239ns (data path - clock path skew + uncertainty)
+Delay (setup path): 6.615ns (data path - clock path skew + uncertainty)
Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL (FF)
- Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[4].U_FDRE (FF)
- Data Path Delay: 6.239ns (Levels of Logic = 1)
+ Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_DOUT (FF)
+ Data Path Delay: 6.615ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: icon_control0<0> rising
Destination Clock: cmp_gn4124_core/clk_p rising
Clock Uncertainty: 0.000ns
- Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[4].U_FDRE
+ Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_DOUT
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X36Y116.COUT Twosco 3.614 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
+ SLICE_X76Y51.COUT Twosco 3.614 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL.CE
U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL
U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL
U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH
- SLICE_X36Y119.G3 net (fanout=3) 0.554 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
- SLICE_X36Y119.Y Tilo 0.616 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/MCNT_en
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_MCNT_rst_SRLC16.U_MCNT_rst
- SLICE_X37Y118.SR net (fanout=4) 1.022 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/MCNT_rst
- SLICE_X37Y118.CLK Tsrck 0.433 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/MCNT<4>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[4].U_FDRE
+ SLICE_X76Y48.G1 net (fanout=3) 0.893 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
+ SLICE_X76Y48.Y Tilo 0.616 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_5_TO_8.F_TPL[0].U_TPL/I_NMU_EQ4.U_iDOUT/iCFG_DIN
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_DOUT_flag_SRLC16.U_DOUT_flag
+ SLICE_X73Y20.BY net (fanout=1) 1.245 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/DOUT_flag
+ SLICE_X73Y20.CLK Tdick 0.247 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<4>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_DOUT
------------------------------------------------- ---------------------------
- Total 6.239ns (4.663ns logic, 1.576ns route)
- (74.7% logic, 25.3% route)
+ Total 6.615ns (4.477ns logic, 2.138ns route)
+ (67.7% logic, 32.3% route)
--------------------------------------------------------------------------------
-Delay (setup path): 6.233ns (data path - clock path skew + uncertainty)
+Delay (setup path): 6.609ns (data path - clock path skew + uncertainty)
Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH (FF)
- Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[4].U_FDRE (FF)
- Data Path Delay: 6.233ns (Levels of Logic = 1)
+ Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_DOUT (FF)
+ Data Path Delay: 6.609ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: icon_control0<0> rising
Destination Clock: cmp_gn4124_core/clk_p rising
Clock Uncertainty: 0.000ns
- Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[4].U_FDRE
+ Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_DOUT
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X36Y116.COUT Twosco 3.608 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
+ SLICE_X76Y51.COUT Twosco 3.608 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL.CE
U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH
U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH
- SLICE_X36Y119.G3 net (fanout=3) 0.554 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
- SLICE_X36Y119.Y Tilo 0.616 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/MCNT_en
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_MCNT_rst_SRLC16.U_MCNT_rst
- SLICE_X37Y118.SR net (fanout=4) 1.022 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/MCNT_rst
- SLICE_X37Y118.CLK Tsrck 0.433 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/MCNT<4>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[4].U_FDRE
+ SLICE_X76Y48.G1 net (fanout=3) 0.893 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
+ SLICE_X76Y48.Y Tilo 0.616 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_5_TO_8.F_TPL[0].U_TPL/I_NMU_EQ4.U_iDOUT/iCFG_DIN
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_DOUT_flag_SRLC16.U_DOUT_flag
+ SLICE_X73Y20.BY net (fanout=1) 1.245 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/DOUT_flag
+ SLICE_X73Y20.CLK Tdick 0.247 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<4>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_DOUT
------------------------------------------------- ---------------------------
- Total 6.233ns (4.657ns logic, 1.576ns route)
- (74.7% logic, 25.3% route)
+ Total 6.609ns (4.471ns logic, 2.138ns route)
+ (67.7% logic, 32.3% route)
--------------------------------------------------------------------------------
-Delay (setup path): 4.552ns (data path - clock path skew + uncertainty)
- Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_MCNT_rst_SRLC16.U_MCNT_rst (FF)
- Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[4].U_FDRE (FF)
- Data Path Delay: 4.552ns (Levels of Logic = 0)
+Delay (setup path): 4.589ns (data path - clock path skew + uncertainty)
+ Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_DOUT_flag_SRLC16.U_DOUT_flag (FF)
+ Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_DOUT (FF)
+ Data Path Delay: 4.589ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: icon_control0<0> rising
Destination Clock: cmp_gn4124_core/clk_p rising
Clock Uncertainty: 0.000ns
- Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_MCNT_rst_SRLC16.U_MCNT_rst to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[4].U_FDRE
+ Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_DOUT_flag_SRLC16.U_DOUT_flag to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_DOUT
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X36Y119.Y Treg 3.097 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/MCNT_en
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_MCNT_en_SRLC16.U_MCNT_en.CE
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_MCNT_rst_SRLC16.U_MCNT_rst
- SLICE_X37Y118.SR net (fanout=4) 1.022 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/MCNT_rst
- SLICE_X37Y118.CLK Tsrck 0.433 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/MCNT<4>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[4].U_FDRE
+ SLICE_X76Y48.Y Treg 3.097 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_5_TO_8.F_TPL[0].U_TPL/I_NMU_EQ4.U_iDOUT/iCFG_DIN
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_DOUT_flag_SRLC16.U_DOUT_flag.CE
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_DOUT_flag_SRLC16.U_DOUT_flag
+ SLICE_X73Y20.BY net (fanout=1) 1.245 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/DOUT_flag
+ SLICE_X73Y20.CLK Tdick 0.247 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<4>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_DOUT
------------------------------------------------- ---------------------------
- Total 4.552ns (3.530ns logic, 1.022ns route)
- (77.5% logic, 22.5% route)
+ Total 4.589ns (3.344ns logic, 1.245ns route)
+ (72.9% logic, 27.1% route)
--------------------------------------------------------------------------------
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[5].U_FDRE (SLICE_X37Y118.SR), 3 paths
+Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_DOUT (SLICE_X75Y8.BY), 3 paths
--------------------------------------------------------------------------------
-Delay (setup path): 6.239ns (data path - clock path skew + uncertainty)
- Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL (FF)
- Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[5].U_FDRE (FF)
- Data Path Delay: 6.239ns (Levels of Logic = 1)
+Delay (setup path): 6.406ns (data path - clock path skew + uncertainty)
+ Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL (FF)
+ Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_DOUT (FF)
+ Data Path Delay: 6.406ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: icon_control0<0> rising
Destination Clock: cmp_gn4124_core/clk_p rising
Clock Uncertainty: 0.000ns
- Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[5].U_FDRE
+ Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_DOUT
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X36Y116.COUT Twosco 3.614 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL.CE
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH
- SLICE_X36Y119.G3 net (fanout=3) 0.554 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
- SLICE_X36Y119.Y Tilo 0.616 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/MCNT_en
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_MCNT_rst_SRLC16.U_MCNT_rst
- SLICE_X37Y118.SR net (fanout=4) 1.022 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/MCNT_rst
- SLICE_X37Y118.CLK Tsrck 0.433 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/MCNT<4>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[5].U_FDRE
+ SLICE_X78Y38.COUT Twosco 3.614 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL.CE
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH
+ SLICE_X78Y36.G1 net (fanout=3) 0.662 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
+ SLICE_X78Y36.Y Tilo 0.616 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/cfg_data<5>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_DOUT_flag_SRLC16.U_DOUT_flag
+ SLICE_X75Y8.BY net (fanout=1) 1.267 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/DOUT_flag
+ SLICE_X75Y8.CLK Tdick 0.247 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<3>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_DOUT
------------------------------------------------- ---------------------------
- Total 6.239ns (4.663ns logic, 1.576ns route)
- (74.7% logic, 25.3% route)
+ Total 6.406ns (4.477ns logic, 1.929ns route)
+ (69.9% logic, 30.1% route)
--------------------------------------------------------------------------------
-Delay (setup path): 6.233ns (data path - clock path skew + uncertainty)
- Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH (FF)
- Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[5].U_FDRE (FF)
- Data Path Delay: 6.233ns (Levels of Logic = 1)
+Delay (setup path): 6.400ns (data path - clock path skew + uncertainty)
+ Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH (FF)
+ Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_DOUT (FF)
+ Data Path Delay: 6.400ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: icon_control0<0> rising
Destination Clock: cmp_gn4124_core/clk_p rising
Clock Uncertainty: 0.000ns
- Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[5].U_FDRE
+ Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_DOUT
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X36Y116.COUT Twosco 3.608 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL.CE
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH
- SLICE_X36Y119.G3 net (fanout=3) 0.554 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
- SLICE_X36Y119.Y Tilo 0.616 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/MCNT_en
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_MCNT_rst_SRLC16.U_MCNT_rst
- SLICE_X37Y118.SR net (fanout=4) 1.022 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/MCNT_rst
- SLICE_X37Y118.CLK Tsrck 0.433 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/MCNT<4>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[5].U_FDRE
+ SLICE_X78Y38.COUT Twosco 3.608 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL.CE
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH
+ SLICE_X78Y36.G1 net (fanout=3) 0.662 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
+ SLICE_X78Y36.Y Tilo 0.616 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/cfg_data<5>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_DOUT_flag_SRLC16.U_DOUT_flag
+ SLICE_X75Y8.BY net (fanout=1) 1.267 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/DOUT_flag
+ SLICE_X75Y8.CLK Tdick 0.247 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<3>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_DOUT
------------------------------------------------- ---------------------------
- Total 6.233ns (4.657ns logic, 1.576ns route)
- (74.7% logic, 25.3% route)
+ Total 6.400ns (4.471ns logic, 1.929ns route)
+ (69.9% logic, 30.1% route)
--------------------------------------------------------------------------------
-Delay (setup path): 4.552ns (data path - clock path skew + uncertainty)
- Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_MCNT_rst_SRLC16.U_MCNT_rst (FF)
- Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[5].U_FDRE (FF)
- Data Path Delay: 4.552ns (Levels of Logic = 0)
+Delay (setup path): 4.611ns (data path - clock path skew + uncertainty)
+ Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_DOUT_flag_SRLC16.U_DOUT_flag (FF)
+ Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_DOUT (FF)
+ Data Path Delay: 4.611ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: icon_control0<0> rising
Destination Clock: cmp_gn4124_core/clk_p rising
Clock Uncertainty: 0.000ns
- Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_MCNT_rst_SRLC16.U_MCNT_rst to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[5].U_FDRE
+ Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_DOUT_flag_SRLC16.U_DOUT_flag to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_DOUT
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X36Y119.Y Treg 3.097 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/MCNT_en
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_MCNT_en_SRLC16.U_MCNT_en.CE
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_MCNT_rst_SRLC16.U_MCNT_rst
- SLICE_X37Y118.SR net (fanout=4) 1.022 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/MCNT_rst
- SLICE_X37Y118.CLK Tsrck 0.433 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/MCNT<4>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[5].U_FDRE
+ SLICE_X78Y36.Y Treg 3.097 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/cfg_data<5>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_DOUT_flag_SRLC16.U_DOUT_flag.CE
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_DOUT_flag_SRLC16.U_DOUT_flag
+ SLICE_X75Y8.BY net (fanout=1) 1.267 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/DOUT_flag
+ SLICE_X75Y8.CLK Tdick 0.247 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<3>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_DOUT
------------------------------------------------- ---------------------------
- Total 4.552ns (3.530ns logic, 1.022ns route)
- (77.5% logic, 22.5% route)
+ Total 4.611ns (3.344ns logic, 1.267ns route)
+ (72.5% logic, 27.5% route)
--------------------------------------------------------------------------------
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[6].U_FDRE (SLICE_X37Y119.SR), 3 paths
+Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_DOUT (SLICE_X75Y11.BY), 3 paths
--------------------------------------------------------------------------------
-Delay (setup path): 6.239ns (data path - clock path skew + uncertainty)
- Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL (FF)
- Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[6].U_FDRE (FF)
- Data Path Delay: 6.239ns (Levels of Logic = 1)
+Delay (setup path): 6.265ns (data path - clock path skew + uncertainty)
+ Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL (FF)
+ Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_DOUT (FF)
+ Data Path Delay: 6.265ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: icon_control0<0> rising
Destination Clock: cmp_gn4124_core/clk_p rising
Clock Uncertainty: 0.000ns
- Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[6].U_FDRE
+ Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_DOUT
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X36Y116.COUT Twosco 3.614 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL.CE
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH
- SLICE_X36Y119.G3 net (fanout=3) 0.554 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
- SLICE_X36Y119.Y Tilo 0.616 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/MCNT_en
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_MCNT_rst_SRLC16.U_MCNT_rst
- SLICE_X37Y119.SR net (fanout=4) 1.022 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/MCNT_rst
- SLICE_X37Y119.CLK Tsrck 0.433 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/MCNT<6>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[6].U_FDRE
+ SLICE_X74Y44.COUT Twosco 3.614 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL.CE
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH
+ SLICE_X74Y42.G1 net (fanout=3) 0.641 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
+ SLICE_X74Y42.Y Tilo 0.616 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/DOUT_flag
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_DOUT_flag_SRLC16.U_DOUT_flag
+ SLICE_X75Y11.BY net (fanout=1) 1.147 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/DOUT_flag
+ SLICE_X75Y11.CLK Tdick 0.247 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<2>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_DOUT
------------------------------------------------- ---------------------------
- Total 6.239ns (4.663ns logic, 1.576ns route)
- (74.7% logic, 25.3% route)
+ Total 6.265ns (4.477ns logic, 1.788ns route)
+ (71.5% logic, 28.5% route)
--------------------------------------------------------------------------------
-Delay (setup path): 6.233ns (data path - clock path skew + uncertainty)
- Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH (FF)
- Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[6].U_FDRE (FF)
- Data Path Delay: 6.233ns (Levels of Logic = 1)
+Delay (setup path): 6.259ns (data path - clock path skew + uncertainty)
+ Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH (FF)
+ Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_DOUT (FF)
+ Data Path Delay: 6.259ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: icon_control0<0> rising
Destination Clock: cmp_gn4124_core/clk_p rising
Clock Uncertainty: 0.000ns
- Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[6].U_FDRE
+ Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_DOUT
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X36Y116.COUT Twosco 3.608 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL.CE
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH
- SLICE_X36Y119.G3 net (fanout=3) 0.554 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
- SLICE_X36Y119.Y Tilo 0.616 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/MCNT_en
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_MCNT_rst_SRLC16.U_MCNT_rst
- SLICE_X37Y119.SR net (fanout=4) 1.022 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/MCNT_rst
- SLICE_X37Y119.CLK Tsrck 0.433 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/MCNT<6>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[6].U_FDRE
+ SLICE_X74Y44.COUT Twosco 3.608 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL.CE
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH
+ SLICE_X74Y42.G1 net (fanout=3) 0.641 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_GAND_MATCH/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH/O
+ SLICE_X74Y42.Y Tilo 0.616 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/DOUT_flag
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_DOUT_flag_SRLC16.U_DOUT_flag
+ SLICE_X75Y11.BY net (fanout=1) 1.147 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/DOUT_flag
+ SLICE_X75Y11.CLK Tdick 0.247 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<2>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_DOUT
------------------------------------------------- ---------------------------
- Total 6.233ns (4.657ns logic, 1.576ns route)
- (74.7% logic, 25.3% route)
+ Total 6.259ns (4.471ns logic, 1.788ns route)
+ (71.4% logic, 28.6% route)
--------------------------------------------------------------------------------
-Delay (setup path): 4.552ns (data path - clock path skew + uncertainty)
- Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_MCNT_rst_SRLC16.U_MCNT_rst (FF)
- Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[6].U_FDRE (FF)
- Data Path Delay: 4.552ns (Levels of Logic = 0)
+Delay (setup path): 4.491ns (data path - clock path skew + uncertainty)
+ Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_DOUT_flag_SRLC16.U_DOUT_flag (FF)
+ Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_DOUT (FF)
+ Data Path Delay: 4.491ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: icon_control0<0> rising
Destination Clock: cmp_gn4124_core/clk_p rising
Clock Uncertainty: 0.000ns
- Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_MCNT_rst_SRLC16.U_MCNT_rst to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[6].U_FDRE
+ Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_DOUT_flag_SRLC16.U_DOUT_flag to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_DOUT
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X36Y119.Y Treg 3.097 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/MCNT_en
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_MCNT_en_SRLC16.U_MCNT_en.CE
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_MCNT_rst_SRLC16.U_MCNT_rst
- SLICE_X37Y119.SR net (fanout=4) 1.022 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/MCNT_rst
- SLICE_X37Y119.CLK Tsrck 0.433 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/MCNT<6>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[4].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.U_MCNT/G[6].U_FDRE
+ SLICE_X74Y42.Y Treg 3.097 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/DOUT_flag
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_DOUT_flag_SRLC16.U_DOUT_flag.CE
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/I_SRLT_NE_1.I_DOUT_flag_SRLC16.U_DOUT_flag
+ SLICE_X75Y11.BY net (fanout=1) 1.147 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/DOUT_flag
+ SLICE_X75Y11.CLK Tdick 0.247 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<2>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_DOUT
------------------------------------------------- ---------------------------
- Total 4.552ns (3.530ns logic, 1.022ns route)
- (77.5% logic, 22.5% route)
+ Total 4.491ns (3.344ns logic, 1.147ns route)
+ (74.5% logic, 25.5% route)
--------------------------------------------------------------------------------
Hold Paths: PATH "TS_J_TO_D_path" TIG;
--------------------------------------------------------------------------------
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[0].U_iCAP_ADDR (SLICE_X67Y113.F4), 1 path
+Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_RST/U_HALT_XFER/U_DOUT0 (SLICE_X73Y58.BY), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 1.060ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[0].U_SEL (FF)
- Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[0].U_iCAP_ADDR (FF)
+Slack (hold path): 0.854ns (requirement - (clock path skew + uncertainty - data path))
+ Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_RST/U_HALT_XFER/U_TFDRE (FF)
+ Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_RST/U_HALT_XFER/U_DOUT0 (FF)
Requirement: -2147483.647ns
- Data Path Delay: 1.060ns (Levels of Logic = 1)
+ Data Path Delay: 0.854ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: icon_control0<0> rising
Destination Clock: cmp_gn4124_core/clk_p rising
Clock Uncertainty: 0.000ns
- Minimum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[0].U_SEL to U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[0].U_iCAP_ADDR
+ Minimum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_RST/U_HALT_XFER/U_TFDRE to U_ila_pro_0/U0/I_YES_D.U_ILA/U_RST/U_HALT_XFER/U_DOUT0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X67Y112.XQ Tcko 0.396 U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec<1>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[0].U_SEL
- SLICE_X67Y113.F4 net (fanout=2) 0.258 U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec<1>
- SLICE_X67Y113.CLK Tckf (-Th) -0.406 U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR<0>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[0].U_CAP_ADDR_MUX
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[0].U_iCAP_ADDR
+ SLICE_X73Y59.YQ Tcko 0.419 U_ila_pro_0/U0/I_YES_D.U_ILA/U_RST/U_HALT_XFER/din_latched
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_RST/U_HALT_XFER/U_TFDRE
+ SLICE_X73Y58.BY net (fanout=1) 0.313 U_ila_pro_0/U0/I_YES_D.U_ILA/U_RST/U_HALT_XFER/din_latched
+ SLICE_X73Y58.CLK Tckdi (-Th) -0.122 U_ila_pro_0/U0/I_YES_D.U_ILA/U_RST/U_HALT_XFER/iDIN<0>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_RST/U_HALT_XFER/U_DOUT0
------------------------------------------------- ---------------------------
- Total 1.060ns (0.802ns logic, 0.258ns route)
- (75.7% logic, 24.3% route)
+ Total 0.854ns (0.541ns logic, 0.313ns route)
+ (63.3% logic, 36.7% route)
--------------------------------------------------------------------------------
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[6].U_iCAP_ADDR (SLICE_X65Y115.G4), 1 path
+Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[3].U_iCAP_ADDR (SLICE_X68Y32.F1), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 1.082ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[6].U_SEL (FF)
- Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[6].U_iCAP_ADDR (FF)
+Slack (hold path): 1.186ns (requirement - (clock path skew + uncertainty - data path))
+ Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[3].U_SEL (FF)
+ Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[3].U_iCAP_ADDR (FF)
Requirement: -2147483.647ns
- Data Path Delay: 1.082ns (Levels of Logic = 1)
+ Data Path Delay: 1.186ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: icon_control0<0> rising
Destination Clock: cmp_gn4124_core/clk_p rising
Clock Uncertainty: 0.000ns
- Minimum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[6].U_SEL to U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[6].U_iCAP_ADDR
+ Minimum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[3].U_SEL to U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[3].U_iCAP_ADDR
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X65Y113.YQ Tcko 0.419 U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec<7>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[6].U_SEL
- SLICE_X65Y115.G4 net (fanout=2) 0.257 U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec<7>
- SLICE_X65Y115.CLK Tckg (-Th) -0.406 U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR<1>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[6].U_CAP_ADDR_MUX
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[6].U_iCAP_ADDR
+ SLICE_X66Y32.XQ Tcko 0.417 U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec<4>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[3].U_SEL
+ SLICE_X68Y32.F1 net (fanout=2) 0.331 U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec<4>
+ SLICE_X68Y32.CLK Tckf (-Th) -0.438 U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR<3>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[3].U_CAP_ADDR_MUX
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[3].U_iCAP_ADDR
------------------------------------------------- ---------------------------
- Total 1.082ns (0.825ns logic, 0.257ns route)
- (76.2% logic, 23.8% route)
+ Total 1.186ns (0.855ns logic, 0.331ns route)
+ (72.1% logic, 27.9% route)
--------------------------------------------------------------------------------
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[2].U_iCAP_ADDR (SLICE_X67Y115.G4), 1 path
+Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_RST/U_ARM_XFER/U_DOUT0 (SLICE_X70Y62.BX), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 1.092ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[2].U_SEL (FF)
- Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[2].U_iCAP_ADDR (FF)
+Slack (hold path): 0.861ns (requirement - (clock path skew + uncertainty - data path))
+ Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_RST/U_ARM_XFER/U_TFDRE (FF)
+ Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_RST/U_ARM_XFER/U_DOUT0 (FF)
Requirement: -2147483.647ns
- Data Path Delay: 1.092ns (Levels of Logic = 1)
+ Data Path Delay: 0.861ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: icon_control0<0> rising
Destination Clock: cmp_gn4124_core/clk_p rising
Clock Uncertainty: 0.000ns
- Minimum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[2].U_SEL to U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[2].U_iCAP_ADDR
+ Minimum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_RST/U_ARM_XFER/U_TFDRE to U_ila_pro_0/U0/I_YES_D.U_ILA/U_RST/U_ARM_XFER/U_DOUT0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X67Y114.XQ Tcko 0.396 U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec<3>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[2].U_SEL
- SLICE_X67Y115.G4 net (fanout=2) 0.290 U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec<3>
- SLICE_X67Y115.CLK Tckg (-Th) -0.406 U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR<2>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[2].U_CAP_ADDR_MUX
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[2].U_iCAP_ADDR
+ SLICE_X70Y65.YQ Tcko 0.477 U_ila_pro_0/U0/I_YES_D.U_ILA/U_RST/U_ARM_XFER/din_latched
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_RST/U_ARM_XFER/U_TFDRE
+ SLICE_X70Y62.BX net (fanout=1) 0.282 U_ila_pro_0/U0/I_YES_D.U_ILA/U_RST/U_ARM_XFER/din_latched
+ SLICE_X70Y62.CLK Tckdi (-Th) -0.102 U_ila_pro_0/U0/I_YES_D.U_ILA/U_RST/U_ARM_XFER/iDIN<0>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_RST/U_ARM_XFER/U_DOUT0
------------------------------------------------- ---------------------------
- Total 1.092ns (0.802ns logic, 0.290ns route)
- (73.4% logic, 26.6% route)
+ Total 0.861ns (0.579ns logic, 0.282ns route)
+ (67.2% logic, 32.8% route)
--------------------------------------------------------------------------------
@@ -747,44 +745,47 @@ Timing constraint: PATH "TS_D_TO_J_path" TIG;
0 timing errors detected. (0 setup errors, 0 hold errors)
--------------------------------------------------------------------------------
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO (SLICE_X59Y127.F2), 17 paths
+Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO (SLICE_X68Y54.G3), 17 paths
--------------------------------------------------------------------------------
-Delay (setup path): 4.647ns (data path - clock path skew + uncertainty)
- Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TRIGGER (FF)
+Delay (setup path): 5.642ns (data path - clock path skew + uncertainty)
+ Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_STATE1 (FF)
Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO (FF)
- Data Path Delay: 4.647ns (Levels of Logic = 3)
+ Data Path Delay: 5.642ns (Levels of Logic = 4)
Clock Path Skew: 0.000ns
Source Clock: cmp_gn4124_core/clk_p rising
Destination Clock: icon_control0<0> rising
Clock Uncertainty: 0.000ns
- Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TRIGGER to U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
+ Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_STATE1 to U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X57Y106.XQ Tcko 0.495 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/TRIGGER_dstat
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TRIGGER
- SLICE_X56Y125.G4 net (fanout=2) 1.280 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/TRIGGER_dstat
- SLICE_X56Y125.X Tif5x 0.853 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/NS_dstat<8>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_F
+ SLICE_X70Y39.YQ Tcko 0.596 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/STATE_dstat<0>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_STATE1
+ SLICE_X70Y38.F3 net (fanout=1) 0.318 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/STATE_dstat<1>
+ SLICE_X70Y38.X Tilo 0.601 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/DSTAT_en_dly3
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13
+ SLICE_X70Y44.F1 net (fanout=1) 0.551 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13
+ SLICE_X70Y44.X Tif5x 0.853 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_G
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8
- SLICE_X57Y126.G4 net (fanout=1) 0.268 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8
- SLICE_X57Y126.X Tif5x 0.791 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/TDO_mux_in<0>1
+ SLICE_X71Y51.G3 net (fanout=1) 0.754 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8
+ SLICE_X71Y51.X Tif5x 0.791 U_ila_pro_0/U0/iDATA<13>
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_2_f5_F
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_2_f5
- SLICE_X59Y127.F2 net (fanout=1) 0.358 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/TDO_mux_in<0>1
- SLICE_X59Y127.CLK Tfck 0.602 U_ila_pro_0/U0/I_YES_D.U_ILA/iSTAT_DOUT
+ SLICE_X68Y54.G3 net (fanout=1) 0.507 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/TDO_mux_in<0>1
+ SLICE_X68Y54.CLK Tgck 0.671 U_ila_pro_0/U0/I_YES_D.U_ILA/iSTAT_DOUT
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O96
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
------------------------------------------------- ---------------------------
- Total 4.647ns (2.741ns logic, 1.906ns route)
- (59.0% logic, 41.0% route)
+ Total 5.642ns (3.512ns logic, 2.130ns route)
+ (62.2% logic, 37.8% route)
--------------------------------------------------------------------------------
-Delay (setup path): 4.561ns (data path - clock path skew + uncertainty)
+Delay (setup path): 5.549ns (data path - clock path skew + uncertainty)
Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_STATE0 (FF)
Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO (FF)
- Data Path Delay: 4.561ns (Levels of Logic = 4)
+ Data Path Delay: 5.549ns (Levels of Logic = 4)
Clock Path Skew: 0.000ns
Source Clock: cmp_gn4124_core/clk_p rising
Destination Clock: icon_control0<0> rising
@@ -794,723 +795,759 @@ Delay (setup path): 4.561ns (data path - clock path skew + uncertainty)
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X51Y124.XQ Tcko 0.495 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/STATE_dstat<0>
+ SLICE_X70Y39.XQ Tcko 0.521 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/STATE_dstat<0>
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_STATE0
- SLICE_X53Y124.F2 net (fanout=1) 0.374 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/STATE_dstat<0>
- SLICE_X53Y124.X Tilo 0.562 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/DSTAT_en_dly2
+ SLICE_X70Y38.F4 net (fanout=1) 0.300 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/STATE_dstat<0>
+ SLICE_X70Y38.X Tilo 0.601 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/DSTAT_en_dly3
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13
- SLICE_X56Y125.F3 net (fanout=1) 0.258 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13
- SLICE_X56Y125.X Tif5x 0.853 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/NS_dstat<8>
+ SLICE_X70Y44.F1 net (fanout=1) 0.551 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13
+ SLICE_X70Y44.X Tif5x 0.853 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_G
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8
- SLICE_X57Y126.G4 net (fanout=1) 0.268 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8
- SLICE_X57Y126.X Tif5x 0.791 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/TDO_mux_in<0>1
+ SLICE_X71Y51.G3 net (fanout=1) 0.754 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8
+ SLICE_X71Y51.X Tif5x 0.791 U_ila_pro_0/U0/iDATA<13>
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_2_f5_F
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_2_f5
- SLICE_X59Y127.F2 net (fanout=1) 0.358 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/TDO_mux_in<0>1
- SLICE_X59Y127.CLK Tfck 0.602 U_ila_pro_0/U0/I_YES_D.U_ILA/iSTAT_DOUT
+ SLICE_X68Y54.G3 net (fanout=1) 0.507 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/TDO_mux_in<0>1
+ SLICE_X68Y54.CLK Tgck 0.671 U_ila_pro_0/U0/I_YES_D.U_ILA/iSTAT_DOUT
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O96
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
------------------------------------------------- ---------------------------
- Total 4.561ns (3.303ns logic, 1.258ns route)
- (72.4% logic, 27.6% route)
+ Total 5.549ns (3.437ns logic, 2.112ns route)
+ (61.9% logic, 38.1% route)
--------------------------------------------------------------------------------
-Delay (setup path): 4.515ns (data path - clock path skew + uncertainty)
- Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_STATE1 (FF)
+Delay (setup path): 5.225ns (data path - clock path skew + uncertainty)
+ Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/G_NS[5].U_NSQ (FF)
Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO (FF)
- Data Path Delay: 4.515ns (Levels of Logic = 4)
+ Data Path Delay: 5.225ns (Levels of Logic = 4)
Clock Path Skew: 0.000ns
Source Clock: cmp_gn4124_core/clk_p rising
Destination Clock: icon_control0<0> rising
Clock Uncertainty: 0.000ns
- Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_STATE1 to U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
+ Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/G_NS[5].U_NSQ to U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X51Y124.YQ Tcko 0.524 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/STATE_dstat<0>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_STATE1
- SLICE_X53Y124.F3 net (fanout=1) 0.299 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/STATE_dstat<1>
- SLICE_X53Y124.X Tilo 0.562 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/DSTAT_en_dly2
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13
- SLICE_X56Y125.F3 net (fanout=1) 0.258 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13
- SLICE_X56Y125.X Tif5x 0.853 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/NS_dstat<8>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_G
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8
- SLICE_X57Y126.G4 net (fanout=1) 0.268 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8
- SLICE_X57Y126.X Tif5x 0.791 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/TDO_mux_in<0>1
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_2_f5_F
+ SLICE_X74Y32.YQ Tcko 0.596 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/NS_dstat<4>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/G_NS[5].U_NSQ
+ SLICE_X75Y38.G2 net (fanout=1) 0.817 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/NS_dstat<5>
+ SLICE_X75Y38.F5 Tif5 0.688 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_10
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_f5
+ SLICE_X75Y38.FXINA net (fanout=1) 0.000 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_f5
+ SLICE_X75Y38.Y Tif6y 0.239 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6
+ SLICE_X71Y51.F4 net (fanout=1) 0.916 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6
+ SLICE_X71Y51.X Tif5x 0.791 U_ila_pro_0/U0/iDATA<13>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_2_f5_G
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_2_f5
- SLICE_X59Y127.F2 net (fanout=1) 0.358 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/TDO_mux_in<0>1
- SLICE_X59Y127.CLK Tfck 0.602 U_ila_pro_0/U0/I_YES_D.U_ILA/iSTAT_DOUT
+ SLICE_X68Y54.G3 net (fanout=1) 0.507 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/TDO_mux_in<0>1
+ SLICE_X68Y54.CLK Tgck 0.671 U_ila_pro_0/U0/I_YES_D.U_ILA/iSTAT_DOUT
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O96
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
------------------------------------------------- ---------------------------
- Total 4.515ns (3.332ns logic, 1.183ns route)
- (73.8% logic, 26.2% route)
+ Total 5.225ns (2.985ns logic, 2.240ns route)
+ (57.1% logic, 42.9% route)
--------------------------------------------------------------------------------
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E (SLICE_X22Y124.G1), 5 paths
+Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[1].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E (SLICE_X76Y2.G1), 5 paths
--------------------------------------------------------------------------------
-Delay (setup path): 3.678ns (data path)
- Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/I_MC_YES.U_MC/U_DOUT (FF)
- Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E (FF)
- Data Path Delay: 3.678ns (Levels of Logic = 2)
+Delay (setup path): 3.844ns (data path)
+ Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_YES.U_MC/U_DOUT (FF)
+ Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[1].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E (FF)
+ Data Path Delay: 3.844ns (Levels of Logic = 2)
Source Clock: cmp_gn4124_core/clk_p rising at 0.000ns
- Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/I_MC_YES.U_MC/U_DOUT to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E
+ Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_YES.U_MC/U_DOUT to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[1].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X22Y122.YQ Tcko 0.596 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<1>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/I_MC_YES.U_MC/U_DOUT
- SLICE_X24Y125.G2 net (fanout=19) 0.965 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<1>
- SLICE_X24Y125.X Tif5x 0.853 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/state<12>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
- SLICE_X22Y125.F2 net (fanout=1) 0.284 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
- SLICE_X22Y125.X Tilo 0.601 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<21>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<38>
- SLICE_X22Y124.G1 net (fanout=1) 0.379 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/mux_out<12>
+ SLICE_X72Y10.YQ Tcko 0.596 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<0>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_YES.U_MC/U_DOUT
+ SLICE_X75Y6.G2 net (fanout=35) 0.891 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<0>
+ SLICE_X75Y6.X Tif5x 0.791 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<29>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[1].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[1].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
+ SLICE_X79Y5.F2 net (fanout=1) 0.621 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[1].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
+ SLICE_X79Y5.X Tilo 0.562 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/mux_out<1>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<5>
+ SLICE_X76Y2.G1 net (fanout=1) 0.383 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/mux_out<1>
------------------------------------------------- ---------------------------
- Total 3.678ns (2.050ns logic, 1.628ns route)
- (55.7% logic, 44.3% route)
+ Total 3.844ns (1.949ns logic, 1.895ns route)
+ (50.7% logic, 49.3% route)
--------------------------------------------------------------------------------
-Delay (setup path): 3.362ns (data path)
- Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_DOUT (FF)
- Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E (FF)
- Data Path Delay: 3.362ns (Levels of Logic = 2)
+Delay (setup path): 3.758ns (data path)
+ Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/I_MC_YES.U_MC/U_DOUT (FF)
+ Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[1].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E (FF)
+ Data Path Delay: 3.758ns (Levels of Logic = 2)
Source Clock: cmp_gn4124_core/clk_p rising at 0.000ns
- Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_DOUT to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E
+ Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/I_MC_YES.U_MC/U_DOUT to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[1].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X23Y122.XQ Tcko 0.495 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<3>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_DOUT
- SLICE_X24Y125.F4 net (fanout=19) 0.750 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<3>
- SLICE_X24Y125.X Tif5x 0.853 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/state<12>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_6
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
- SLICE_X22Y125.F2 net (fanout=1) 0.284 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
- SLICE_X22Y125.X Tilo 0.601 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<21>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<38>
- SLICE_X22Y124.G1 net (fanout=1) 0.379 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/mux_out<12>
- ------------------------------------------------- ---------------------------
- Total 3.362ns (1.949ns logic, 1.413ns route)
- (58.0% logic, 42.0% route)
+ SLICE_X72Y12.YQ Tcko 0.596 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<1>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/I_MC_YES.U_MC/U_DOUT
+ SLICE_X75Y6.G4 net (fanout=19) 0.805 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<1>
+ SLICE_X75Y6.X Tif5x 0.791 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<29>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[1].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[1].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
+ SLICE_X79Y5.F2 net (fanout=1) 0.621 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[1].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
+ SLICE_X79Y5.X Tilo 0.562 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/mux_out<1>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<5>
+ SLICE_X76Y2.G1 net (fanout=1) 0.383 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/mux_out<1>
+ ------------------------------------------------- ---------------------------
+ Total 3.758ns (1.949ns logic, 1.809ns route)
+ (51.9% logic, 48.1% route)
--------------------------------------------------------------------------------
-Delay (setup path): 3.249ns (data path)
- Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_YES.U_MC/U_DOUT (FF)
- Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E (FF)
- Data Path Delay: 3.249ns (Levels of Logic = 2)
+Delay (setup path): 3.687ns (data path)
+ Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_DOUT (FF)
+ Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[1].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E (FF)
+ Data Path Delay: 3.687ns (Levels of Logic = 2)
Source Clock: cmp_gn4124_core/clk_p rising at 0.000ns
- Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_YES.U_MC/U_DOUT to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E
+ Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_DOUT to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[1].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X23Y122.YQ Tcko 0.524 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<3>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_YES.U_MC/U_DOUT
- SLICE_X24Y125.G4 net (fanout=35) 0.608 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<0>
- SLICE_X24Y125.X Tif5x 0.853 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/state<12>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
- SLICE_X22Y125.F2 net (fanout=1) 0.284 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[12].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
- SLICE_X22Y125.X Tilo 0.601 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<21>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<38>
- SLICE_X22Y124.G1 net (fanout=1) 0.379 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/mux_out<12>
+ SLICE_X75Y11.YQ Tcko 0.524 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<2>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_DOUT
+ SLICE_X75Y6.F1 net (fanout=19) 0.806 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<2>
+ SLICE_X75Y6.X Tif5x 0.791 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<29>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[1].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_6
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[1].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
+ SLICE_X79Y5.F2 net (fanout=1) 0.621 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[1].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
+ SLICE_X79Y5.X Tilo 0.562 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/mux_out<1>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<5>
+ SLICE_X76Y2.G1 net (fanout=1) 0.383 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/mux_out<1>
------------------------------------------------- ---------------------------
- Total 3.249ns (1.978ns logic, 1.271ns route)
- (60.9% logic, 39.1% route)
+ Total 3.687ns (1.877ns logic, 1.810ns route)
+ (50.9% logic, 49.1% route)
--------------------------------------------------------------------------------
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[8].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E (SLICE_X20Y123.F1), 5 paths
+Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[7].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E (SLICE_X74Y3.G1), 5 paths
--------------------------------------------------------------------------------
-Delay (setup path): 3.666ns (data path)
- Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/I_MC_YES.U_MC/U_DOUT (FF)
- Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[8].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E (FF)
- Data Path Delay: 3.666ns (Levels of Logic = 2)
+Delay (setup path): 3.823ns (data path)
+ Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_YES.U_MC/U_DOUT (FF)
+ Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[7].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E (FF)
+ Data Path Delay: 3.823ns (Levels of Logic = 2)
Source Clock: cmp_gn4124_core/clk_p rising at 0.000ns
- Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/I_MC_YES.U_MC/U_DOUT to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[8].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E
+ Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_YES.U_MC/U_DOUT to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[7].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X22Y122.YQ Tcko 0.596 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<1>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/I_MC_YES.U_MC/U_DOUT
- SLICE_X22Y123.G1 net (fanout=19) 0.536 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<1>
- SLICE_X22Y123.X Tif5x 0.853 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<2>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[8].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[8].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
- SLICE_X21Y124.F2 net (fanout=1) 0.535 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[8].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
- SLICE_X21Y124.X Tilo 0.562 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/state<11>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<26>
- SLICE_X20Y123.F1 net (fanout=1) 0.584 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/mux_out<8>
- ------------------------------------------------- ---------------------------
- Total 3.666ns (2.011ns logic, 1.655ns route)
- (54.9% logic, 45.1% route)
+ SLICE_X72Y10.YQ Tcko 0.596 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<0>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_YES.U_MC/U_DOUT
+ SLICE_X71Y4.G2 net (fanout=35) 1.010 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<0>
+ SLICE_X71Y4.X Tif5x 0.791 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<23>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[7].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[7].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
+ SLICE_X71Y3.F3 net (fanout=1) 0.264 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[7].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
+ SLICE_X71Y3.X Tilo 0.562 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<21>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<23>
+ SLICE_X74Y3.G1 net (fanout=1) 0.600 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/mux_out<7>
+ ------------------------------------------------- ---------------------------
+ Total 3.823ns (1.949ns logic, 1.874ns route)
+ (51.0% logic, 49.0% route)
--------------------------------------------------------------------------------
-Delay (setup path): 3.655ns (data path)
- Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_DOUT (FF)
- Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[8].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E (FF)
- Data Path Delay: 3.655ns (Levels of Logic = 2)
+Delay (setup path): 3.806ns (data path)
+ Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/I_MC_YES.U_MC/U_DOUT (FF)
+ Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[7].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E (FF)
+ Data Path Delay: 3.806ns (Levels of Logic = 2)
Source Clock: cmp_gn4124_core/clk_p rising at 0.000ns
- Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_DOUT to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[8].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E
+ Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/I_MC_YES.U_MC/U_DOUT to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[7].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X22Y123.YQ Tcko 0.596 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<2>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_YES.U_MC/U_DOUT
- SLICE_X22Y123.F4 net (fanout=19) 0.525 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<2>
- SLICE_X22Y123.X Tif5x 0.853 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<2>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[8].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_6
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[8].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
- SLICE_X21Y124.F2 net (fanout=1) 0.535 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[8].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
- SLICE_X21Y124.X Tilo 0.562 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/state<11>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<26>
- SLICE_X20Y123.F1 net (fanout=1) 0.584 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/mux_out<8>
+ SLICE_X72Y12.YQ Tcko 0.596 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<1>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/I_MC_YES.U_MC/U_DOUT
+ SLICE_X71Y4.G4 net (fanout=19) 0.993 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<1>
+ SLICE_X71Y4.X Tif5x 0.791 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<23>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[7].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[7].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
+ SLICE_X71Y3.F3 net (fanout=1) 0.264 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[7].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
+ SLICE_X71Y3.X Tilo 0.562 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<21>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<23>
+ SLICE_X74Y3.G1 net (fanout=1) 0.600 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/mux_out<7>
------------------------------------------------- ---------------------------
- Total 3.655ns (2.011ns logic, 1.644ns route)
- (55.0% logic, 45.0% route)
+ Total 3.806ns (1.949ns logic, 1.857ns route)
+ (51.2% logic, 48.8% route)
--------------------------------------------------------------------------------
-Delay (setup path): 3.644ns (data path)
- Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_YES.U_MC/U_DOUT (FF)
- Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[8].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E (FF)
- Data Path Delay: 3.644ns (Levels of Logic = 2)
+Delay (setup path): 3.699ns (data path)
+ Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_DOUT (FF)
+ Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[7].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E (FF)
+ Data Path Delay: 3.699ns (Levels of Logic = 2)
Source Clock: cmp_gn4124_core/clk_p rising at 0.000ns
- Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_YES.U_MC/U_DOUT to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[8].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E
+ Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_DOUT to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[7].SI_CFG/I_NOLUT6.I_SRL_T2.U_SRLC16E
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X23Y122.YQ Tcko 0.524 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<3>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_YES.U_MC/U_DOUT
- SLICE_X22Y123.G3 net (fanout=35) 0.586 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<0>
- SLICE_X22Y123.X Tif5x 0.853 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<2>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[8].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[8].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
- SLICE_X21Y124.F2 net (fanout=1) 0.535 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[8].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
- SLICE_X21Y124.X Tilo 0.562 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/state<11>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<26>
- SLICE_X20Y123.F1 net (fanout=1) 0.584 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/mux_out<8>
+ SLICE_X75Y8.YQ Tcko 0.524 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<3>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_YES.U_MC/U_DOUT
+ SLICE_X71Y4.F4 net (fanout=19) 0.958 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/trigCondIn<3>
+ SLICE_X71Y4.X Tif5x 0.791 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<23>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[7].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_6
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[7].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
+ SLICE_X71Y3.F3 net (fanout=1) 0.264 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[7].U_MUS.U_MUX/U_CS_MUX/I3.U_MUX8/Mmux_O_5_f5
+ SLICE_X71Y3.X Tilo 0.562 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<21>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<23>
+ SLICE_X74Y3.G1 net (fanout=1) 0.600 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/mux_out<7>
------------------------------------------------- ---------------------------
- Total 3.644ns (1.939ns logic, 1.705ns route)
- (53.2% logic, 46.8% route)
+ Total 3.699ns (1.877ns logic, 1.822ns route)
+ (50.7% logic, 49.3% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_J_CLK = PERIOD TIMEGRP "J_CLK" 30 ns HIGH 50%;
- 5151 paths analyzed, 736 endpoints analyzed, 0 failing endpoints
+ 5162 paths analyzed, 737 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
- Minimum period is 12.930ns.
+ Minimum period is 15.303ns.
--------------------------------------------------------------------------------
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO (SLICE_X59Y127.F4), 795 paths
+Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO (SLICE_X68Y54.G1), 795 paths
--------------------------------------------------------------------------------
-Slack (setup path): 17.070ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_icon_pro/U0/U_ICON/U_SYNC/U_SYNC (FF)
+Slack (setup path): 14.697ns (requirement - (data path - clock path skew + uncertainty))
+ Source: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[13].I_NE0.U_TARGET (FF)
Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO (FF)
Requirement: 30.000ns
- Data Path Delay: 12.930ns (Levels of Logic = 10)
+ Data Path Delay: 15.303ns (Levels of Logic = 10)
Clock Path Skew: 0.000ns
Source Clock: icon_control0<0> rising at 0.000ns
Destination Clock: icon_control0<0> rising at 30.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path: U_icon_pro/U0/U_ICON/U_SYNC/U_SYNC to U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
+ Maximum Data Path: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[13].I_NE0.U_TARGET to U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X75Y135.YQ Tcko 0.524 U_icon_pro/U0/U_ICON/iSYNC
- U_icon_pro/U0/U_ICON/U_SYNC/U_SYNC
- SLICE_X72Y128.F1 net (fanout=2) 0.606 U_icon_pro/U0/U_ICON/iSYNC
- SLICE_X72Y128.X Tilo 0.601 U_icon_pro/U0/U_ICON/iCORE_ID<3>
- U_icon_pro/U0/U_ICON/U_CTRL_OUT/U_DATA_VALID
- SLICE_X26Y122.G2 net (fanout=32) 3.326 U_icon_pro/U0/U_ICON/U_CTRL_OUT/iDATA_VALID
- SLICE_X26Y122.Y Tilo 0.616 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[15].SI_CFG/iCFG_DIN
- U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[15].U_LCE
- SLICE_X61Y123.G1 net (fanout=66) 1.487 icon_control0<19>
- SLICE_X61Y123.COUT Topcyg 1.009 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
+ SLICE_X74Y96.YQ Tcko 0.596 U_icon_pro/U0/U_ICON/iCORE_ID<2>
+ U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[13].I_NE0.U_TARGET
+ SLICE_X75Y97.F4 net (fanout=5) 0.541 U_icon_pro/U0/U_ICON/iCORE_ID<1>
+ SLICE_X75Y97.X Tilo 0.562 U_icon_pro/U0/U_ICON/iCORE_ID<0>
+ U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[0].U_LUT
+ SLICE_X65Y27.G2 net (fanout=32) 4.348 U_icon_pro/U0/U_ICON/iCORE_ID_SEL<0>
+ SLICE_X65Y27.Y Tilo 0.561 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/I_MC_YES.U_MC/cfg_data<1>
+ U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[1].U_HCE
+ SLICE_X71Y65.G3 net (fanout=58) 2.384 icon_control0<21>
+ SLICE_X71Y65.COUT Topcyg 1.009 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<3>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
- SLICE_X61Y124.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
- SLICE_X61Y124.COUT Tbyp 0.130 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
+ SLICE_X71Y66.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
+ SLICE_X71Y66.COUT Tbyp 0.130 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<4>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
- SLICE_X61Y125.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
- SLICE_X61Y125.COUT Tbyp 0.130 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
+ SLICE_X71Y67.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
+ SLICE_X71Y67.COUT Tbyp 0.130 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<6>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
- SLICE_X61Y126.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
- SLICE_X61Y126.XB Tcinxb 0.216 icon_control0<35>
+ SLICE_X71Y68.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
+ SLICE_X71Y68.XB Tcinxb 0.216 icon_control0<35>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8>
- SLICE_X56Y131.F3 net (fanout=3) 0.768 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8>
- SLICE_X56Y131.X Tif5x 0.853 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_15_f5
+ SLICE_X67Y54.F1 net (fanout=3) 1.165 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8>
+ SLICE_X67Y54.X Tif5x 0.791 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_15_f5
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_15_f5_G
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_15_f5
- SLICE_X58Y133.G2 net (fanout=1) 0.360 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_15_f5
- SLICE_X58Y133.Y Tilo 0.616 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
+ SLICE_X66Y52.G4 net (fanout=1) 0.319 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_15_f5
+ SLICE_X66Y52.Y Tilo 0.616 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O21
- SLICE_X58Y133.F3 net (fanout=1) 0.021 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O21/O
- SLICE_X58Y133.X Tilo 0.601 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
+ SLICE_X66Y52.F4 net (fanout=1) 0.035 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O21/O
+ SLICE_X66Y52.X Tilo 0.601 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
- SLICE_X59Y127.F4 net (fanout=1) 0.464 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
- SLICE_X59Y127.CLK Tfck 0.602 U_ila_pro_0/U0/I_YES_D.U_ILA/iSTAT_DOUT
+ SLICE_X68Y54.G1 net (fanout=1) 0.628 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
+ SLICE_X68Y54.CLK Tgck 0.671 U_ila_pro_0/U0/I_YES_D.U_ILA/iSTAT_DOUT
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O96
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
------------------------------------------------- ---------------------------
- Total 12.930ns (5.898ns logic, 7.032ns route)
- (45.6% logic, 54.4% route)
+ Total 15.303ns (5.883ns logic, 9.420ns route)
+ (38.4% logic, 61.6% route)
--------------------------------------------------------------------------------
-Slack (setup path): 17.502ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET (FF)
+Slack (setup path): 14.831ns (requirement - (data path - clock path skew + uncertainty))
+ Source: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[15].I_EQ0.U_TARGET (FF)
Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO (FF)
Requirement: 30.000ns
- Data Path Delay: 12.498ns (Levels of Logic = 10)
+ Data Path Delay: 15.169ns (Levels of Logic = 10)
Clock Path Skew: 0.000ns
Source Clock: icon_control0<0> rising at 0.000ns
Destination Clock: icon_control0<0> rising at 30.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET to U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
+ Maximum Data Path: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[15].I_EQ0.U_TARGET to U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X70Y129.YQ Tcko 0.596 U_icon_pro/U0/U_ICON/iCORE_ID<0>
- U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET
- SLICE_X71Y129.F2 net (fanout=5) 0.953 U_icon_pro/U0/U_ICON/iCORE_ID<0>
- SLICE_X71Y129.X Tilo 0.562 U_icon_pro/U0/U_ICON/U_CMD/iTARGET<11>
+ SLICE_X75Y97.YQ Tcko 0.524 U_icon_pro/U0/U_ICON/iCORE_ID<0>
+ U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[15].I_EQ0.U_TARGET
+ SLICE_X75Y97.F1 net (fanout=4) 0.479 U_icon_pro/U0/U_ICON/iCORE_ID<3>
+ SLICE_X75Y97.X Tilo 0.562 U_icon_pro/U0/U_ICON/iCORE_ID<0>
U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[0].U_LUT
- SLICE_X26Y122.G4 net (fanout=32) 2.514 U_icon_pro/U0/U_ICON/iCORE_ID_SEL<0>
- SLICE_X26Y122.Y Tilo 0.616 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[15].SI_CFG/iCFG_DIN
- U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[15].U_LCE
- SLICE_X61Y123.G1 net (fanout=66) 1.487 icon_control0<19>
- SLICE_X61Y123.COUT Topcyg 1.009 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
+ SLICE_X65Y27.G2 net (fanout=32) 4.348 U_icon_pro/U0/U_ICON/iCORE_ID_SEL<0>
+ SLICE_X65Y27.Y Tilo 0.561 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/I_MC_YES.U_MC/cfg_data<1>
+ U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[1].U_HCE
+ SLICE_X71Y65.G3 net (fanout=58) 2.384 icon_control0<21>
+ SLICE_X71Y65.COUT Topcyg 1.009 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<3>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
- SLICE_X61Y124.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
- SLICE_X61Y124.COUT Tbyp 0.130 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
+ SLICE_X71Y66.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
+ SLICE_X71Y66.COUT Tbyp 0.130 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<4>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
- SLICE_X61Y125.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
- SLICE_X61Y125.COUT Tbyp 0.130 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
+ SLICE_X71Y67.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
+ SLICE_X71Y67.COUT Tbyp 0.130 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<6>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
- SLICE_X61Y126.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
- SLICE_X61Y126.XB Tcinxb 0.216 icon_control0<35>
+ SLICE_X71Y68.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
+ SLICE_X71Y68.XB Tcinxb 0.216 icon_control0<35>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8>
- SLICE_X56Y131.F3 net (fanout=3) 0.768 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8>
- SLICE_X56Y131.X Tif5x 0.853 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_15_f5
+ SLICE_X67Y54.F1 net (fanout=3) 1.165 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8>
+ SLICE_X67Y54.X Tif5x 0.791 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_15_f5
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_15_f5_G
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_15_f5
- SLICE_X58Y133.G2 net (fanout=1) 0.360 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_15_f5
- SLICE_X58Y133.Y Tilo 0.616 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
+ SLICE_X66Y52.G4 net (fanout=1) 0.319 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_15_f5
+ SLICE_X66Y52.Y Tilo 0.616 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O21
- SLICE_X58Y133.F3 net (fanout=1) 0.021 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O21/O
- SLICE_X58Y133.X Tilo 0.601 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
+ SLICE_X66Y52.F4 net (fanout=1) 0.035 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O21/O
+ SLICE_X66Y52.X Tilo 0.601 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
- SLICE_X59Y127.F4 net (fanout=1) 0.464 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
- SLICE_X59Y127.CLK Tfck 0.602 U_ila_pro_0/U0/I_YES_D.U_ILA/iSTAT_DOUT
+ SLICE_X68Y54.G1 net (fanout=1) 0.628 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
+ SLICE_X68Y54.CLK Tgck 0.671 U_ila_pro_0/U0/I_YES_D.U_ILA/iSTAT_DOUT
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O96
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
------------------------------------------------- ---------------------------
- Total 12.498ns (5.931ns logic, 6.567ns route)
- (47.5% logic, 52.5% route)
+ Total 15.169ns (5.811ns logic, 9.358ns route)
+ (38.3% logic, 61.7% route)
--------------------------------------------------------------------------------
-Slack (setup path): 17.509ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[15].I_EQ0.U_TARGET (FF)
+Slack (setup path): 14.843ns (requirement - (data path - clock path skew + uncertainty))
+ Source: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET (FF)
Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO (FF)
Requirement: 30.000ns
- Data Path Delay: 12.491ns (Levels of Logic = 10)
+ Data Path Delay: 15.157ns (Levels of Logic = 10)
Clock Path Skew: 0.000ns
Source Clock: icon_control0<0> rising at 0.000ns
Destination Clock: icon_control0<0> rising at 30.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[15].I_EQ0.U_TARGET to U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
+ Maximum Data Path: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET to U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X72Y128.YQ Tcko 0.596 U_icon_pro/U0/U_ICON/iCORE_ID<3>
- U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[15].I_EQ0.U_TARGET
- SLICE_X71Y129.F3 net (fanout=4) 0.946 U_icon_pro/U0/U_ICON/iCORE_ID<3>
- SLICE_X71Y129.X Tilo 0.562 U_icon_pro/U0/U_ICON/U_CMD/iTARGET<11>
+ SLICE_X75Y97.XQ Tcko 0.495 U_icon_pro/U0/U_ICON/iCORE_ID<0>
+ U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET
+ SLICE_X75Y97.F2 net (fanout=5) 0.496 U_icon_pro/U0/U_ICON/iCORE_ID<0>
+ SLICE_X75Y97.X Tilo 0.562 U_icon_pro/U0/U_ICON/iCORE_ID<0>
U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[0].U_LUT
- SLICE_X26Y122.G4 net (fanout=32) 2.514 U_icon_pro/U0/U_ICON/iCORE_ID_SEL<0>
- SLICE_X26Y122.Y Tilo 0.616 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[15].SI_CFG/iCFG_DIN
- U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[15].U_LCE
- SLICE_X61Y123.G1 net (fanout=66) 1.487 icon_control0<19>
- SLICE_X61Y123.COUT Topcyg 1.009 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
+ SLICE_X65Y27.G2 net (fanout=32) 4.348 U_icon_pro/U0/U_ICON/iCORE_ID_SEL<0>
+ SLICE_X65Y27.Y Tilo 0.561 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/I_MC_YES.U_MC/cfg_data<1>
+ U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[1].U_HCE
+ SLICE_X71Y65.G3 net (fanout=58) 2.384 icon_control0<21>
+ SLICE_X71Y65.COUT Topcyg 1.009 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<3>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
- SLICE_X61Y124.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
- SLICE_X61Y124.COUT Tbyp 0.130 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
+ SLICE_X71Y66.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
+ SLICE_X71Y66.COUT Tbyp 0.130 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<4>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
- SLICE_X61Y125.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
- SLICE_X61Y125.COUT Tbyp 0.130 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
+ SLICE_X71Y67.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
+ SLICE_X71Y67.COUT Tbyp 0.130 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<6>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
- SLICE_X61Y126.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
- SLICE_X61Y126.XB Tcinxb 0.216 icon_control0<35>
+ SLICE_X71Y68.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
+ SLICE_X71Y68.XB Tcinxb 0.216 icon_control0<35>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8>
- SLICE_X56Y131.F3 net (fanout=3) 0.768 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8>
- SLICE_X56Y131.X Tif5x 0.853 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_15_f5
+ SLICE_X67Y54.F1 net (fanout=3) 1.165 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8>
+ SLICE_X67Y54.X Tif5x 0.791 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_15_f5
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_15_f5_G
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_15_f5
- SLICE_X58Y133.G2 net (fanout=1) 0.360 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_15_f5
- SLICE_X58Y133.Y Tilo 0.616 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
+ SLICE_X66Y52.G4 net (fanout=1) 0.319 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_15_f5
+ SLICE_X66Y52.Y Tilo 0.616 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O21
- SLICE_X58Y133.F3 net (fanout=1) 0.021 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O21/O
- SLICE_X58Y133.X Tilo 0.601 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
+ SLICE_X66Y52.F4 net (fanout=1) 0.035 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O21/O
+ SLICE_X66Y52.X Tilo 0.601 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
- SLICE_X59Y127.F4 net (fanout=1) 0.464 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
- SLICE_X59Y127.CLK Tfck 0.602 U_ila_pro_0/U0/I_YES_D.U_ILA/iSTAT_DOUT
+ SLICE_X68Y54.G1 net (fanout=1) 0.628 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O48
+ SLICE_X68Y54.CLK Tgck 0.671 U_ila_pro_0/U0/I_YES_D.U_ILA/iSTAT_DOUT
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O96
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
------------------------------------------------- ---------------------------
- Total 12.491ns (5.931ns logic, 6.560ns route)
- (47.5% logic, 52.5% route)
+ Total 15.157ns (5.782ns logic, 9.375ns route)
+ (38.1% logic, 61.9% route)
--------------------------------------------------------------------------------
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO (SLICE_X59Y127.F1), 354 paths
+Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO (SLICE_X68Y54.G4), 354 paths
--------------------------------------------------------------------------------
-Slack (setup path): 19.277ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_icon_pro/U0/U_ICON/U_SYNC/U_SYNC (FF)
+Slack (setup path): 16.773ns (requirement - (data path - clock path skew + uncertainty))
+ Source: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[13].I_NE0.U_TARGET (FF)
Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO (FF)
Requirement: 30.000ns
- Data Path Delay: 10.723ns (Levels of Logic = 8)
+ Data Path Delay: 13.227ns (Levels of Logic = 8)
Clock Path Skew: 0.000ns
Source Clock: icon_control0<0> rising at 0.000ns
Destination Clock: icon_control0<0> rising at 30.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path: U_icon_pro/U0/U_ICON/U_SYNC/U_SYNC to U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
+ Maximum Data Path: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[13].I_NE0.U_TARGET to U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X75Y135.YQ Tcko 0.524 U_icon_pro/U0/U_ICON/iSYNC
- U_icon_pro/U0/U_ICON/U_SYNC/U_SYNC
- SLICE_X72Y128.F1 net (fanout=2) 0.606 U_icon_pro/U0/U_ICON/iSYNC
- SLICE_X72Y128.X Tilo 0.601 U_icon_pro/U0/U_ICON/iCORE_ID<3>
- U_icon_pro/U0/U_ICON/U_CTRL_OUT/U_DATA_VALID
- SLICE_X26Y122.G2 net (fanout=32) 3.326 U_icon_pro/U0/U_ICON/U_CTRL_OUT/iDATA_VALID
- SLICE_X26Y122.Y Tilo 0.616 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[15].SI_CFG/iCFG_DIN
- U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[15].U_LCE
- SLICE_X61Y123.G1 net (fanout=66) 1.487 icon_control0<19>
- SLICE_X61Y123.COUT Topcyg 1.009 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
+ SLICE_X74Y96.YQ Tcko 0.596 U_icon_pro/U0/U_ICON/iCORE_ID<2>
+ U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[13].I_NE0.U_TARGET
+ SLICE_X75Y97.F4 net (fanout=5) 0.541 U_icon_pro/U0/U_ICON/iCORE_ID<1>
+ SLICE_X75Y97.X Tilo 0.562 U_icon_pro/U0/U_ICON/iCORE_ID<0>
+ U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[0].U_LUT
+ SLICE_X65Y27.G2 net (fanout=32) 4.348 U_icon_pro/U0/U_ICON/iCORE_ID_SEL<0>
+ SLICE_X65Y27.Y Tilo 0.561 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/I_MC_YES.U_MC/cfg_data<1>
+ U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[1].U_HCE
+ SLICE_X71Y65.G3 net (fanout=58) 2.384 icon_control0<21>
+ SLICE_X71Y65.COUT Topcyg 1.009 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<3>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
- SLICE_X61Y124.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
- SLICE_X61Y124.COUT Tbyp 0.130 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
+ SLICE_X71Y66.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
+ SLICE_X71Y66.COUT Tbyp 0.130 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<4>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
- SLICE_X61Y125.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
- SLICE_X61Y125.COUT Tbyp 0.130 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
+ SLICE_X71Y67.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
+ SLICE_X71Y67.COUT Tbyp 0.130 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<6>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
- SLICE_X61Y126.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
- SLICE_X61Y126.XB Tcinxb 0.216 icon_control0<35>
+ SLICE_X71Y68.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
+ SLICE_X71Y68.XB Tcinxb 0.216 icon_control0<35>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8>
- SLICE_X58Y131.F3 net (fanout=3) 0.535 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8>
- SLICE_X58Y131.X Tilo 0.601 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2
+ SLICE_X67Y55.G2 net (fanout=3) 0.878 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8>
+ SLICE_X67Y55.Y Tilo 0.561 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/iSTAT<16>
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2
- SLICE_X59Y127.F1 net (fanout=1) 0.340 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2
- SLICE_X59Y127.CLK Tfck 0.602 U_ila_pro_0/U0/I_YES_D.U_ILA/iSTAT_DOUT
+ SLICE_X68Y54.G4 net (fanout=1) 0.640 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2
+ SLICE_X68Y54.CLK Tgck 0.671 U_ila_pro_0/U0/I_YES_D.U_ILA/iSTAT_DOUT
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O96
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
------------------------------------------------- ---------------------------
- Total 10.723ns (4.429ns logic, 6.294ns route)
- (41.3% logic, 58.7% route)
+ Total 13.227ns (4.436ns logic, 8.791ns route)
+ (33.5% logic, 66.5% route)
--------------------------------------------------------------------------------
-Slack (setup path): 19.709ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET (FF)
+Slack (setup path): 16.907ns (requirement - (data path - clock path skew + uncertainty))
+ Source: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[15].I_EQ0.U_TARGET (FF)
Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO (FF)
Requirement: 30.000ns
- Data Path Delay: 10.291ns (Levels of Logic = 8)
+ Data Path Delay: 13.093ns (Levels of Logic = 8)
Clock Path Skew: 0.000ns
Source Clock: icon_control0<0> rising at 0.000ns
Destination Clock: icon_control0<0> rising at 30.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET to U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
+ Maximum Data Path: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[15].I_EQ0.U_TARGET to U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X70Y129.YQ Tcko 0.596 U_icon_pro/U0/U_ICON/iCORE_ID<0>
- U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET
- SLICE_X71Y129.F2 net (fanout=5) 0.953 U_icon_pro/U0/U_ICON/iCORE_ID<0>
- SLICE_X71Y129.X Tilo 0.562 U_icon_pro/U0/U_ICON/U_CMD/iTARGET<11>
+ SLICE_X75Y97.YQ Tcko 0.524 U_icon_pro/U0/U_ICON/iCORE_ID<0>
+ U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[15].I_EQ0.U_TARGET
+ SLICE_X75Y97.F1 net (fanout=4) 0.479 U_icon_pro/U0/U_ICON/iCORE_ID<3>
+ SLICE_X75Y97.X Tilo 0.562 U_icon_pro/U0/U_ICON/iCORE_ID<0>
U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[0].U_LUT
- SLICE_X26Y122.G4 net (fanout=32) 2.514 U_icon_pro/U0/U_ICON/iCORE_ID_SEL<0>
- SLICE_X26Y122.Y Tilo 0.616 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[15].SI_CFG/iCFG_DIN
- U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[15].U_LCE
- SLICE_X61Y123.G1 net (fanout=66) 1.487 icon_control0<19>
- SLICE_X61Y123.COUT Topcyg 1.009 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
+ SLICE_X65Y27.G2 net (fanout=32) 4.348 U_icon_pro/U0/U_ICON/iCORE_ID_SEL<0>
+ SLICE_X65Y27.Y Tilo 0.561 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/I_MC_YES.U_MC/cfg_data<1>
+ U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[1].U_HCE
+ SLICE_X71Y65.G3 net (fanout=58) 2.384 icon_control0<21>
+ SLICE_X71Y65.COUT Topcyg 1.009 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<3>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
- SLICE_X61Y124.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
- SLICE_X61Y124.COUT Tbyp 0.130 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
+ SLICE_X71Y66.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
+ SLICE_X71Y66.COUT Tbyp 0.130 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<4>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
- SLICE_X61Y125.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
- SLICE_X61Y125.COUT Tbyp 0.130 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
+ SLICE_X71Y67.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
+ SLICE_X71Y67.COUT Tbyp 0.130 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<6>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
- SLICE_X61Y126.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
- SLICE_X61Y126.XB Tcinxb 0.216 icon_control0<35>
+ SLICE_X71Y68.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
+ SLICE_X71Y68.XB Tcinxb 0.216 icon_control0<35>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8>
- SLICE_X58Y131.F3 net (fanout=3) 0.535 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8>
- SLICE_X58Y131.X Tilo 0.601 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2
+ SLICE_X67Y55.G2 net (fanout=3) 0.878 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8>
+ SLICE_X67Y55.Y Tilo 0.561 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/iSTAT<16>
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2
- SLICE_X59Y127.F1 net (fanout=1) 0.340 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2
- SLICE_X59Y127.CLK Tfck 0.602 U_ila_pro_0/U0/I_YES_D.U_ILA/iSTAT_DOUT
+ SLICE_X68Y54.G4 net (fanout=1) 0.640 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2
+ SLICE_X68Y54.CLK Tgck 0.671 U_ila_pro_0/U0/I_YES_D.U_ILA/iSTAT_DOUT
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O96
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
------------------------------------------------- ---------------------------
- Total 10.291ns (4.462ns logic, 5.829ns route)
- (43.4% logic, 56.6% route)
+ Total 13.093ns (4.364ns logic, 8.729ns route)
+ (33.3% logic, 66.7% route)
--------------------------------------------------------------------------------
-Slack (setup path): 19.716ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[15].I_EQ0.U_TARGET (FF)
+Slack (setup path): 16.919ns (requirement - (data path - clock path skew + uncertainty))
+ Source: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET (FF)
Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO (FF)
Requirement: 30.000ns
- Data Path Delay: 10.284ns (Levels of Logic = 8)
+ Data Path Delay: 13.081ns (Levels of Logic = 8)
Clock Path Skew: 0.000ns
Source Clock: icon_control0<0> rising at 0.000ns
Destination Clock: icon_control0<0> rising at 30.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[15].I_EQ0.U_TARGET to U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
+ Maximum Data Path: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET to U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X72Y128.YQ Tcko 0.596 U_icon_pro/U0/U_ICON/iCORE_ID<3>
- U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[15].I_EQ0.U_TARGET
- SLICE_X71Y129.F3 net (fanout=4) 0.946 U_icon_pro/U0/U_ICON/iCORE_ID<3>
- SLICE_X71Y129.X Tilo 0.562 U_icon_pro/U0/U_ICON/U_CMD/iTARGET<11>
+ SLICE_X75Y97.XQ Tcko 0.495 U_icon_pro/U0/U_ICON/iCORE_ID<0>
+ U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET
+ SLICE_X75Y97.F2 net (fanout=5) 0.496 U_icon_pro/U0/U_ICON/iCORE_ID<0>
+ SLICE_X75Y97.X Tilo 0.562 U_icon_pro/U0/U_ICON/iCORE_ID<0>
U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[0].U_LUT
- SLICE_X26Y122.G4 net (fanout=32) 2.514 U_icon_pro/U0/U_ICON/iCORE_ID_SEL<0>
- SLICE_X26Y122.Y Tilo 0.616 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[15].SI_CFG/iCFG_DIN
- U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[15].U_LCE
- SLICE_X61Y123.G1 net (fanout=66) 1.487 icon_control0<19>
- SLICE_X61Y123.COUT Topcyg 1.009 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
+ SLICE_X65Y27.G2 net (fanout=32) 4.348 U_icon_pro/U0/U_ICON/iCORE_ID_SEL<0>
+ SLICE_X65Y27.Y Tilo 0.561 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/I_MC_YES.U_MC/cfg_data<1>
+ U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[1].U_HCE
+ SLICE_X71Y65.G3 net (fanout=58) 2.384 icon_control0<21>
+ SLICE_X71Y65.COUT Topcyg 1.009 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<3>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
- SLICE_X61Y124.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
- SLICE_X61Y124.COUT Tbyp 0.130 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
+ SLICE_X71Y66.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3>
+ SLICE_X71Y66.COUT Tbyp 0.130 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<4>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
- SLICE_X61Y125.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
- SLICE_X61Y125.COUT Tbyp 0.130 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
+ SLICE_X71Y67.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5>
+ SLICE_X71Y67.COUT Tbyp 0.130 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<6>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
- SLICE_X61Y126.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
- SLICE_X61Y126.XB Tcinxb 0.216 icon_control0<35>
+ SLICE_X71Y68.CIN net (fanout=1) 0.000 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7>
+ SLICE_X71Y68.XB Tcinxb 0.216 icon_control0<35>
U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8>
- SLICE_X58Y131.F3 net (fanout=3) 0.535 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8>
- SLICE_X58Y131.X Tilo 0.601 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2
+ SLICE_X67Y55.G2 net (fanout=3) 0.878 U_ila_pro_0/U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8>
+ SLICE_X67Y55.Y Tilo 0.561 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/iSTAT<16>
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2
- SLICE_X59Y127.F1 net (fanout=1) 0.340 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2
- SLICE_X59Y127.CLK Tfck 0.602 U_ila_pro_0/U0/I_YES_D.U_ILA/iSTAT_DOUT
+ SLICE_X68Y54.G4 net (fanout=1) 0.640 U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2
+ SLICE_X68Y54.CLK Tgck 0.671 U_ila_pro_0/U0/I_YES_D.U_ILA/iSTAT_DOUT
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O96
U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_TDO
------------------------------------------------- ---------------------------
- Total 10.284ns (4.462ns logic, 5.822ns route)
- (43.4% logic, 56.6% route)
+ Total 13.081ns (4.335ns logic, 8.746ns route)
+ (33.1% logic, 66.9% route)
--------------------------------------------------------------------------------
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[9].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i (RAMB16_X1Y0.ENA), 11 paths
+Paths for end point U_icon_pro/U0/U_ICON/U_TDO_reg (SLICE_X75Y96.G1), 49 paths
--------------------------------------------------------------------------------
-Slack (setup path): 19.338ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[11].I_NE0.U_TARGET (FF)
- Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[9].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i (RAM)
+Slack (setup path): 18.659ns (requirement - (data path - clock path skew + uncertainty))
+ Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[2].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i (RAM)
+ Destination: U_icon_pro/U0/U_ICON/U_TDO_reg (FF)
Requirement: 30.000ns
- Data Path Delay: 10.662ns (Levels of Logic = 2)
+ Data Path Delay: 11.341ns (Levels of Logic = 6)
Clock Path Skew: 0.000ns
Source Clock: icon_control0<0> rising at 0.000ns
Destination Clock: icon_control0<0> rising at 30.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[11].I_NE0.U_TARGET to U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[9].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X71Y129.YQ Tcko 0.524 U_icon_pro/U0/U_ICON/U_CMD/iTARGET<11>
- U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[11].I_NE0.U_TARGET
- SLICE_X62Y116.F3 net (fanout=17) 1.616 U_icon_pro/U0/U_ICON/U_CMD/iTARGET<11>
- SLICE_X62Y116.X Tilo 0.601 U_icon_pro/U0/U_ICON/iCOMMAND_SEL<2>
- U_icon_pro/U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[2].U_LUT
- SLICE_X72Y118.G1 net (fanout=2) 0.905 U_icon_pro/U0/U_ICON/iCOMMAND_SEL<2>
- SLICE_X72Y118.Y Tilo 0.616 icon_control0<3>
- U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[2].U_LCE
- RAMB16_X1Y0.ENA net (fanout=26) 5.982 icon_control0<6>
- RAMB16_X1Y0.CLKA Trcck_ENA 0.418 U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[9].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[9].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i
- ------------------------------------------------- ---------------------------
- Total 10.662ns (2.159ns logic, 8.503ns route)
- (20.2% logic, 79.8% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 19.715ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[6].I_NE0.U_TARGET (FF)
- Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[9].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i (RAM)
+ Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[2].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i to U_icon_pro/U0/U_ICON/U_TDO_reg
+ Location Delay type Delay(ns) Physical Resource
+ Logical Resource(s)
+ ------------------------------------------------- -------------------
+ RAMB16_X1Y11.DOA0 Trcko_DOWA 2.107 U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[2].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[2].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i
+ SLICE_X75Y57.F3 net (fanout=1) 2.931 U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/localDOA<2>
+ SLICE_X75Y57.F5 Tif5 0.688 U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_9_f5
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_102
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_9_f5
+ SLICE_X75Y56.FXINB net (fanout=1) 0.000 U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_9_f5
+ SLICE_X75Y56.FX Tinbfx 0.202 U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_8_f51
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_7_f6
+ SLICE_X74Y57.FXINB net (fanout=1) 0.000 U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_7_f6
+ SLICE_X74Y57.Y Tif6y 0.315 U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_5_f7
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_5_f7
+ SLICE_X62Y57.F1 net (fanout=1) 0.917 U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_5_f7
+ SLICE_X62Y57.X Tilo 0.601 U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/muxAddrFF<4>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/muxAddrFF<4>
+ SLICE_X69Y56.F1 net (fanout=1) 0.619 U_ila_pro_0/U0/I_YES_D.U_ILA/iDATA_DOUT
+ SLICE_X69Y56.X Tilo 0.562 icon_control0<3>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_DOUT
+ SLICE_X75Y96.G1 net (fanout=1) 1.568 icon_control0<3>
+ SLICE_X75Y96.CLK Tgck 0.831 U_icon_pro/U0/U_ICON/iTDO
+ U_icon_pro/U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_4
+ U_icon_pro/U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_2_f5
+ U_icon_pro/U0/U_ICON/U_TDO_reg
+ ------------------------------------------------- ---------------------------
+ Total 11.341ns (5.306ns logic, 6.035ns route)
+ (46.8% logic, 53.2% route)
+
+--------------------------------------------------------------------------------
+Slack (setup path): 18.773ns (requirement - (data path - clock path skew + uncertainty))
+ Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i (RAM)
+ Destination: U_icon_pro/U0/U_ICON/U_TDO_reg (FF)
Requirement: 30.000ns
- Data Path Delay: 10.285ns (Levels of Logic = 2)
+ Data Path Delay: 11.227ns (Levels of Logic = 6)
Clock Path Skew: 0.000ns
Source Clock: icon_control0<0> rising at 0.000ns
Destination Clock: icon_control0<0> rising at 30.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[6].I_NE0.U_TARGET to U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[9].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X71Y126.YQ Tcko 0.524 U_icon_pro/U0/U_ICON/iCOMMAND_GRP<0>
- U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[6].I_NE0.U_TARGET
- SLICE_X63Y127.G4 net (fanout=3) 0.848 U_icon_pro/U0/U_ICON/iCOMMAND_GRP<0>
- SLICE_X63Y127.Y Tilo 0.561 icon_control0<4>
- U_icon_pro/U0/U_ICON/U_CTRL_OUT/U_CMDGRP0
- SLICE_X72Y118.G4 net (fanout=16) 1.336 U_icon_pro/U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL<0>
- SLICE_X72Y118.Y Tilo 0.616 icon_control0<3>
- U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[2].U_LCE
- RAMB16_X1Y0.ENA net (fanout=26) 5.982 icon_control0<6>
- RAMB16_X1Y0.CLKA Trcck_ENA 0.418 U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[9].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[9].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i
- ------------------------------------------------- ---------------------------
- Total 10.285ns (2.119ns logic, 8.166ns route)
- (20.6% logic, 79.4% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 19.836ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET (FF)
- Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[9].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i (RAM)
+ Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i to U_icon_pro/U0/U_ICON/U_TDO_reg
+ Location Delay type Delay(ns) Physical Resource
+ Logical Resource(s)
+ ------------------------------------------------- -------------------
+ RAMB16_X0Y4.DOA0 Trcko_DOWA 2.107 U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i
+ SLICE_X75Y57.G4 net (fanout=1) 2.817 U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/localDOA<0>
+ SLICE_X75Y57.F5 Tif5 0.688 U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_9_f5
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_11
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_9_f5
+ SLICE_X75Y56.FXINB net (fanout=1) 0.000 U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_9_f5
+ SLICE_X75Y56.FX Tinbfx 0.202 U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_8_f51
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_7_f6
+ SLICE_X74Y57.FXINB net (fanout=1) 0.000 U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_7_f6
+ SLICE_X74Y57.Y Tif6y 0.315 U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_5_f7
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_5_f7
+ SLICE_X62Y57.F1 net (fanout=1) 0.917 U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_5_f7
+ SLICE_X62Y57.X Tilo 0.601 U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/muxAddrFF<4>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/muxAddrFF<4>
+ SLICE_X69Y56.F1 net (fanout=1) 0.619 U_ila_pro_0/U0/I_YES_D.U_ILA/iDATA_DOUT
+ SLICE_X69Y56.X Tilo 0.562 icon_control0<3>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_DOUT
+ SLICE_X75Y96.G1 net (fanout=1) 1.568 icon_control0<3>
+ SLICE_X75Y96.CLK Tgck 0.831 U_icon_pro/U0/U_ICON/iTDO
+ U_icon_pro/U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_4
+ U_icon_pro/U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_2_f5
+ U_icon_pro/U0/U_ICON/U_TDO_reg
+ ------------------------------------------------- ---------------------------
+ Total 11.227ns (5.306ns logic, 5.921ns route)
+ (47.3% logic, 52.7% route)
+
+--------------------------------------------------------------------------------
+Slack (setup path): 19.108ns (requirement - (data path - clock path skew + uncertainty))
+ Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[1].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i (RAM)
+ Destination: U_icon_pro/U0/U_ICON/U_TDO_reg (FF)
Requirement: 30.000ns
- Data Path Delay: 10.164ns (Levels of Logic = 2)
+ Data Path Delay: 10.892ns (Levels of Logic = 6)
Clock Path Skew: 0.000ns
Source Clock: icon_control0<0> rising at 0.000ns
Destination Clock: icon_control0<0> rising at 30.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET to U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[9].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i
+ Maximum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[1].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i to U_icon_pro/U0/U_ICON/U_TDO_reg
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X70Y129.YQ Tcko 0.596 U_icon_pro/U0/U_ICON/iCORE_ID<0>
- U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET
- SLICE_X71Y129.F2 net (fanout=5) 0.953 U_icon_pro/U0/U_ICON/iCORE_ID<0>
- SLICE_X71Y129.X Tilo 0.562 U_icon_pro/U0/U_ICON/U_CMD/iTARGET<11>
- U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[0].U_LUT
- SLICE_X72Y118.G3 net (fanout=32) 1.037 U_icon_pro/U0/U_ICON/iCORE_ID_SEL<0>
- SLICE_X72Y118.Y Tilo 0.616 icon_control0<3>
- U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[2].U_LCE
- RAMB16_X1Y0.ENA net (fanout=26) 5.982 icon_control0<6>
- RAMB16_X1Y0.CLKA Trcck_ENA 0.418 U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[9].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[9].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i
+ RAMB16_X0Y5.DOA0 Trcko_DOWA 2.107 U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[1].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[1].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i
+ SLICE_X75Y57.G2 net (fanout=1) 2.482 U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/localDOA<1>
+ SLICE_X75Y57.F5 Tif5 0.688 U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_9_f5
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_11
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_9_f5
+ SLICE_X75Y56.FXINB net (fanout=1) 0.000 U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_9_f5
+ SLICE_X75Y56.FX Tinbfx 0.202 U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_8_f51
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_7_f6
+ SLICE_X74Y57.FXINB net (fanout=1) 0.000 U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_7_f6
+ SLICE_X74Y57.Y Tif6y 0.315 U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_5_f7
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_5_f7
+ SLICE_X62Y57.F1 net (fanout=1) 0.917 U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/I_MUX.U_RD_DATA/U_CS_MUX/I5.U_MUX32/Mmux_O_5_f7
+ SLICE_X62Y57.X Tilo 0.601 U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/muxAddrFF<4>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/muxAddrFF<4>
+ SLICE_X69Y56.F1 net (fanout=1) 0.619 U_ila_pro_0/U0/I_YES_D.U_ILA/iDATA_DOUT
+ SLICE_X69Y56.X Tilo 0.562 icon_control0<3>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_DOUT
+ SLICE_X75Y96.G1 net (fanout=1) 1.568 icon_control0<3>
+ SLICE_X75Y96.CLK Tgck 0.831 U_icon_pro/U0/U_ICON/iTDO
+ U_icon_pro/U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_4
+ U_icon_pro/U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_2_f5
+ U_icon_pro/U0/U_ICON/U_TDO_reg
------------------------------------------------- ---------------------------
- Total 10.164ns (2.192ns logic, 7.972ns route)
- (21.6% logic, 78.4% route)
+ Total 10.892ns (5.306ns logic, 5.586ns route)
+ (48.7% logic, 51.3% route)
--------------------------------------------------------------------------------
Hold Paths: TS_J_CLK = PERIOD TIMEGRP "J_CLK" 30 ns HIGH 50%;
--------------------------------------------------------------------------------
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[42].U_REG (SLICE_X25Y123.BX), 1 path
+Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.I_SRL.U_SELX (SLICE_X74Y18.BY), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.798ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[43].U_REG (FF)
- Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[42].U_REG (FF)
+Slack (hold path): 0.645ns (requirement - (clock path skew + uncertainty - data path))
+ Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[15].U_SEL (FF)
+ Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.I_SRL.U_SELX (FF)
Requirement: 0.000ns
- Data Path Delay: 0.798ns (Levels of Logic = 0)
+ Data Path Delay: 0.645ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: icon_control0<0> rising at 30.000ns
Destination Clock: icon_control0<0> rising at 30.000ns
Clock Uncertainty: 0.000ns
- Minimum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[43].U_REG to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[42].U_REG
+ Minimum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[15].U_SEL to U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.I_SRL.U_SELX
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X24Y123.XQ Tcko 0.417 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<43>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[43].U_REG
- SLICE_X25Y123.BX net (fanout=2) 0.319 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<43>
- SLICE_X25Y123.CLK Tckdi (-Th) -0.062 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<42>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[42].U_REG
+ SLICE_X72Y18.YQ Tcko 0.477 U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec<16>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[15].U_SEL
+ SLICE_X74Y18.BY net (fanout=1) 0.298 U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec<16>
+ SLICE_X74Y18.CLK Tdh (-Th) 0.130 U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data<0>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.I_SRL.U_SELX
------------------------------------------------- ---------------------------
- Total 0.798ns (0.479ns logic, 0.319ns route)
- (60.0% logic, 40.0% route)
+ Total 0.645ns (0.347ns logic, 0.298ns route)
+ (53.8% logic, 46.2% route)
--------------------------------------------------------------------------------
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[40].U_REG (SLICE_X25Y126.BX), 1 path
+Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[19].U_REG (SLICE_X73Y0.BX), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.799ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[41].U_REG (FF)
- Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[40].U_REG (FF)
+Slack (hold path): 0.786ns (requirement - (clock path skew + uncertainty - data path))
+ Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[20].U_REG (FF)
+ Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[19].U_REG (FF)
Requirement: 0.000ns
- Data Path Delay: 0.799ns (Levels of Logic = 0)
+ Data Path Delay: 0.786ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: icon_control0<0> rising at 30.000ns
Destination Clock: icon_control0<0> rising at 30.000ns
Clock Uncertainty: 0.000ns
- Minimum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[41].U_REG to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[40].U_REG
+ Minimum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[20].U_REG to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[19].U_REG
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X25Y126.YQ Tcko 0.419 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<40>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[41].U_REG
- SLICE_X25Y126.BX net (fanout=2) 0.318 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<41>
- SLICE_X25Y126.CLK Tckdi (-Th) -0.062 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<40>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[40].U_REG
+ SLICE_X73Y3.XQ Tcko 0.396 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<20>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[20].U_REG
+ SLICE_X73Y0.BX net (fanout=2) 0.328 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<20>
+ SLICE_X73Y0.CLK Tckdi (-Th) -0.062 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<19>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[19].U_REG
------------------------------------------------- ---------------------------
- Total 0.799ns (0.481ns logic, 0.318ns route)
- (60.2% logic, 39.8% route)
+ Total 0.786ns (0.458ns logic, 0.328ns route)
+ (58.3% logic, 41.7% route)
--------------------------------------------------------------------------------
-Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[7].U_REG (SLICE_X18Y123.BX), 1 path
+Paths for end point U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[9].U_REG (SLICE_X75Y4.BX), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.807ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[8].U_REG (FF)
- Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[7].U_REG (FF)
+Slack (hold path): 0.798ns (requirement - (clock path skew + uncertainty - data path))
+ Source: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[10].U_REG (FF)
+ Destination: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[9].U_REG (FF)
Requirement: 0.000ns
- Data Path Delay: 0.807ns (Levels of Logic = 0)
+ Data Path Delay: 0.798ns (Levels of Logic = 0)
Clock Path Skew: 0.000ns
Source Clock: icon_control0<0> rising at 30.000ns
Destination Clock: icon_control0<0> rising at 30.000ns
Clock Uncertainty: 0.000ns
- Minimum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[8].U_REG to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[7].U_REG
+ Minimum Data Path: U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[10].U_REG to U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[9].U_REG
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X19Y124.YQ Tcko 0.419 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<8>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[8].U_REG
- SLICE_X18Y123.BX net (fanout=2) 0.286 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<8>
- SLICE_X18Y123.CLK Tckdi (-Th) -0.102 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<7>
- U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[7].U_REG
+ SLICE_X74Y5.XQ Tcko 0.417 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<10>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[10].U_REG
+ SLICE_X75Y4.BX net (fanout=2) 0.319 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<10>
+ SLICE_X75Y4.CLK Tckdi (-Th) -0.062 U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/sel<9>
+ U_ila_pro_0/U0/I_YES_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_CFG.U_CFG_FDS[9].U_REG
------------------------------------------------- ---------------------------
- Total 0.807ns (0.521ns logic, 0.286ns route)
- (64.6% logic, 35.4% route)
+ Total 0.798ns (0.479ns logic, 0.319ns route)
+ (60.0% logic, 40.0% route)
--------------------------------------------------------------------------------
@@ -1521,7 +1558,7 @@ Slack: 27.237ns (period - min period limit)
Min period limit: 2.763ns (361.925MHz) (Trper_CLKA)
Physical resource: U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[9].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i/CLKA
Logical resource: U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[9].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i/CLKA
- Location pin: RAMB16_X1Y0.CLKA
+ Location pin: RAMB16_X1Y1.CLKA
Clock network: icon_control0<0>
--------------------------------------------------------------------------------
Slack: 27.237ns (period - min period limit)
@@ -1529,7 +1566,7 @@ Slack: 27.237ns (period - min period limit)
Min period limit: 2.763ns (361.925MHz) (Trper_CLKA)
Physical resource: U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[8].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i/CLKA
Logical resource: U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[8].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i/CLKA
- Location pin: RAMB16_X0Y10.CLKA
+ Location pin: RAMB16_X1Y2.CLKA
Clock network: icon_control0<0>
--------------------------------------------------------------------------------
Slack: 27.237ns (period - min period limit)
@@ -1537,7 +1574,7 @@ Slack: 27.237ns (period - min period limit)
Min period limit: 2.763ns (361.925MHz) (Trper_CLKA)
Physical resource: U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[7].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i/CLKA
Logical resource: U_ila_pro_0/U0/I_YES_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[7].U_BRAM/ram_rt1_s1_s16_if.ram_rt1_s1_s16_i/CLKA
- Location pin: RAMB16_X0Y7.CLKA
+ Location pin: RAMB16_X1Y0.CLKA
Clock network: icon_control0<0>
--------------------------------------------------------------------------------
@@ -1556,7 +1593,7 @@ Slack: 0.500ns (period - min period limit)
Min period limit: 4.500ns (222.222MHz) ()
Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/CLKB
Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/CLKB
- Location pin: RAMB16_X1Y5.CLKB
+ Location pin: RAMB16_X0Y10.CLKB
Clock network: cmp_gn4124_core/clk_p
--------------------------------------------------------------------------------
Slack: 0.500ns (period - min period limit)
@@ -1564,7 +1601,7 @@ Slack: 0.500ns (period - min period limit)
Min period limit: 4.500ns (222.222MHz) ()
Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_noinit.ram/dpram.dp36x36.ram/CLKA
Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_noinit.ram/dpram.dp36x36.ram/CLKA
- Location pin: RAMB16_X0Y13.CLKA
+ Location pin: RAMB16_X1Y12.CLKA
Clock network: cmp_gn4124_core/clk_p
--------------------------------------------------------------------------------
Slack: 0.500ns (period - min period limit)
@@ -1572,432 +1609,420 @@ Slack: 0.500ns (period - min period limit)
Min period limit: 4.500ns (222.222MHz) ()
Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/CLKA
Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/CLKA
- Location pin: RAMB16_X0Y11.CLKA
+ Location pin: RAMB16_X1Y13.CLKA
Clock network: cmp_gn4124_core/clk_p
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_p2l_clkn = PERIOD TIMEGRP "p2l_clkn_grp" 5 ns HIGH 50%;
- 29951 paths analyzed, 8744 endpoints analyzed, 65 failing endpoints
- 65 timing errors detected. (65 setup errors, 0 hold errors, 0 component switching limit errors)
- Minimum period is 5.673ns.
+ 29928 paths analyzed, 8742 endpoints analyzed, 98 failing endpoints
+ 98 timing errors detected. (98 setup errors, 0 hold errors, 0 component switching limit errors)
+ Minimum period is 5.647ns.
--------------------------------------------------------------------------------
-Paths for end point cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_3 (SLICE_X61Y34.CE), 32 paths
+Paths for end point cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_13 (SLICE_X14Y51.CE), 32 paths
--------------------------------------------------------------------------------
-Slack (setup path): -0.673ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_29 (FF)
- Destination: cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_3 (FF)
+Slack (setup path): -0.647ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_27 (FF)
+ Destination: cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_13 (FF)
Requirement: 5.000ns
- Data Path Delay: 5.641ns (Levels of Logic = 4)
- Clock Path Skew: -0.032ns (0.452 - 0.484)
+ Data Path Delay: 5.539ns (Levels of Logic = 4)
+ Clock Path Skew: -0.108ns (0.434 - 0.542)
Source Clock: cmp_gn4124_core/clk_p rising at 0.000ns
Destination Clock: cmp_gn4124_core/clk_p rising at 5.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path: cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_29 to cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_3
+ Maximum Data Path: cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_27 to cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_13
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X63Y55.YQ Tcko 0.524 cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt<28>
- cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_29
- SLICE_X62Y45.F2 net (fanout=2) 1.029 cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt<29>
- SLICE_X62Y45.X Tilo 0.601 cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_28_BRB2
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and000015
- SLICE_X62Y47.F3 net (fanout=1) 0.236 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and000015
- SLICE_X62Y47.X Tilo 0.601 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000130
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000130
- SLICE_X60Y34.G4 net (fanout=2) 0.595 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000130
- SLICE_X60Y34.Y Tilo 0.616 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr
+ SLICE_X18Y62.YQ Tcko 0.596 cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt<26>
+ cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_27
+ SLICE_X17Y55.F2 net (fanout=2) 0.982 cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt<27>
+ SLICE_X17Y55.X Tilo 0.562 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<22>
+ cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000165
+ SLICE_X16Y54.F4 net (fanout=1) 0.035 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000165
+ SLICE_X16Y54.X Tilo 0.601 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<14>
+ cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000175
+ SLICE_X15Y53.G4 net (fanout=2) 0.328 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000175
+ SLICE_X15Y53.Y Tilo 0.561 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr
cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000198
- SLICE_X60Y34.F4 net (fanout=1) 0.035 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr_and0000
- SLICE_X60Y34.X Tilo 0.601 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr
+ SLICE_X15Y53.F4 net (fanout=1) 0.022 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr_and0000
+ SLICE_X15Y53.X Tilo 0.562 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr
cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and00002
- SLICE_X61Y34.CE net (fanout=15) 0.648 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000
- SLICE_X61Y34.CLK Tceck 0.155 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<3>
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_3
+ SLICE_X14Y51.CE net (fanout=16) 1.135 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000
+ SLICE_X14Y51.CLK Tceck 0.155 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<13>
+ cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_13
------------------------------------------------- ---------------------------
- Total 5.641ns (3.098ns logic, 2.543ns route)
- (54.9% logic, 45.1% route)
+ Total 5.539ns (3.037ns logic, 2.502ns route)
+ (54.8% logic, 45.2% route)
--------------------------------------------------------------------------------
-Slack (setup path): -0.596ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_5 (FF)
- Destination: cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_3 (FF)
+Slack (setup path): -0.645ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_15 (FF)
+ Destination: cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_13 (FF)
Requirement: 5.000ns
- Data Path Delay: 5.481ns (Levels of Logic = 4)
- Clock Path Skew: -0.115ns (0.229 - 0.344)
+ Data Path Delay: 5.584ns (Levels of Logic = 4)
+ Clock Path Skew: -0.061ns (0.434 - 0.495)
Source Clock: cmp_gn4124_core/clk_p rising at 0.000ns
Destination Clock: cmp_gn4124_core/clk_p rising at 5.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path: cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_5 to cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_3
+ Maximum Data Path: cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_15 to cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_13
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X63Y43.YQ Tcko 0.524 cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt<4>
- cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_5
- SLICE_X62Y48.G1 net (fanout=2) 0.863 cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt<5>
- SLICE_X62Y48.Y Tilo 0.616 cmp_gn4124_core/cmp_dma_controller/dma_ctrl_carrier_addr_o<14>
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000165
- SLICE_X62Y49.F4 net (fanout=1) 0.035 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000165
- SLICE_X62Y49.X Tilo 0.601 cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_31_BRB2
+ SLICE_X18Y56.YQ Tcko 0.596 cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt<14>
+ cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_15
+ SLICE_X16Y54.G2 net (fanout=2) 0.635 cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt<15>
+ SLICE_X16Y54.Y Tilo 0.616 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<14>
+ cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000143
+ SLICE_X16Y54.F1 net (fanout=1) 0.373 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000143/O
+ SLICE_X16Y54.X Tilo 0.601 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<14>
cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000175
- SLICE_X60Y34.G3 net (fanout=2) 0.787 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000175
- SLICE_X60Y34.Y Tilo 0.616 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr
+ SLICE_X15Y53.G4 net (fanout=2) 0.328 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000175
+ SLICE_X15Y53.Y Tilo 0.561 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr
cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000198
- SLICE_X60Y34.F4 net (fanout=1) 0.035 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr_and0000
- SLICE_X60Y34.X Tilo 0.601 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr
+ SLICE_X15Y53.F4 net (fanout=1) 0.022 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr_and0000
+ SLICE_X15Y53.X Tilo 0.562 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr
cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and00002
- SLICE_X61Y34.CE net (fanout=15) 0.648 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000
- SLICE_X61Y34.CLK Tceck 0.155 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<3>
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_3
+ SLICE_X14Y51.CE net (fanout=16) 1.135 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000
+ SLICE_X14Y51.CLK Tceck 0.155 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<13>
+ cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_13
------------------------------------------------- ---------------------------
- Total 5.481ns (3.113ns logic, 2.368ns route)
- (56.8% logic, 43.2% route)
+ Total 5.584ns (3.091ns logic, 2.493ns route)
+ (55.4% logic, 44.6% route)
--------------------------------------------------------------------------------
-Slack (setup path): -0.492ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_4 (FF)
- Destination: cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_3 (FF)
+Slack (setup path): -0.643ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_29 (FF)
+ Destination: cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_13 (FF)
Requirement: 5.000ns
- Data Path Delay: 5.377ns (Levels of Logic = 4)
- Clock Path Skew: -0.115ns (0.229 - 0.344)
+ Data Path Delay: 5.535ns (Levels of Logic = 4)
+ Clock Path Skew: -0.108ns (0.434 - 0.542)
Source Clock: cmp_gn4124_core/clk_p rising at 0.000ns
Destination Clock: cmp_gn4124_core/clk_p rising at 5.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path: cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_4 to cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_3
+ Maximum Data Path: cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_29 to cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_13
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X63Y43.XQ Tcko 0.495 cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt<4>
- cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_4
- SLICE_X62Y48.G2 net (fanout=2) 0.788 cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt<4>
- SLICE_X62Y48.Y Tilo 0.616 cmp_gn4124_core/cmp_dma_controller/dma_ctrl_carrier_addr_o<14>
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000165
- SLICE_X62Y49.F4 net (fanout=1) 0.035 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000165
- SLICE_X62Y49.X Tilo 0.601 cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_31_BRB2
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000175
- SLICE_X60Y34.G3 net (fanout=2) 0.787 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000175
- SLICE_X60Y34.Y Tilo 0.616 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr
+ SLICE_X18Y63.YQ Tcko 0.596 cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt<28>
+ cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_29
+ SLICE_X17Y52.F4 net (fanout=2) 0.996 cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt<29>
+ SLICE_X17Y52.X Tilo 0.562 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and000015
+ cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and000015
+ SLICE_X17Y53.F2 net (fanout=1) 0.087 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and000015
+ SLICE_X17Y53.X Tilo 0.562 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000130
+ cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000130
+ SLICE_X15Y53.G3 net (fanout=2) 0.297 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000130
+ SLICE_X15Y53.Y Tilo 0.561 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr
cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000198
- SLICE_X60Y34.F4 net (fanout=1) 0.035 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr_and0000
- SLICE_X60Y34.X Tilo 0.601 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr
+ SLICE_X15Y53.F4 net (fanout=1) 0.022 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr_and0000
+ SLICE_X15Y53.X Tilo 0.562 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr
cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and00002
- SLICE_X61Y34.CE net (fanout=15) 0.648 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000
- SLICE_X61Y34.CLK Tceck 0.155 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<3>
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_3
+ SLICE_X14Y51.CE net (fanout=16) 1.135 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000
+ SLICE_X14Y51.CLK Tceck 0.155 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<13>
+ cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_13
------------------------------------------------- ---------------------------
- Total 5.377ns (3.084ns logic, 2.293ns route)
- (57.4% logic, 42.6% route)
+ Total 5.535ns (2.998ns logic, 2.537ns route)
+ (54.2% logic, 45.8% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_16 (SLICE_X61Y34.CE), 32 paths
+Paths for end point cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt_9 (SLICE_X12Y58.G2), 66 paths
--------------------------------------------------------------------------------
-Slack (setup path): -0.673ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_29 (FF)
- Destination: cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_16 (FF)
+Slack (setup path): -0.636ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_29_BRB3 (FF)
+ Destination: cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt_9 (FF)
Requirement: 5.000ns
- Data Path Delay: 5.641ns (Levels of Logic = 4)
- Clock Path Skew: -0.032ns (0.452 - 0.484)
+ Data Path Delay: 5.586ns (Levels of Logic = 4)
+ Clock Path Skew: -0.050ns (0.248 - 0.298)
Source Clock: cmp_gn4124_core/clk_p rising at 0.000ns
Destination Clock: cmp_gn4124_core/clk_p rising at 5.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path: cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_29 to cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_16
+ Maximum Data Path: cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_29_BRB3 to cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt_9
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X63Y55.YQ Tcko 0.524 cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt<28>
- cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_29
- SLICE_X62Y45.F2 net (fanout=2) 1.029 cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt<29>
- SLICE_X62Y45.X Tilo 0.601 cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_28_BRB2
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and000015
- SLICE_X62Y47.F3 net (fanout=1) 0.236 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and000015
- SLICE_X62Y47.X Tilo 0.601 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000130
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000130
- SLICE_X60Y34.G4 net (fanout=2) 0.595 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000130
- SLICE_X60Y34.Y Tilo 0.616 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000198
- SLICE_X60Y34.F4 net (fanout=1) 0.035 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr_and0000
- SLICE_X60Y34.X Tilo 0.601 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and00002
- SLICE_X61Y34.CE net (fanout=15) 0.648 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000
- SLICE_X61Y34.CLK Tceck 0.155 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<3>
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_16
+ SLICE_X8Y50.XQ Tcko 0.521 cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_29_BRB3
+ cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_29_BRB3
+ SLICE_X10Y50.G4 net (fanout=24) 0.576 cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_29_BRB3
+ SLICE_X10Y50.Y Tilo 0.616 U_ila_pro_0/U0/iDATA<247>
+ cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_mux0001<26>11
+ SLICE_X8Y57.G3 net (fanout=4) 0.753 cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<24>
+ SLICE_X8Y57.COUT Topcyg 1.127 cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_cy<7>1
+ cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_lut<7>1
+ cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_cy<7>_0
+ SLICE_X8Y58.CIN net (fanout=1) 0.000 cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_cy<7>1
+ SLICE_X8Y58.XB Tcinxb 0.313 cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_cy<8>
+ cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_cy<8>
+ SLICE_X12Y58.G2 net (fanout=22) 1.009 cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_cy<8>
+ SLICE_X12Y58.CLK Tgck 0.671 cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt<9>
+ cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt_mux0002<1>1
+ cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt_9
------------------------------------------------- ---------------------------
- Total 5.641ns (3.098ns logic, 2.543ns route)
- (54.9% logic, 45.1% route)
+ Total 5.586ns (3.248ns logic, 2.338ns route)
+ (58.1% logic, 41.9% route)
--------------------------------------------------------------------------------
-Slack (setup path): -0.596ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_5 (FF)
- Destination: cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_16 (FF)
+Slack (setup path): -0.592ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_24_BRB2 (FF)
+ Destination: cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt_9 (FF)
Requirement: 5.000ns
- Data Path Delay: 5.481ns (Levels of Logic = 4)
- Clock Path Skew: -0.115ns (0.229 - 0.344)
+ Data Path Delay: 5.580ns (Levels of Logic = 4)
+ Clock Path Skew: -0.012ns (0.248 - 0.260)
Source Clock: cmp_gn4124_core/clk_p rising at 0.000ns
Destination Clock: cmp_gn4124_core/clk_p rising at 5.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path: cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_5 to cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_16
+ Maximum Data Path: cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_24_BRB2 to cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt_9
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X63Y43.YQ Tcko 0.524 cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt<4>
- cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_5
- SLICE_X62Y48.G1 net (fanout=2) 0.863 cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt<5>
- SLICE_X62Y48.Y Tilo 0.616 cmp_gn4124_core/cmp_dma_controller/dma_ctrl_carrier_addr_o<14>
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000165
- SLICE_X62Y49.F4 net (fanout=1) 0.035 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000165
- SLICE_X62Y49.X Tilo 0.601 cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_31_BRB2
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000175
- SLICE_X60Y34.G3 net (fanout=2) 0.787 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000175
- SLICE_X60Y34.Y Tilo 0.616 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000198
- SLICE_X60Y34.F4 net (fanout=1) 0.035 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr_and0000
- SLICE_X60Y34.X Tilo 0.601 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and00002
- SLICE_X61Y34.CE net (fanout=15) 0.648 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000
- SLICE_X61Y34.CLK Tceck 0.155 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<3>
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_16
+ SLICE_X11Y54.YQ Tcko 0.524 cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_23_BRB2
+ cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_24_BRB2
+ SLICE_X10Y50.G2 net (fanout=2) 0.567 cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_24_BRB2
+ SLICE_X10Y50.Y Tilo 0.616 U_ila_pro_0/U0/iDATA<247>
+ cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_mux0001<26>11
+ SLICE_X8Y57.G3 net (fanout=4) 0.753 cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<24>
+ SLICE_X8Y57.COUT Topcyg 1.127 cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_cy<7>1
+ cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_lut<7>1
+ cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_cy<7>_0
+ SLICE_X8Y58.CIN net (fanout=1) 0.000 cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_cy<7>1
+ SLICE_X8Y58.XB Tcinxb 0.313 cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_cy<8>
+ cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_cy<8>
+ SLICE_X12Y58.G2 net (fanout=22) 1.009 cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_cy<8>
+ SLICE_X12Y58.CLK Tgck 0.671 cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt<9>
+ cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt_mux0002<1>1
+ cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt_9
------------------------------------------------- ---------------------------
- Total 5.481ns (3.113ns logic, 2.368ns route)
- (56.8% logic, 43.2% route)
+ Total 5.580ns (3.251ns logic, 2.329ns route)
+ (58.3% logic, 41.7% route)
--------------------------------------------------------------------------------
-Slack (setup path): -0.492ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_4 (FF)
- Destination: cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_16 (FF)
+Slack (setup path): -0.583ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_29_BRB3 (FF)
+ Destination: cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt_9 (FF)
Requirement: 5.000ns
- Data Path Delay: 5.377ns (Levels of Logic = 4)
- Clock Path Skew: -0.115ns (0.229 - 0.344)
+ Data Path Delay: 5.533ns (Levels of Logic = 3)
+ Clock Path Skew: -0.050ns (0.248 - 0.298)
Source Clock: cmp_gn4124_core/clk_p rising at 0.000ns
Destination Clock: cmp_gn4124_core/clk_p rising at 5.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path: cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_4 to cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_16
+ Maximum Data Path: cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_29_BRB3 to cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt_9
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X63Y43.XQ Tcko 0.495 cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt<4>
- cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_4
- SLICE_X62Y48.G2 net (fanout=2) 0.788 cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt<4>
- SLICE_X62Y48.Y Tilo 0.616 cmp_gn4124_core/cmp_dma_controller/dma_ctrl_carrier_addr_o<14>
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000165
- SLICE_X62Y49.F4 net (fanout=1) 0.035 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000165
- SLICE_X62Y49.X Tilo 0.601 cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_31_BRB2
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000175
- SLICE_X60Y34.G3 net (fanout=2) 0.787 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000175
- SLICE_X60Y34.Y Tilo 0.616 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000198
- SLICE_X60Y34.F4 net (fanout=1) 0.035 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr_and0000
- SLICE_X60Y34.X Tilo 0.601 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and00002
- SLICE_X61Y34.CE net (fanout=15) 0.648 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000
- SLICE_X61Y34.CLK Tceck 0.155 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<3>
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_16
+ SLICE_X8Y50.XQ Tcko 0.521 cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_29_BRB3
+ cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_29_BRB3
+ SLICE_X10Y52.G2 net (fanout=24) 0.717 cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_29_BRB3
+ SLICE_X10Y52.Y Tilo 0.616 U_ila_pro_0/U0/iDATA<251>
+ cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_mux0001<30>11
+ SLICE_X8Y58.F4 net (fanout=4) 0.755 cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<28>
+ SLICE_X8Y58.XB Topxb 1.244 cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_cy<8>
+ cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_lut<8>
+ cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_cy<8>
+ SLICE_X12Y58.G2 net (fanout=22) 1.009 cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_cy<8>
+ SLICE_X12Y58.CLK Tgck 0.671 cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt<9>
+ cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt_mux0002<1>1
+ cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt_9
------------------------------------------------- ---------------------------
- Total 5.377ns (3.084ns logic, 2.293ns route)
- (57.4% logic, 42.6% route)
+ Total 5.533ns (3.052ns logic, 2.481ns route)
+ (55.2% logic, 44.8% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_2 (SLICE_X61Y35.CE), 32 paths
+Paths for end point cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt_10 (SLICE_X12Y61.G4), 66 paths
--------------------------------------------------------------------------------
-Slack (setup path): -0.673ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_29 (FF)
- Destination: cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_2 (FF)
+Slack (setup path): -0.632ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_29_BRB3 (FF)
+ Destination: cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt_10 (FF)
Requirement: 5.000ns
- Data Path Delay: 5.641ns (Levels of Logic = 4)
- Clock Path Skew: -0.032ns (0.452 - 0.484)
+ Data Path Delay: 5.608ns (Levels of Logic = 4)
+ Clock Path Skew: -0.024ns (0.274 - 0.298)
Source Clock: cmp_gn4124_core/clk_p rising at 0.000ns
Destination Clock: cmp_gn4124_core/clk_p rising at 5.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path: cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_29 to cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_2
+ Maximum Data Path: cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_29_BRB3 to cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt_10
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X63Y55.YQ Tcko 0.524 cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt<28>
- cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_29
- SLICE_X62Y45.F2 net (fanout=2) 1.029 cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt<29>
- SLICE_X62Y45.X Tilo 0.601 cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_28_BRB2
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and000015
- SLICE_X62Y47.F3 net (fanout=1) 0.236 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and000015
- SLICE_X62Y47.X Tilo 0.601 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000130
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000130
- SLICE_X60Y34.G4 net (fanout=2) 0.595 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000130
- SLICE_X60Y34.Y Tilo 0.616 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000198
- SLICE_X60Y34.F4 net (fanout=1) 0.035 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr_and0000
- SLICE_X60Y34.X Tilo 0.601 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and00002
- SLICE_X61Y35.CE net (fanout=15) 0.648 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000
- SLICE_X61Y35.CLK Tceck 0.155 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<2>
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_2
+ SLICE_X8Y50.XQ Tcko 0.521 cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_29_BRB3
+ cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_29_BRB3
+ SLICE_X10Y50.G4 net (fanout=24) 0.576 cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_29_BRB3
+ SLICE_X10Y50.Y Tilo 0.616 U_ila_pro_0/U0/iDATA<247>
+ cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_mux0001<26>11
+ SLICE_X8Y57.G3 net (fanout=4) 0.753 cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<24>
+ SLICE_X8Y57.COUT Topcyg 1.127 cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_cy<7>1
+ cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_lut<7>1
+ cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_cy<7>_0
+ SLICE_X8Y58.CIN net (fanout=1) 0.000 cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_cy<7>1
+ SLICE_X8Y58.XB Tcinxb 0.313 cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_cy<8>
+ cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_cy<8>
+ SLICE_X12Y61.G4 net (fanout=22) 1.031 cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_cy<8>
+ SLICE_X12Y61.CLK Tgck 0.671 cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt<10>
+ cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt_mux0002<0>1
+ cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt_10
------------------------------------------------- ---------------------------
- Total 5.641ns (3.098ns logic, 2.543ns route)
- (54.9% logic, 45.1% route)
+ Total 5.608ns (3.248ns logic, 2.360ns route)
+ (57.9% logic, 42.1% route)
--------------------------------------------------------------------------------
-Slack (setup path): -0.596ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_5 (FF)
- Destination: cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_2 (FF)
+Slack (setup path): -0.588ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_24_BRB2 (FF)
+ Destination: cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt_10 (FF)
Requirement: 5.000ns
- Data Path Delay: 5.481ns (Levels of Logic = 4)
- Clock Path Skew: -0.115ns (0.229 - 0.344)
+ Data Path Delay: 5.602ns (Levels of Logic = 4)
+ Clock Path Skew: 0.014ns (0.274 - 0.260)
Source Clock: cmp_gn4124_core/clk_p rising at 0.000ns
Destination Clock: cmp_gn4124_core/clk_p rising at 5.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path: cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_5 to cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_2
+ Maximum Data Path: cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_24_BRB2 to cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt_10
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X63Y43.YQ Tcko 0.524 cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt<4>
- cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_5
- SLICE_X62Y48.G1 net (fanout=2) 0.863 cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt<5>
- SLICE_X62Y48.Y Tilo 0.616 cmp_gn4124_core/cmp_dma_controller/dma_ctrl_carrier_addr_o<14>
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000165
- SLICE_X62Y49.F4 net (fanout=1) 0.035 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000165
- SLICE_X62Y49.X Tilo 0.601 cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_31_BRB2
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000175
- SLICE_X60Y34.G3 net (fanout=2) 0.787 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000175
- SLICE_X60Y34.Y Tilo 0.616 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000198
- SLICE_X60Y34.F4 net (fanout=1) 0.035 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr_and0000
- SLICE_X60Y34.X Tilo 0.601 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and00002
- SLICE_X61Y35.CE net (fanout=15) 0.648 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000
- SLICE_X61Y35.CLK Tceck 0.155 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<2>
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_2
+ SLICE_X11Y54.YQ Tcko 0.524 cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_23_BRB2
+ cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_24_BRB2
+ SLICE_X10Y50.G2 net (fanout=2) 0.567 cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_24_BRB2
+ SLICE_X10Y50.Y Tilo 0.616 U_ila_pro_0/U0/iDATA<247>
+ cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_mux0001<26>11
+ SLICE_X8Y57.G3 net (fanout=4) 0.753 cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<24>
+ SLICE_X8Y57.COUT Topcyg 1.127 cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_cy<7>1
+ cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_lut<7>1
+ cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_cy<7>_0
+ SLICE_X8Y58.CIN net (fanout=1) 0.000 cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_cy<7>1
+ SLICE_X8Y58.XB Tcinxb 0.313 cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_cy<8>
+ cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_cy<8>
+ SLICE_X12Y61.G4 net (fanout=22) 1.031 cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_cy<8>
+ SLICE_X12Y61.CLK Tgck 0.671 cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt<10>
+ cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt_mux0002<0>1
+ cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt_10
------------------------------------------------- ---------------------------
- Total 5.481ns (3.113ns logic, 2.368ns route)
- (56.8% logic, 43.2% route)
+ Total 5.602ns (3.251ns logic, 2.351ns route)
+ (58.0% logic, 42.0% route)
--------------------------------------------------------------------------------
-Slack (setup path): -0.492ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_4 (FF)
- Destination: cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_2 (FF)
+Slack (setup path): -0.579ns (requirement - (data path - clock path skew + uncertainty))
+ Source: cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_29_BRB3 (FF)
+ Destination: cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt_10 (FF)
Requirement: 5.000ns
- Data Path Delay: 5.377ns (Levels of Logic = 4)
- Clock Path Skew: -0.115ns (0.229 - 0.344)
+ Data Path Delay: 5.555ns (Levels of Logic = 3)
+ Clock Path Skew: -0.024ns (0.274 - 0.298)
Source Clock: cmp_gn4124_core/clk_p rising at 0.000ns
Destination Clock: cmp_gn4124_core/clk_p rising at 5.000ns
Clock Uncertainty: 0.000ns
- Maximum Data Path: cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_4 to cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_2
+ Maximum Data Path: cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_29_BRB3 to cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt_10
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X63Y43.XQ Tcko 0.495 cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt<4>
- cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt_4
- SLICE_X62Y48.G2 net (fanout=2) 0.788 cmp_gn4124_core/cmp_l2p_dma_master/dma_length_cnt<4>
- SLICE_X62Y48.Y Tilo 0.616 cmp_gn4124_core/cmp_dma_controller/dma_ctrl_carrier_addr_o<14>
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000165
- SLICE_X62Y49.F4 net (fanout=1) 0.035 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000165
- SLICE_X62Y49.X Tilo 0.601 cmp_gn4124_core/cmp_l2p_dma_master/l2p_address_l_31_BRB2
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000175
- SLICE_X60Y34.G3 net (fanout=2) 0.787 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000175
- SLICE_X60Y34.Y Tilo 0.616 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000198
- SLICE_X60Y34.F4 net (fanout=1) 0.035 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr_and0000
- SLICE_X60Y34.X Tilo 0.601 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_wr
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and00002
- SLICE_X61Y35.CE net (fanout=15) 0.648 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_and0000
- SLICE_X61Y35.CLK Tceck 0.155 cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din<2>
- cmp_gn4124_core/cmp_l2p_dma_master/addr_fifo_din_2
+ SLICE_X8Y50.XQ Tcko 0.521 cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_29_BRB3
+ cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_29_BRB3
+ SLICE_X10Y52.G2 net (fanout=24) 0.717 cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_29_BRB3
+ SLICE_X10Y52.Y Tilo 0.616 U_ila_pro_0/U0/iDATA<251>
+ cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt_mux0001<30>11
+ SLICE_X8Y58.F4 net (fanout=4) 0.755 cmp_gn4124_core/cmp_l2p_dma_master/l2p_len_cnt<28>
+ SLICE_X8Y58.XB Topxb 1.244 cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_cy<8>
+ cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_lut<8>
+ cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_cy<8>
+ SLICE_X12Y61.G4 net (fanout=22) 1.031 cmp_gn4124_core/cmp_l2p_dma_master/Mcompar_l2p_dma_current_state_cmp_gt0000_cy<8>
+ SLICE_X12Y61.CLK Tgck 0.671 cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt<10>
+ cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt_mux0002<0>1
+ cmp_gn4124_core/cmp_l2p_dma_master/l2p_data_cnt_10
------------------------------------------------- ---------------------------
- Total 5.377ns (3.084ns logic, 2.293ns route)
- (57.4% logic, 42.6% route)
+ Total 5.555ns (3.052ns logic, 2.503ns route)
+ (54.9% logic, 45.1% route)
--------------------------------------------------------------------------------
Hold Paths: TS_p2l_clkn = PERIOD TIMEGRP "p2l_clkn_grp" 5 ns HIGH 50%;
--------------------------------------------------------------------------------
-Paths for end point cmp_gn4124_core/cmp_p2l_des/p2l_data_o_8 (SLICE_X74Y74.BY), 1 path
+Paths for end point cmp_gn4124_core/cmp_p2l_des/p2l_data_o_5 (SLICE_X73Y84.BY), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.274ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_gn4124_core/cmp_p2l_des/p2l_data_sdr_l_8 (FF)
- Destination: cmp_gn4124_core/cmp_p2l_des/p2l_data_o_8 (FF)
+Slack (hold path): 0.428ns (requirement - (clock path skew + uncertainty - data path))
+ Source: cmp_gn4124_core/cmp_p2l_des/p2l_data_sdr_l_5 (FF)
+ Destination: cmp_gn4124_core/cmp_p2l_des/p2l_data_o_5 (FF)
Requirement: 0.000ns
- Data Path Delay: 0.869ns (Levels of Logic = 0)
- Clock Path Skew: 0.595ns (2.998 - 2.403)
+ Data Path Delay: 0.854ns (Levels of Logic = 0)
+ Clock Path Skew: 0.426ns (2.829 - 2.403)
Source Clock: cmp_gn4124_core/clk_n rising at 5.000ns
Destination Clock: cmp_gn4124_core/clk_p rising at 5.000ns
Clock Uncertainty: 0.000ns
- Minimum Data Path: cmp_gn4124_core/cmp_p2l_des/p2l_data_sdr_l_8 to cmp_gn4124_core/cmp_p2l_des/p2l_data_o_8
+ Minimum Data Path: cmp_gn4124_core/cmp_p2l_des/p2l_data_sdr_l_5 to cmp_gn4124_core/cmp_p2l_des/p2l_data_o_5
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X75Y75.YQ Tcko 0.419 cmp_gn4124_core/cmp_p2l_des/p2l_data_sdr_l<8>
- cmp_gn4124_core/cmp_p2l_des/p2l_data_sdr_l_8
- SLICE_X74Y74.BY net (fanout=1) 0.313 cmp_gn4124_core/cmp_p2l_des/p2l_data_sdr_l<8>
- SLICE_X74Y74.CLK Tckdi (-Th) -0.137 cmp_gn4124_core/cmp_p2l_des/p2l_data_o<8>
- cmp_gn4124_core/cmp_p2l_des/p2l_data_o_8
+ SLICE_X75Y85.YQ Tcko 0.419 cmp_gn4124_core/cmp_p2l_des/p2l_data_sdr_l<5>
+ cmp_gn4124_core/cmp_p2l_des/p2l_data_sdr_l_5
+ SLICE_X73Y84.BY net (fanout=1) 0.313 cmp_gn4124_core/cmp_p2l_des/p2l_data_sdr_l<5>
+ SLICE_X73Y84.CLK Tckdi (-Th) -0.122 cmp_gn4124_core/cmp_p2l_des/p2l_data_o<5>
+ cmp_gn4124_core/cmp_p2l_des/p2l_data_o_5
------------------------------------------------- ---------------------------
- Total 0.869ns (0.556ns logic, 0.313ns route)
- (64.0% logic, 36.0% route)
+ Total 0.854ns (0.541ns logic, 0.313ns route)
+ (63.3% logic, 36.7% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_gn4124_core/cmp_l2p_ser/DDROUT[10].U/FDDRRSE1/ODDR2/FF0 (R19.O1), 1 path
+Paths for end point cmp_gn4124_core/cmp_p2l_des/p2l_data_o_6 (SLICE_X75Y78.BX), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.276ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_gn4124_core/cmp_l2p_ser/data_d_10 (FF)
- Destination: cmp_gn4124_core/cmp_l2p_ser/DDROUT[10].U/FDDRRSE1/ODDR2/FF0 (FF)
+Slack (hold path): 0.436ns (requirement - (clock path skew + uncertainty - data path))
+ Source: cmp_gn4124_core/cmp_p2l_des/p2l_data_sdr_l_6 (FF)
+ Destination: cmp_gn4124_core/cmp_p2l_des/p2l_data_o_6 (FF)
Requirement: 0.000ns
- Data Path Delay: 0.691ns (Levels of Logic = 0)
- Clock Path Skew: 0.415ns (2.862 - 2.447)
- Source Clock: cmp_gn4124_core/clk_p rising at 5.000ns
- Destination Clock: cmp_gn4124_core/clk_n rising at 5.000ns
+ Data Path Delay: 0.911ns (Levels of Logic = 0)
+ Clock Path Skew: 0.475ns (2.893 - 2.418)
+ Source Clock: cmp_gn4124_core/clk_n rising at 5.000ns
+ Destination Clock: cmp_gn4124_core/clk_p rising at 5.000ns
Clock Uncertainty: 0.000ns
- Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/data_d_10 to cmp_gn4124_core/cmp_l2p_ser/DDROUT[10].U/FDDRRSE1/ODDR2/FF0
+ Minimum Data Path: cmp_gn4124_core/cmp_p2l_des/p2l_data_sdr_l_6 to cmp_gn4124_core/cmp_p2l_des/p2l_data_o_6
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X78Y57.YQ Tcko 0.477 cmp_gn4124_core/cmp_l2p_ser/data_d<10>
- cmp_gn4124_core/cmp_l2p_ser/data_d_10
- R19.O1 net (fanout=1) 0.253 cmp_gn4124_core/cmp_l2p_ser/data_d<10>
- R19.OTCLK1 Tiocko (-Th) 0.039 L2P_DATA<10>
- cmp_gn4124_core/cmp_l2p_ser/DDROUT[10].U/FDDRRSE1/ODDR2/FF0
+ SLICE_X74Y79.YQ Tcko 0.477 cmp_gn4124_core/cmp_p2l_des/p2l_data_sdr_l<6>
+ cmp_gn4124_core/cmp_p2l_des/p2l_data_sdr_l_6
+ SLICE_X75Y78.BX net (fanout=1) 0.372 cmp_gn4124_core/cmp_p2l_des/p2l_data_sdr_l<6>
+ SLICE_X75Y78.CLK Tckdi (-Th) -0.062 cmp_gn4124_core/cmp_p2l_des/p2l_data_o<6>
+ cmp_gn4124_core/cmp_p2l_des/p2l_data_o_6
------------------------------------------------- ---------------------------
- Total 0.691ns (0.438ns logic, 0.253ns route)
- (63.4% logic, 36.6% route)
+ Total 0.911ns (0.539ns logic, 0.372ns route)
+ (59.2% logic, 40.8% route)
--------------------------------------------------------------------------------
-Paths for end point cmp_gn4124_core/cmp_l2p_ser/DDROUT[15].U/FDDRRSE1/ODDR2/FF0 (N19.O1), 1 path
+Paths for end point cmp_gn4124_core/cmp_p2l_des/p2l_data_o_9 (SLICE_X75Y78.BY), 1 path
--------------------------------------------------------------------------------
-Slack (hold path): 0.294ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_gn4124_core/cmp_l2p_ser/data_d_15 (FF)
- Destination: cmp_gn4124_core/cmp_l2p_ser/DDROUT[15].U/FDDRRSE1/ODDR2/FF0 (FF)
+Slack (hold path): 0.437ns (requirement - (clock path skew + uncertainty - data path))
+ Source: cmp_gn4124_core/cmp_p2l_des/p2l_data_sdr_l_9 (FF)
+ Destination: cmp_gn4124_core/cmp_p2l_des/p2l_data_o_9 (FF)
Requirement: 0.000ns
- Data Path Delay: 0.691ns (Levels of Logic = 0)
- Clock Path Skew: 0.397ns (2.869 - 2.472)
- Source Clock: cmp_gn4124_core/clk_p rising at 5.000ns
- Destination Clock: cmp_gn4124_core/clk_n rising at 5.000ns
+ Data Path Delay: 0.912ns (Levels of Logic = 0)
+ Clock Path Skew: 0.475ns (2.893 - 2.418)
+ Source Clock: cmp_gn4124_core/clk_n rising at 5.000ns
+ Destination Clock: cmp_gn4124_core/clk_p rising at 5.000ns
Clock Uncertainty: 0.000ns
- Minimum Data Path: cmp_gn4124_core/cmp_l2p_ser/data_d_15 to cmp_gn4124_core/cmp_l2p_ser/DDROUT[15].U/FDDRRSE1/ODDR2/FF0
+ Minimum Data Path: cmp_gn4124_core/cmp_p2l_des/p2l_data_sdr_l_9 to cmp_gn4124_core/cmp_p2l_des/p2l_data_o_9
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
- SLICE_X78Y58.YQ Tcko 0.477 cmp_gn4124_core/cmp_l2p_ser/data_d<15>
- cmp_gn4124_core/cmp_l2p_ser/data_d_15
- N19.O1 net (fanout=1) 0.253 cmp_gn4124_core/cmp_l2p_ser/data_d<15>
- N19.OTCLK1 Tiocko (-Th) 0.039 L2P_DATA<15>
- cmp_gn4124_core/cmp_l2p_ser/DDROUT[15].U/FDDRRSE1/ODDR2/FF0
+ SLICE_X74Y78.YQ Tcko 0.477 cmp_gn4124_core/cmp_p2l_des/p2l_data_sdr_l<9>
+ cmp_gn4124_core/cmp_p2l_des/p2l_data_sdr_l_9
+ SLICE_X75Y78.BY net (fanout=1) 0.313 cmp_gn4124_core/cmp_p2l_des/p2l_data_sdr_l<9>
+ SLICE_X75Y78.CLK Tckdi (-Th) -0.122 cmp_gn4124_core/cmp_p2l_des/p2l_data_o<6>
+ cmp_gn4124_core/cmp_p2l_des/p2l_data_o_9
------------------------------------------------- ---------------------------
- Total 0.691ns (0.438ns logic, 0.253ns route)
- (63.4% logic, 36.6% route)
+ Total 0.912ns (0.599ns logic, 0.313ns route)
+ (65.7% logic, 34.3% route)
--------------------------------------------------------------------------------
@@ -2008,7 +2033,7 @@ Slack: 0.500ns (period - min period limit)
Min period limit: 4.500ns (222.222MHz) ()
Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/CLKB
Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/CLKB
- Location pin: RAMB16_X1Y5.CLKB
+ Location pin: RAMB16_X0Y10.CLKB
Clock network: cmp_gn4124_core/clk_p
--------------------------------------------------------------------------------
Slack: 0.500ns (period - min period limit)
@@ -2016,7 +2041,7 @@ Slack: 0.500ns (period - min period limit)
Min period limit: 4.500ns (222.222MHz) ()
Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_noinit.ram/dpram.dp36x36.ram/CLKA
Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/s3_noinit.ram/dpram.dp36x36.ram/CLKA
- Location pin: RAMB16_X0Y13.CLKA
+ Location pin: RAMB16_X1Y12.CLKA
Clock network: cmp_gn4124_core/clk_p
--------------------------------------------------------------------------------
Slack: 0.500ns (period - min period limit)
@@ -2024,7 +2049,7 @@ Slack: 0.500ns (period - min period limit)
Min period limit: 4.500ns (222.222MHz) ()
Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/CLKA
Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/dpram.dp36x36.ram/CLKA
- Location pin: RAMB16_X0Y11.CLKA
+ Location pin: RAMB16_X1Y13.CLKA
Clock network: cmp_gn4124_core/clk_p
--------------------------------------------------------------------------------
@@ -2063,7 +2088,7 @@ Slack (slowest paths): 0.237ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- Y21.OTCLK2 net (fanout=2540) 1.022 cmp_gn4124_core/clk_p
+ Y21.OTCLK2 net (fanout=2661) 1.022 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.917ns (1.873ns logic, 1.044ns route)
(64.2% logic, 35.8% route)
@@ -2149,7 +2174,7 @@ Delay (fastest paths): 5.247ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- Y21.OTCLK2 net (fanout=2540) 0.869 cmp_gn4124_core/clk_p
+ Y21.OTCLK2 net (fanout=2661) 0.869 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.474ns (1.588ns logic, 0.886ns route)
(64.2% logic, 35.8% route)
@@ -2238,7 +2263,7 @@ Slack (slowest paths): 0.237ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- AA22.OTCLK2 net (fanout=2540) 1.022 cmp_gn4124_core/clk_p
+ AA22.OTCLK2 net (fanout=2661) 1.022 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.917ns (1.873ns logic, 1.044ns route)
(64.2% logic, 35.8% route)
@@ -2324,7 +2349,7 @@ Delay (fastest paths): 5.246ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- AA22.OTCLK2 net (fanout=2540) 0.869 cmp_gn4124_core/clk_p
+ AA22.OTCLK2 net (fanout=2661) 0.869 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.473ns (1.587ns logic, 0.886ns route)
(64.2% logic, 35.8% route)
@@ -2416,7 +2441,7 @@ Slack (slowest paths): 0.330ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- V22.OTCLK2 net (fanout=2540) 1.018 cmp_gn4124_core/clk_p
+ V22.OTCLK2 net (fanout=2661) 1.018 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.913ns (1.873ns logic, 1.040ns route)
(64.3% logic, 35.7% route)
@@ -2502,7 +2527,7 @@ Delay (fastest paths): 5.154ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- V22.OTCLK2 net (fanout=2540) 0.866 cmp_gn4124_core/clk_p
+ V22.OTCLK2 net (fanout=2661) 0.866 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.470ns (1.587ns logic, 0.883ns route)
(64.3% logic, 35.7% route)
@@ -2597,7 +2622,7 @@ Slack (slowest paths): 0.330ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- V22.OTCLK2 net (fanout=2540) 1.018 cmp_gn4124_core/clk_p
+ V22.OTCLK2 net (fanout=2661) 1.018 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.913ns (1.873ns logic, 1.040ns route)
(64.3% logic, 35.7% route)
@@ -2683,7 +2708,7 @@ Delay (fastest paths): 5.155ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- V22.OTCLK2 net (fanout=2540) 0.866 cmp_gn4124_core/clk_p
+ V22.OTCLK2 net (fanout=2661) 0.866 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.471ns (1.588ns logic, 0.883ns route)
(64.3% logic, 35.7% route)
@@ -2772,7 +2797,7 @@ Slack (slowest paths): 0.375ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- R19.OTCLK2 net (fanout=2540) 0.973 cmp_gn4124_core/clk_p
+ R19.OTCLK2 net (fanout=2661) 0.973 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.868ns (1.873ns logic, 0.995ns route)
(65.3% logic, 34.7% route)
@@ -2858,7 +2883,7 @@ Delay (fastest paths): 5.115ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- R19.OTCLK2 net (fanout=2540) 0.827 cmp_gn4124_core/clk_p
+ R19.OTCLK2 net (fanout=2661) 0.827 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.431ns (1.587ns logic, 0.844ns route)
(65.3% logic, 34.7% route)
@@ -2953,7 +2978,7 @@ Slack (slowest paths): 0.375ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- R19.OTCLK2 net (fanout=2540) 0.973 cmp_gn4124_core/clk_p
+ R19.OTCLK2 net (fanout=2661) 0.973 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.868ns (1.873ns logic, 0.995ns route)
(65.3% logic, 34.7% route)
@@ -3039,7 +3064,7 @@ Delay (fastest paths): 5.116ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- R19.OTCLK2 net (fanout=2540) 0.827 cmp_gn4124_core/clk_p
+ R19.OTCLK2 net (fanout=2661) 0.827 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.432ns (1.588ns logic, 0.844ns route)
(65.3% logic, 34.7% route)
@@ -3128,7 +3153,7 @@ Slack (slowest paths): 0.336ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- N18.OTCLK2 net (fanout=2540) 1.012 cmp_gn4124_core/clk_p
+ N18.OTCLK2 net (fanout=2661) 1.012 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.907ns (1.873ns logic, 1.034ns route)
(64.4% logic, 35.6% route)
@@ -3214,7 +3239,7 @@ Delay (fastest paths): 5.148ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- N18.OTCLK2 net (fanout=2540) 0.860 cmp_gn4124_core/clk_p
+ N18.OTCLK2 net (fanout=2661) 0.860 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.464ns (1.587ns logic, 0.877ns route)
(64.4% logic, 35.6% route)
@@ -3309,7 +3334,7 @@ Slack (slowest paths): 0.336ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- N18.OTCLK2 net (fanout=2540) 1.012 cmp_gn4124_core/clk_p
+ N18.OTCLK2 net (fanout=2661) 1.012 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.907ns (1.873ns logic, 1.034ns route)
(64.4% logic, 35.6% route)
@@ -3395,7 +3420,7 @@ Delay (fastest paths): 5.149ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- N18.OTCLK2 net (fanout=2540) 0.860 cmp_gn4124_core/clk_p
+ N18.OTCLK2 net (fanout=2661) 0.860 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.465ns (1.588ns logic, 0.877ns route)
(64.4% logic, 35.6% route)
@@ -3484,7 +3509,7 @@ Slack (slowest paths): 0.313ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- U19.OTCLK2 net (fanout=2540) 1.035 cmp_gn4124_core/clk_p
+ U19.OTCLK2 net (fanout=2661) 1.035 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.930ns (1.873ns logic, 1.057ns route)
(63.9% logic, 36.1% route)
@@ -3570,7 +3595,7 @@ Delay (fastest paths): 5.168ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- U19.OTCLK2 net (fanout=2540) 0.880 cmp_gn4124_core/clk_p
+ U19.OTCLK2 net (fanout=2661) 0.880 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.484ns (1.587ns logic, 0.897ns route)
(63.9% logic, 36.1% route)
@@ -3665,7 +3690,7 @@ Slack (slowest paths): 0.313ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- U19.OTCLK2 net (fanout=2540) 1.035 cmp_gn4124_core/clk_p
+ U19.OTCLK2 net (fanout=2661) 1.035 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.930ns (1.873ns logic, 1.057ns route)
(63.9% logic, 36.1% route)
@@ -3751,7 +3776,7 @@ Delay (fastest paths): 5.169ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- U19.OTCLK2 net (fanout=2540) 0.880 cmp_gn4124_core/clk_p
+ U19.OTCLK2 net (fanout=2661) 0.880 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.485ns (1.588ns logic, 0.897ns route)
(63.9% logic, 36.1% route)
@@ -3840,7 +3865,7 @@ Slack (slowest paths): 0.317ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- U21.OTCLK2 net (fanout=2540) 1.031 cmp_gn4124_core/clk_p
+ U21.OTCLK2 net (fanout=2661) 1.031 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.926ns (1.873ns logic, 1.053ns route)
(64.0% logic, 36.0% route)
@@ -3926,7 +3951,7 @@ Delay (fastest paths): 5.165ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- U21.OTCLK2 net (fanout=2540) 0.877 cmp_gn4124_core/clk_p
+ U21.OTCLK2 net (fanout=2661) 0.877 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.481ns (1.587ns logic, 0.894ns route)
(64.0% logic, 36.0% route)
@@ -4021,7 +4046,7 @@ Slack (slowest paths): 0.317ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- U21.OTCLK2 net (fanout=2540) 1.031 cmp_gn4124_core/clk_p
+ U21.OTCLK2 net (fanout=2661) 1.031 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.926ns (1.873ns logic, 1.053ns route)
(64.0% logic, 36.0% route)
@@ -4107,7 +4132,7 @@ Delay (fastest paths): 5.166ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- U21.OTCLK2 net (fanout=2540) 0.877 cmp_gn4124_core/clk_p
+ U21.OTCLK2 net (fanout=2661) 0.877 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.482ns (1.588ns logic, 0.894ns route)
(64.0% logic, 36.0% route)
@@ -4196,7 +4221,7 @@ Slack (slowest paths): 0.313ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- U20.OTCLK2 net (fanout=2540) 1.035 cmp_gn4124_core/clk_p
+ U20.OTCLK2 net (fanout=2661) 1.035 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.930ns (1.873ns logic, 1.057ns route)
(63.9% logic, 36.1% route)
@@ -4282,7 +4307,7 @@ Delay (fastest paths): 5.168ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- U20.OTCLK2 net (fanout=2540) 0.880 cmp_gn4124_core/clk_p
+ U20.OTCLK2 net (fanout=2661) 0.880 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.484ns (1.587ns logic, 0.897ns route)
(63.9% logic, 36.1% route)
@@ -4377,7 +4402,7 @@ Slack (slowest paths): 0.313ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- U20.OTCLK2 net (fanout=2540) 1.035 cmp_gn4124_core/clk_p
+ U20.OTCLK2 net (fanout=2661) 1.035 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.930ns (1.873ns logic, 1.057ns route)
(63.9% logic, 36.1% route)
@@ -4463,7 +4488,7 @@ Delay (fastest paths): 5.169ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- U20.OTCLK2 net (fanout=2540) 0.880 cmp_gn4124_core/clk_p
+ U20.OTCLK2 net (fanout=2661) 0.880 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.485ns (1.588ns logic, 0.897ns route)
(63.9% logic, 36.1% route)
@@ -4552,7 +4577,7 @@ Slack (slowest paths): 0.358ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- N19.OTCLK2 net (fanout=2540) 0.990 cmp_gn4124_core/clk_p
+ N19.OTCLK2 net (fanout=2661) 0.990 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.885ns (1.873ns logic, 1.012ns route)
(64.9% logic, 35.1% route)
@@ -4638,7 +4663,7 @@ Delay (fastest paths): 5.130ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- N19.OTCLK2 net (fanout=2540) 0.842 cmp_gn4124_core/clk_p
+ N19.OTCLK2 net (fanout=2661) 0.842 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.446ns (1.587ns logic, 0.859ns route)
(64.9% logic, 35.1% route)
@@ -4733,7 +4758,7 @@ Slack (slowest paths): 0.358ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- N19.OTCLK2 net (fanout=2540) 0.990 cmp_gn4124_core/clk_p
+ N19.OTCLK2 net (fanout=2661) 0.990 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.885ns (1.873ns logic, 1.012ns route)
(64.9% logic, 35.1% route)
@@ -4819,7 +4844,7 @@ Delay (fastest paths): 5.131ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- N19.OTCLK2 net (fanout=2540) 0.842 cmp_gn4124_core/clk_p
+ N19.OTCLK2 net (fanout=2661) 0.842 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.447ns (1.588ns logic, 0.859ns route)
(64.9% logic, 35.1% route)
@@ -4908,7 +4933,7 @@ Slack (slowest paths): 0.330ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- W22.OTCLK2 net (fanout=2540) 1.018 cmp_gn4124_core/clk_p
+ W22.OTCLK2 net (fanout=2661) 1.018 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.913ns (1.873ns logic, 1.040ns route)
(64.3% logic, 35.7% route)
@@ -4994,7 +5019,7 @@ Delay (fastest paths): 5.154ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- W22.OTCLK2 net (fanout=2540) 0.866 cmp_gn4124_core/clk_p
+ W22.OTCLK2 net (fanout=2661) 0.866 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.470ns (1.587ns logic, 0.883ns route)
(64.3% logic, 35.7% route)
@@ -5089,7 +5114,7 @@ Slack (slowest paths): 0.330ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- W22.OTCLK2 net (fanout=2540) 1.018 cmp_gn4124_core/clk_p
+ W22.OTCLK2 net (fanout=2661) 1.018 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.913ns (1.873ns logic, 1.040ns route)
(64.3% logic, 35.7% route)
@@ -5175,7 +5200,7 @@ Delay (fastest paths): 5.155ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- W22.OTCLK2 net (fanout=2540) 0.866 cmp_gn4124_core/clk_p
+ W22.OTCLK2 net (fanout=2661) 0.866 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.471ns (1.588ns logic, 0.883ns route)
(64.3% logic, 35.7% route)
@@ -5264,7 +5289,7 @@ Slack (slowest paths): 0.341ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- V20.OTCLK2 net (fanout=2540) 1.007 cmp_gn4124_core/clk_p
+ V20.OTCLK2 net (fanout=2661) 1.007 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.902ns (1.873ns logic, 1.029ns route)
(64.5% logic, 35.5% route)
@@ -5350,7 +5375,7 @@ Delay (fastest paths): 5.144ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- V20.OTCLK2 net (fanout=2540) 0.856 cmp_gn4124_core/clk_p
+ V20.OTCLK2 net (fanout=2661) 0.856 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.460ns (1.587ns logic, 0.873ns route)
(64.5% logic, 35.5% route)
@@ -5445,7 +5470,7 @@ Slack (slowest paths): 0.341ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- V20.OTCLK2 net (fanout=2540) 1.007 cmp_gn4124_core/clk_p
+ V20.OTCLK2 net (fanout=2661) 1.007 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.902ns (1.873ns logic, 1.029ns route)
(64.5% logic, 35.5% route)
@@ -5531,7 +5556,7 @@ Delay (fastest paths): 5.145ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- V20.OTCLK2 net (fanout=2540) 0.856 cmp_gn4124_core/clk_p
+ V20.OTCLK2 net (fanout=2661) 0.856 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.461ns (1.588ns logic, 0.873ns route)
(64.5% logic, 35.5% route)
@@ -5620,7 +5645,7 @@ Slack (slowest paths): 0.341ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- V19.OTCLK2 net (fanout=2540) 1.007 cmp_gn4124_core/clk_p
+ V19.OTCLK2 net (fanout=2661) 1.007 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.902ns (1.873ns logic, 1.029ns route)
(64.5% logic, 35.5% route)
@@ -5706,7 +5731,7 @@ Delay (fastest paths): 5.144ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- V19.OTCLK2 net (fanout=2540) 0.856 cmp_gn4124_core/clk_p
+ V19.OTCLK2 net (fanout=2661) 0.856 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.460ns (1.587ns logic, 0.873ns route)
(64.5% logic, 35.5% route)
@@ -5801,7 +5826,7 @@ Slack (slowest paths): 0.341ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- V19.OTCLK2 net (fanout=2540) 1.007 cmp_gn4124_core/clk_p
+ V19.OTCLK2 net (fanout=2661) 1.007 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.902ns (1.873ns logic, 1.029ns route)
(64.5% logic, 35.5% route)
@@ -5887,7 +5912,7 @@ Delay (fastest paths): 5.145ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- V19.OTCLK2 net (fanout=2540) 0.856 cmp_gn4124_core/clk_p
+ V19.OTCLK2 net (fanout=2661) 0.856 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.461ns (1.588ns logic, 0.873ns route)
(64.5% logic, 35.5% route)
@@ -5976,7 +6001,7 @@ Slack (slowest paths): 0.352ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- W21.OTCLK2 net (fanout=2540) 0.996 cmp_gn4124_core/clk_p
+ W21.OTCLK2 net (fanout=2661) 0.996 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.891ns (1.873ns logic, 1.018ns route)
(64.8% logic, 35.2% route)
@@ -6062,7 +6087,7 @@ Delay (fastest paths): 5.135ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- W21.OTCLK2 net (fanout=2540) 0.847 cmp_gn4124_core/clk_p
+ W21.OTCLK2 net (fanout=2661) 0.847 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.451ns (1.587ns logic, 0.864ns route)
(64.7% logic, 35.3% route)
@@ -6157,7 +6182,7 @@ Slack (slowest paths): 0.352ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- W21.OTCLK2 net (fanout=2540) 0.996 cmp_gn4124_core/clk_p
+ W21.OTCLK2 net (fanout=2661) 0.996 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.891ns (1.873ns logic, 1.018ns route)
(64.8% logic, 35.2% route)
@@ -6243,7 +6268,7 @@ Delay (fastest paths): 5.136ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- W21.OTCLK2 net (fanout=2540) 0.847 cmp_gn4124_core/clk_p
+ W21.OTCLK2 net (fanout=2661) 0.847 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.452ns (1.588ns logic, 0.864ns route)
(64.8% logic, 35.2% route)
@@ -6332,7 +6357,7 @@ Slack (slowest paths): 0.352ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- Y22.OTCLK2 net (fanout=2540) 0.996 cmp_gn4124_core/clk_p
+ Y22.OTCLK2 net (fanout=2661) 0.996 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.891ns (1.873ns logic, 1.018ns route)
(64.8% logic, 35.2% route)
@@ -6418,7 +6443,7 @@ Delay (fastest paths): 5.135ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- Y22.OTCLK2 net (fanout=2540) 0.847 cmp_gn4124_core/clk_p
+ Y22.OTCLK2 net (fanout=2661) 0.847 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.451ns (1.587ns logic, 0.864ns route)
(64.7% logic, 35.3% route)
@@ -6513,7 +6538,7 @@ Slack (slowest paths): 0.352ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- Y22.OTCLK2 net (fanout=2540) 0.996 cmp_gn4124_core/clk_p
+ Y22.OTCLK2 net (fanout=2661) 0.996 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.891ns (1.873ns logic, 1.018ns route)
(64.8% logic, 35.2% route)
@@ -6599,7 +6624,7 @@ Delay (fastest paths): 5.136ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- Y22.OTCLK2 net (fanout=2540) 0.847 cmp_gn4124_core/clk_p
+ Y22.OTCLK2 net (fanout=2661) 0.847 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.452ns (1.588ns logic, 0.864ns route)
(64.8% logic, 35.2% route)
@@ -6688,7 +6713,7 @@ Slack (slowest paths): 0.337ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- T18.OTCLK2 net (fanout=2540) 1.011 cmp_gn4124_core/clk_p
+ T18.OTCLK2 net (fanout=2661) 1.011 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.906ns (1.873ns logic, 1.033ns route)
(64.5% logic, 35.5% route)
@@ -6774,7 +6799,7 @@ Delay (fastest paths): 5.147ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- T18.OTCLK2 net (fanout=2540) 0.859 cmp_gn4124_core/clk_p
+ T18.OTCLK2 net (fanout=2661) 0.859 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.463ns (1.587ns logic, 0.876ns route)
(64.4% logic, 35.6% route)
@@ -6869,7 +6894,7 @@ Slack (slowest paths): 0.337ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- T18.OTCLK2 net (fanout=2540) 1.011 cmp_gn4124_core/clk_p
+ T18.OTCLK2 net (fanout=2661) 1.011 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.906ns (1.873ns logic, 1.033ns route)
(64.5% logic, 35.5% route)
@@ -6955,7 +6980,7 @@ Delay (fastest paths): 5.148ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- T18.OTCLK2 net (fanout=2540) 0.859 cmp_gn4124_core/clk_p
+ T18.OTCLK2 net (fanout=2661) 0.859 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.464ns (1.588ns logic, 0.876ns route)
(64.4% logic, 35.6% route)
@@ -7044,7 +7069,7 @@ Slack (slowest paths): 0.337ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- T17.OTCLK2 net (fanout=2540) 1.011 cmp_gn4124_core/clk_p
+ T17.OTCLK2 net (fanout=2661) 1.011 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.906ns (1.873ns logic, 1.033ns route)
(64.5% logic, 35.5% route)
@@ -7130,7 +7155,7 @@ Delay (fastest paths): 5.147ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- T17.OTCLK2 net (fanout=2540) 0.859 cmp_gn4124_core/clk_p
+ T17.OTCLK2 net (fanout=2661) 0.859 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.463ns (1.587ns logic, 0.876ns route)
(64.4% logic, 35.6% route)
@@ -7225,7 +7250,7 @@ Slack (slowest paths): 0.337ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- T17.OTCLK2 net (fanout=2540) 1.011 cmp_gn4124_core/clk_p
+ T17.OTCLK2 net (fanout=2661) 1.011 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.906ns (1.873ns logic, 1.033ns route)
(64.5% logic, 35.5% route)
@@ -7311,7 +7336,7 @@ Delay (fastest paths): 5.148ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- T17.OTCLK2 net (fanout=2540) 0.859 cmp_gn4124_core/clk_p
+ T17.OTCLK2 net (fanout=2661) 0.859 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.464ns (1.588ns logic, 0.876ns route)
(64.4% logic, 35.6% route)
@@ -7400,7 +7425,7 @@ Slack (slowest paths): 0.330ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- W20.OTCLK2 net (fanout=2540) 1.018 cmp_gn4124_core/clk_p
+ W20.OTCLK2 net (fanout=2661) 1.018 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.913ns (1.873ns logic, 1.040ns route)
(64.3% logic, 35.7% route)
@@ -7486,7 +7511,7 @@ Delay (fastest paths): 5.153ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- W20.OTCLK2 net (fanout=2540) 0.865 cmp_gn4124_core/clk_p
+ W20.OTCLK2 net (fanout=2661) 0.865 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.469ns (1.587ns logic, 0.882ns route)
(64.3% logic, 35.7% route)
@@ -7581,7 +7606,7 @@ Slack (slowest paths): 0.330ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- W20.OTCLK2 net (fanout=2540) 1.018 cmp_gn4124_core/clk_p
+ W20.OTCLK2 net (fanout=2661) 1.018 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.913ns (1.873ns logic, 1.040ns route)
(64.3% logic, 35.7% route)
@@ -7667,7 +7692,7 @@ Delay (fastest paths): 5.154ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- W20.OTCLK2 net (fanout=2540) 0.865 cmp_gn4124_core/clk_p
+ W20.OTCLK2 net (fanout=2661) 0.865 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.470ns (1.588ns logic, 0.882ns route)
(64.3% logic, 35.7% route)
@@ -7756,7 +7781,7 @@ Slack (slowest paths): 0.330ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- W19.OTCLK2 net (fanout=2540) 1.018 cmp_gn4124_core/clk_p
+ W19.OTCLK2 net (fanout=2661) 1.018 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.913ns (1.873ns logic, 1.040ns route)
(64.3% logic, 35.7% route)
@@ -7842,7 +7867,7 @@ Delay (fastest paths): 5.153ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- W19.OTCLK2 net (fanout=2540) 0.865 cmp_gn4124_core/clk_p
+ W19.OTCLK2 net (fanout=2661) 0.865 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.469ns (1.587ns logic, 0.882ns route)
(64.3% logic, 35.7% route)
@@ -7937,7 +7962,7 @@ Slack (slowest paths): 0.330ns (requirement - (clock arrival + clock path + dat
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- W19.OTCLK2 net (fanout=2540) 1.018 cmp_gn4124_core/clk_p
+ W19.OTCLK2 net (fanout=2661) 1.018 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.913ns (1.873ns logic, 1.040ns route)
(64.3% logic, 35.7% route)
@@ -8023,7 +8048,7 @@ Delay (fastest paths): 5.154ns (clock arrival + clock path + data path - uncert
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- W19.OTCLK2 net (fanout=2540) 0.865 cmp_gn4124_core/clk_p
+ W19.OTCLK2 net (fanout=2661) 0.865 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.470ns (1.588ns logic, 0.882ns route)
(64.3% logic, 35.7% route)
@@ -8315,7 +8340,7 @@ Slack (setup path): 0.408ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- E22.ICLK2 net (fanout=2540) 0.854 cmp_gn4124_core/clk_p
+ E22.ICLK2 net (fanout=2661) 0.854 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.458ns (1.587ns logic, 0.871ns route)
(64.6% logic, 35.4% route)
@@ -8454,7 +8479,7 @@ Slack (hold path): 0.271ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- E22.ICLK2 net (fanout=2540) 1.004 cmp_gn4124_core/clk_p
+ E22.ICLK2 net (fanout=2661) 1.004 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.899ns (1.873ns logic, 1.026ns route)
(64.6% logic, 35.4% route)
@@ -8552,7 +8577,7 @@ Slack (setup path): 0.409ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- E22.ICLK2 net (fanout=2540) 0.854 cmp_gn4124_core/clk_p
+ E22.ICLK2 net (fanout=2661) 0.854 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.459ns (1.588ns logic, 0.871ns route)
(64.6% logic, 35.4% route)
@@ -8645,7 +8670,7 @@ Slack (hold path): 0.271ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- E22.ICLK2 net (fanout=2540) 1.004 cmp_gn4124_core/clk_p
+ E22.ICLK2 net (fanout=2661) 1.004 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.899ns (1.873ns logic, 1.026ns route)
(64.6% logic, 35.4% route)
@@ -8697,7 +8722,7 @@ Slack (setup path): 0.421ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- K19.ICLK2 net (fanout=2540) 0.867 cmp_gn4124_core/clk_p
+ K19.ICLK2 net (fanout=2661) 0.867 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.471ns (1.587ns logic, 0.884ns route)
(64.2% logic, 35.8% route)
@@ -8836,7 +8861,7 @@ Slack (hold path): 0.254ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- K19.ICLK2 net (fanout=2540) 1.021 cmp_gn4124_core/clk_p
+ K19.ICLK2 net (fanout=2661) 1.021 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.916ns (1.873ns logic, 1.043ns route)
(64.2% logic, 35.8% route)
@@ -8891,7 +8916,7 @@ Slack (setup path): 0.422ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- K19.ICLK2 net (fanout=2540) 0.867 cmp_gn4124_core/clk_p
+ K19.ICLK2 net (fanout=2661) 0.867 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.472ns (1.588ns logic, 0.884ns route)
(64.2% logic, 35.8% route)
@@ -9027,7 +9052,7 @@ Slack (hold path): 0.254ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- K19.ICLK2 net (fanout=2540) 1.021 cmp_gn4124_core/clk_p
+ K19.ICLK2 net (fanout=2661) 1.021 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.916ns (1.873ns logic, 1.043ns route)
(64.2% logic, 35.8% route)
@@ -9079,7 +9104,7 @@ Slack (setup path): 0.425ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- M20.ICLK2 net (fanout=2540) 0.871 cmp_gn4124_core/clk_p
+ M20.ICLK2 net (fanout=2661) 0.871 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.475ns (1.587ns logic, 0.888ns route)
(64.1% logic, 35.9% route)
@@ -9218,7 +9243,7 @@ Slack (hold path): 0.250ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- M20.ICLK2 net (fanout=2540) 1.025 cmp_gn4124_core/clk_p
+ M20.ICLK2 net (fanout=2661) 1.025 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.920ns (1.873ns logic, 1.047ns route)
(64.1% logic, 35.9% route)
@@ -9273,7 +9298,7 @@ Slack (setup path): 0.426ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- M20.ICLK2 net (fanout=2540) 0.871 cmp_gn4124_core/clk_p
+ M20.ICLK2 net (fanout=2661) 0.871 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.476ns (1.588ns logic, 0.888ns route)
(64.1% logic, 35.9% route)
@@ -9409,7 +9434,7 @@ Slack (hold path): 0.250ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- M20.ICLK2 net (fanout=2540) 1.025 cmp_gn4124_core/clk_p
+ M20.ICLK2 net (fanout=2661) 1.025 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.920ns (1.873ns logic, 1.047ns route)
(64.1% logic, 35.9% route)
@@ -9461,7 +9486,7 @@ Slack (setup path): 0.385ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- G22.ICLK2 net (fanout=2540) 0.831 cmp_gn4124_core/clk_p
+ G22.ICLK2 net (fanout=2661) 0.831 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.435ns (1.587ns logic, 0.848ns route)
(65.2% logic, 34.8% route)
@@ -9600,7 +9625,7 @@ Slack (hold path): 0.297ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- G22.ICLK2 net (fanout=2540) 0.978 cmp_gn4124_core/clk_p
+ G22.ICLK2 net (fanout=2661) 0.978 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.873ns (1.873ns logic, 1.000ns route)
(65.2% logic, 34.8% route)
@@ -9655,7 +9680,7 @@ Slack (setup path): 0.386ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- G22.ICLK2 net (fanout=2540) 0.831 cmp_gn4124_core/clk_p
+ G22.ICLK2 net (fanout=2661) 0.831 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.436ns (1.588ns logic, 0.848ns route)
(65.2% logic, 34.8% route)
@@ -9791,7 +9816,7 @@ Slack (hold path): 0.297ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- G22.ICLK2 net (fanout=2540) 0.978 cmp_gn4124_core/clk_p
+ G22.ICLK2 net (fanout=2661) 0.978 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.873ns (1.873ns logic, 1.000ns route)
(65.2% logic, 34.8% route)
@@ -9843,7 +9868,7 @@ Slack (setup path): 0.400ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- L18.ICLK2 net (fanout=2540) 0.846 cmp_gn4124_core/clk_p
+ L18.ICLK2 net (fanout=2661) 0.846 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.450ns (1.587ns logic, 0.863ns route)
(64.8% logic, 35.2% route)
@@ -9982,7 +10007,7 @@ Slack (hold path): 0.280ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- L18.ICLK2 net (fanout=2540) 0.995 cmp_gn4124_core/clk_p
+ L18.ICLK2 net (fanout=2661) 0.995 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.890ns (1.873ns logic, 1.017ns route)
(64.8% logic, 35.2% route)
@@ -10037,7 +10062,7 @@ Slack (setup path): 0.401ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- L18.ICLK2 net (fanout=2540) 0.846 cmp_gn4124_core/clk_p
+ L18.ICLK2 net (fanout=2661) 0.846 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.451ns (1.588ns logic, 0.863ns route)
(64.8% logic, 35.2% route)
@@ -10173,7 +10198,7 @@ Slack (hold path): 0.280ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- L18.ICLK2 net (fanout=2540) 0.995 cmp_gn4124_core/clk_p
+ L18.ICLK2 net (fanout=2661) 0.995 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.890ns (1.873ns logic, 1.017ns route)
(64.8% logic, 35.2% route)
@@ -10225,7 +10250,7 @@ Slack (setup path): 0.425ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- M18.ICLK2 net (fanout=2540) 0.871 cmp_gn4124_core/clk_p
+ M18.ICLK2 net (fanout=2661) 0.871 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.475ns (1.587ns logic, 0.888ns route)
(64.1% logic, 35.9% route)
@@ -10364,7 +10389,7 @@ Slack (hold path): 0.250ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- M18.ICLK2 net (fanout=2540) 1.025 cmp_gn4124_core/clk_p
+ M18.ICLK2 net (fanout=2661) 1.025 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.920ns (1.873ns logic, 1.047ns route)
(64.1% logic, 35.9% route)
@@ -10419,7 +10444,7 @@ Slack (setup path): 0.426ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- M18.ICLK2 net (fanout=2540) 0.871 cmp_gn4124_core/clk_p
+ M18.ICLK2 net (fanout=2661) 0.871 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.476ns (1.588ns logic, 0.888ns route)
(64.1% logic, 35.9% route)
@@ -10555,7 +10580,7 @@ Slack (hold path): 0.250ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- M18.ICLK2 net (fanout=2540) 1.025 cmp_gn4124_core/clk_p
+ M18.ICLK2 net (fanout=2661) 1.025 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.920ns (1.873ns logic, 1.047ns route)
(64.1% logic, 35.9% route)
@@ -10607,7 +10632,7 @@ Slack (setup path): 0.421ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- K20.ICLK2 net (fanout=2540) 0.867 cmp_gn4124_core/clk_p
+ K20.ICLK2 net (fanout=2661) 0.867 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.471ns (1.587ns logic, 0.884ns route)
(64.2% logic, 35.8% route)
@@ -10746,7 +10771,7 @@ Slack (hold path): 0.254ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- K20.ICLK2 net (fanout=2540) 1.021 cmp_gn4124_core/clk_p
+ K20.ICLK2 net (fanout=2661) 1.021 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.916ns (1.873ns logic, 1.043ns route)
(64.2% logic, 35.8% route)
@@ -10801,7 +10826,7 @@ Slack (setup path): 0.422ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- K20.ICLK2 net (fanout=2540) 0.867 cmp_gn4124_core/clk_p
+ K20.ICLK2 net (fanout=2661) 0.867 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.472ns (1.588ns logic, 0.884ns route)
(64.2% logic, 35.8% route)
@@ -10937,7 +10962,7 @@ Slack (hold path): 0.254ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- K20.ICLK2 net (fanout=2540) 1.021 cmp_gn4124_core/clk_p
+ K20.ICLK2 net (fanout=2661) 1.021 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.916ns (1.873ns logic, 1.043ns route)
(64.2% logic, 35.8% route)
@@ -10989,7 +11014,7 @@ Slack (setup path): 0.435ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- J18.ICLK2 net (fanout=2540) 0.881 cmp_gn4124_core/clk_p
+ J18.ICLK2 net (fanout=2661) 0.881 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.485ns (1.587ns logic, 0.898ns route)
(63.9% logic, 36.1% route)
@@ -11128,7 +11153,7 @@ Slack (hold path): 0.238ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- J18.ICLK2 net (fanout=2540) 1.037 cmp_gn4124_core/clk_p
+ J18.ICLK2 net (fanout=2661) 1.037 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.932ns (1.873ns logic, 1.059ns route)
(63.9% logic, 36.1% route)
@@ -11226,7 +11251,7 @@ Slack (setup path): 0.436ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- J18.ICLK2 net (fanout=2540) 0.881 cmp_gn4124_core/clk_p
+ J18.ICLK2 net (fanout=2661) 0.881 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.486ns (1.588ns logic, 0.898ns route)
(63.9% logic, 36.1% route)
@@ -11319,7 +11344,7 @@ Slack (hold path): 0.238ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- J18.ICLK2 net (fanout=2540) 1.037 cmp_gn4124_core/clk_p
+ J18.ICLK2 net (fanout=2661) 1.037 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.932ns (1.873ns logic, 1.059ns route)
(63.9% logic, 36.1% route)
@@ -11371,7 +11396,7 @@ Slack (setup path): 0.439ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- G19.ICLK2 net (fanout=2540) 0.885 cmp_gn4124_core/clk_p
+ G19.ICLK2 net (fanout=2661) 0.885 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.489ns (1.587ns logic, 0.902ns route)
(63.8% logic, 36.2% route)
@@ -11510,7 +11535,7 @@ Slack (hold path): 0.234ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- G19.ICLK2 net (fanout=2540) 1.041 cmp_gn4124_core/clk_p
+ G19.ICLK2 net (fanout=2661) 1.041 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.936ns (1.873ns logic, 1.063ns route)
(63.8% logic, 36.2% route)
@@ -11608,7 +11633,7 @@ Slack (setup path): 0.440ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- G19.ICLK2 net (fanout=2540) 0.885 cmp_gn4124_core/clk_p
+ G19.ICLK2 net (fanout=2661) 0.885 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.490ns (1.588ns logic, 0.902ns route)
(63.8% logic, 36.2% route)
@@ -11701,7 +11726,7 @@ Slack (hold path): 0.234ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- G19.ICLK2 net (fanout=2540) 1.041 cmp_gn4124_core/clk_p
+ G19.ICLK2 net (fanout=2661) 1.041 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.936ns (1.873ns logic, 1.063ns route)
(63.8% logic, 36.2% route)
@@ -11753,7 +11778,7 @@ Slack (setup path): 0.383ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- K15.ICLK2 net (fanout=2540) 0.829 cmp_gn4124_core/clk_p
+ K15.ICLK2 net (fanout=2661) 0.829 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.433ns (1.587ns logic, 0.846ns route)
(65.2% logic, 34.8% route)
@@ -11892,7 +11917,7 @@ Slack (hold path): 0.299ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- K15.ICLK2 net (fanout=2540) 0.976 cmp_gn4124_core/clk_p
+ K15.ICLK2 net (fanout=2661) 0.976 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.871ns (1.873ns logic, 0.998ns route)
(65.2% logic, 34.8% route)
@@ -11990,7 +12015,7 @@ Slack (setup path): 0.384ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- K15.ICLK2 net (fanout=2540) 0.829 cmp_gn4124_core/clk_p
+ K15.ICLK2 net (fanout=2661) 0.829 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.434ns (1.588ns logic, 0.846ns route)
(65.2% logic, 34.8% route)
@@ -12083,7 +12108,7 @@ Slack (hold path): 0.299ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- K15.ICLK2 net (fanout=2540) 0.976 cmp_gn4124_core/clk_p
+ K15.ICLK2 net (fanout=2661) 0.976 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.871ns (1.873ns logic, 0.998ns route)
(65.2% logic, 34.8% route)
@@ -12135,7 +12160,7 @@ Slack (setup path): 0.423ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- H17.ICLK2 net (fanout=2540) 0.869 cmp_gn4124_core/clk_p
+ H17.ICLK2 net (fanout=2661) 0.869 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.473ns (1.587ns logic, 0.886ns route)
(64.2% logic, 35.8% route)
@@ -12274,7 +12299,7 @@ Slack (hold path): 0.252ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- H17.ICLK2 net (fanout=2540) 1.023 cmp_gn4124_core/clk_p
+ H17.ICLK2 net (fanout=2661) 1.023 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.918ns (1.873ns logic, 1.045ns route)
(64.2% logic, 35.8% route)
@@ -12372,7 +12397,7 @@ Slack (setup path): 0.424ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- H17.ICLK2 net (fanout=2540) 0.869 cmp_gn4124_core/clk_p
+ H17.ICLK2 net (fanout=2661) 0.869 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.474ns (1.588ns logic, 0.886ns route)
(64.2% logic, 35.8% route)
@@ -12465,7 +12490,7 @@ Slack (hold path): 0.252ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- H17.ICLK2 net (fanout=2540) 1.023 cmp_gn4124_core/clk_p
+ H17.ICLK2 net (fanout=2661) 1.023 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.918ns (1.873ns logic, 1.045ns route)
(64.2% logic, 35.8% route)
@@ -12517,7 +12542,7 @@ Slack (setup path): 0.439ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- G20.ICLK2 net (fanout=2540) 0.885 cmp_gn4124_core/clk_p
+ G20.ICLK2 net (fanout=2661) 0.885 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.489ns (1.587ns logic, 0.902ns route)
(63.8% logic, 36.2% route)
@@ -12656,7 +12681,7 @@ Slack (hold path): 0.234ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- G20.ICLK2 net (fanout=2540) 1.041 cmp_gn4124_core/clk_p
+ G20.ICLK2 net (fanout=2661) 1.041 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.936ns (1.873ns logic, 1.063ns route)
(63.8% logic, 36.2% route)
@@ -12754,7 +12779,7 @@ Slack (setup path): 0.440ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- G20.ICLK2 net (fanout=2540) 0.885 cmp_gn4124_core/clk_p
+ G20.ICLK2 net (fanout=2661) 0.885 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.490ns (1.588ns logic, 0.902ns route)
(63.8% logic, 36.2% route)
@@ -12847,7 +12872,7 @@ Slack (hold path): 0.234ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- G20.ICLK2 net (fanout=2540) 1.041 cmp_gn4124_core/clk_p
+ G20.ICLK2 net (fanout=2661) 1.041 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.936ns (1.873ns logic, 1.063ns route)
(63.8% logic, 36.2% route)
@@ -12899,7 +12924,7 @@ Slack (setup path): 0.382ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- F22.ICLK2 net (fanout=2540) 0.828 cmp_gn4124_core/clk_p
+ F22.ICLK2 net (fanout=2661) 0.828 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.432ns (1.587ns logic, 0.845ns route)
(65.3% logic, 34.7% route)
@@ -13038,7 +13063,7 @@ Slack (hold path): 0.301ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- F22.ICLK2 net (fanout=2540) 0.974 cmp_gn4124_core/clk_p
+ F22.ICLK2 net (fanout=2661) 0.974 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.869ns (1.873ns logic, 0.996ns route)
(65.3% logic, 34.7% route)
@@ -13136,7 +13161,7 @@ Slack (setup path): 0.383ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- F22.ICLK2 net (fanout=2540) 0.828 cmp_gn4124_core/clk_p
+ F22.ICLK2 net (fanout=2661) 0.828 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.433ns (1.588ns logic, 0.845ns route)
(65.3% logic, 34.7% route)
@@ -13229,7 +13254,7 @@ Slack (hold path): 0.301ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- F22.ICLK2 net (fanout=2540) 0.974 cmp_gn4124_core/clk_p
+ F22.ICLK2 net (fanout=2661) 0.974 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.869ns (1.873ns logic, 0.996ns route)
(65.3% logic, 34.7% route)
@@ -13281,7 +13306,7 @@ Slack (setup path): 0.435ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- H19.ICLK2 net (fanout=2540) 0.881 cmp_gn4124_core/clk_p
+ H19.ICLK2 net (fanout=2661) 0.881 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.485ns (1.587ns logic, 0.898ns route)
(63.9% logic, 36.1% route)
@@ -13420,7 +13445,7 @@ Slack (hold path): 0.238ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- H19.ICLK2 net (fanout=2540) 1.037 cmp_gn4124_core/clk_p
+ H19.ICLK2 net (fanout=2661) 1.037 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.932ns (1.873ns logic, 1.059ns route)
(63.9% logic, 36.1% route)
@@ -13518,7 +13543,7 @@ Slack (setup path): 0.436ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- H19.ICLK2 net (fanout=2540) 0.881 cmp_gn4124_core/clk_p
+ H19.ICLK2 net (fanout=2661) 0.881 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.486ns (1.588ns logic, 0.898ns route)
(63.9% logic, 36.1% route)
@@ -13611,7 +13636,7 @@ Slack (hold path): 0.238ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- H19.ICLK2 net (fanout=2540) 1.037 cmp_gn4124_core/clk_p
+ H19.ICLK2 net (fanout=2661) 1.037 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.932ns (1.873ns logic, 1.059ns route)
(63.9% logic, 36.1% route)
@@ -13663,7 +13688,7 @@ Slack (setup path): 0.415ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- K22.ICLK2 net (fanout=2540) 0.861 cmp_gn4124_core/clk_p
+ K22.ICLK2 net (fanout=2661) 0.861 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.465ns (1.587ns logic, 0.878ns route)
(64.4% logic, 35.6% route)
@@ -13802,7 +13827,7 @@ Slack (hold path): 0.261ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- K22.ICLK2 net (fanout=2540) 1.014 cmp_gn4124_core/clk_p
+ K22.ICLK2 net (fanout=2661) 1.014 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.909ns (1.873ns logic, 1.036ns route)
(64.4% logic, 35.6% route)
@@ -13857,7 +13882,7 @@ Slack (setup path): 0.416ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- K22.ICLK2 net (fanout=2540) 0.861 cmp_gn4124_core/clk_p
+ K22.ICLK2 net (fanout=2661) 0.861 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.466ns (1.588ns logic, 0.878ns route)
(64.4% logic, 35.6% route)
@@ -13993,7 +14018,7 @@ Slack (hold path): 0.261ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- K22.ICLK2 net (fanout=2540) 1.014 cmp_gn4124_core/clk_p
+ K22.ICLK2 net (fanout=2661) 1.014 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.909ns (1.873ns logic, 1.036ns route)
(64.4% logic, 35.6% route)
@@ -14045,7 +14070,7 @@ Slack (setup path): 0.376ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- K17.ICLK2 net (fanout=2540) 0.822 cmp_gn4124_core/clk_p
+ K17.ICLK2 net (fanout=2661) 0.822 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.426ns (1.587ns logic, 0.839ns route)
(65.4% logic, 34.6% route)
@@ -14184,7 +14209,7 @@ Slack (hold path): 0.308ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- K17.ICLK2 net (fanout=2540) 0.967 cmp_gn4124_core/clk_p
+ K17.ICLK2 net (fanout=2661) 0.967 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.862ns (1.873ns logic, 0.989ns route)
(65.4% logic, 34.6% route)
@@ -14282,7 +14307,7 @@ Slack (setup path): 0.377ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- K17.ICLK2 net (fanout=2540) 0.822 cmp_gn4124_core/clk_p
+ K17.ICLK2 net (fanout=2661) 0.822 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.427ns (1.588ns logic, 0.839ns route)
(65.4% logic, 34.6% route)
@@ -14375,7 +14400,7 @@ Slack (hold path): 0.308ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- K17.ICLK2 net (fanout=2540) 0.967 cmp_gn4124_core/clk_p
+ K17.ICLK2 net (fanout=2661) 0.967 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.862ns (1.873ns logic, 0.989ns route)
(65.4% logic, 34.6% route)
@@ -14427,7 +14452,7 @@ Slack (setup path): 1.176ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- L22.ICLK1 net (fanout=2540) 0.866 cmp_gn4124_core/clk_p
+ L22.ICLK1 net (fanout=2661) 0.866 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.470ns (1.587ns logic, 0.883ns route)
(64.3% logic, 35.7% route)
@@ -14473,7 +14498,7 @@ Slack (hold path): 1.198ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- L22.ICLK1 net (fanout=2540) 1.019 cmp_gn4124_core/clk_p
+ L22.ICLK1 net (fanout=2661) 1.019 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.914ns (1.873ns logic, 1.041ns route)
(64.3% logic, 35.7% route)
@@ -14525,7 +14550,7 @@ Slack (setup path): 1.176ns (requirement - (data path - clock path - clock a
BUFGMUX_X2Y10.O Tgi0o 0.117 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- M22.ICLK1 net (fanout=2540) 0.866 cmp_gn4124_core/clk_p
+ M22.ICLK1 net (fanout=2661) 0.866 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.470ns (1.587ns logic, 0.883ns route)
(64.3% logic, 35.7% route)
@@ -14571,7 +14596,7 @@ Slack (hold path): 1.198ns (requirement - (clock path + clock arrival + unc
BUFGMUX_X2Y10.O Tgi0o 0.212 cmp_gn4124_core/CLK_bufg
cmp_gn4124_core/CLK_bufg.GCLKMUX
cmp_gn4124_core/CLK_bufg
- M22.ICLK1 net (fanout=2540) 1.019 cmp_gn4124_core/clk_p
+ M22.ICLK1 net (fanout=2661) 1.019 cmp_gn4124_core/clk_p
------------------------------------------------- ---------------------------
Total 2.914ns (1.873ns logic, 1.041ns route)
(64.3% logic, 35.7% route)
@@ -14755,8 +14780,8 @@ Clock to Setup on destination clock P2L_CLKn
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
-P2L_CLKn | 5.673| | | |
-P2L_CLKp | 5.673| | | |
+P2L_CLKn | 5.647| | | |
+P2L_CLKp | 5.647| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock P2L_CLKp
@@ -14764,8 +14789,8 @@ Clock to Setup on destination clock P2L_CLKp
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
-P2L_CLKn | 5.673| | | |
-P2L_CLKp | 5.673| | | |
+P2L_CLKn | 5.647| | | |
+P2L_CLKp | 5.647| | | |
---------------+---------+---------+---------+---------+
COMP "P2L_DATA<0>" OFFSET = IN 1.2 ns VALID 1.6 ns BEFORE COMP "P2L_CLKp" HIGH;
@@ -15466,13 +15491,13 @@ L2P_VALID | 6.122| 0.000|
Timing summary:
---------------
-Timing errors: 65 Score: 22013 (Setup/Max: 22013, Hold: 0)
+Timing errors: 98 Score: 22331 (Setup/Max: 22331, Hold: 0)
-Constraints cover 36448 paths, 4 nets, and 14332 connections
+Constraints cover 36436 paths, 4 nets, and 14482 connections
Design statistics:
- Minimum period: 12.930ns{1} (Maximum frequency: 77.340MHz)
- Maximum path delay from/to any node: 4.655ns
+ Minimum period: 15.303ns{1} (Maximum frequency: 65.347MHz)
+ Maximum path delay from/to any node: 5.537ns
Maximum net delay: 0.022ns
Minimum input required time before clock: 0.824ns
Minimum output required time after clock: 6.263ns
@@ -15481,14 +15506,14 @@ Design statistics:
------------------------------------Footnotes-----------------------------------
1) The minimum period statistic assumes all single cycle delays.
-Analysis completed Fri Nov 5 15:18:58 2010
+Analysis completed Wed Nov 10 20:13:03 2010
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
-Peak Memory Usage: 191 MB
+Peak Memory Usage: 193 MB